AD8450 (Rev. B) - Analog Devices [PDF]

Precision Analog Front End and Controller for Battery Test/Formation Systems AD8450

Data Sheet FEATURES

GENERAL DESCRIPTION

Integrated constant current and voltage modes with automatic switchover Charge and discharge modes Precision voltage and current measurement Integrated precision control feedback blocks Precision interface to PWM or linear power converters Programmable gain settings Current sense gains: 26, 66, 133, and 200 Voltage sense gains: 0.2, 0.27, 0.4, and 0.8 Programmable OVP and OCP fault detection Current sharing and balancing Excellent ac and dc performance Maximum offset voltage drift: 0.6 µV/°C Maximum gain drift: 3 ppm/°C Low current sense amplifier input voltage noise: ≤9 nV/√Hz Current sense CMRR: 126 dB minimum (gain = 200) TTL compliant logic

The AD8450 is a precision analog front end and controller for testing and monitoring battery cells. A precision programmable gain instrumentation amplifier (PGIA) measures the battery charge/discharge current, and a programmable gain difference amplifier (PGDA) measures the battery voltage (see Figure 1). Internal laser trimmed resistor networks set the gains for the PGIA and the PGDA, optimizing the performance of the AD8450 over the rated temperature range. PGIA gains are 26, 66, 133, and 200. PGDA gains are 0.2, 0.27, 0.4, and 0.8.

APPLICATIONS

The AD8450 includes resistor programmable overvoltage and overcurrent detection and current sharing circuitry. Current sharing is used to balance the output current of multiple bridged channels.

Voltages at the ISET and VSET inputs set the desired constant current (CC) and constant voltage (CV) values. CC to CV switching is automatic and transparent to the system. A TTL logic level input, MODE, selects the charge or discharge mode (high for charge, low for discharge). An analog output, VCTRL, interfaces directly with the Analog Devices, Inc., ADP1972 PWM controller.

Battery cell formation and testing Battery module testing

The AD8450 simplifies designs by providing excellent accuracy, performance over temperature, flexibility with functionality, and overall reliability in a space-saving package. The AD8450 is available in an 80-lead, 14 mm × 14 mm × 1 mm LQFP package and is rated for an operating temperature of −40°C to +85°C.

FUNCTIONAL BLOCK DIAGRAM ISREFH/ ISREFL

ISMEA

ISET

IVE0/ IVE1

VINT

AD8450 GAIN NETWORK AND MUX

CONSTANT CURRENT LOOP FILTER

26, 66, 133, 200

CURRENT SHARING

CURRENT SENSE PGIA (CHARGE/ DISCHARGE) SWITCHING

MODE VOLTAGE SENSE PGDA GAIN NETWORK

IMAX VCLP

ISVN

BVPx

CSH

0.2, 0.27, 0.4, 0.8

CONSTANT VOLTAGE LOOP FILTER

BVNx

BVREFH/ BVREFL

BVMEA

VSET

VVE0/ VVE1

VVP0

VSETBF VINT

VCTRL

1×

VCLN VOLTAGE REFERENCE

VREF

FAULT DETECTION

FAULT

OVPS/ OVPR

OCPS/ OCPR

11966-001

ISVP

Figure 1.

Rev. B

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AD8450

Data Sheet

TABLE OF CONTENTS Features .............................................................................................. 1

Overcurrent and Overvoltage Comparators........................... 27

Applications ....................................................................................... 1

Current Sharing Bus and IMAX Output ................................. 28

General Description ......................................................................... 1

Applications Information .............................................................. 29

Functional Block Diagram .............................................................. 1

Functional Description .............................................................. 29

Revision History ............................................................................... 2

Power Supply Connections ....................................................... 29

Specifications..................................................................................... 3

Power Supply Sequencing ......................................................... 29

Absolute Maximum Ratings ............................................................ 8

Power-On Sequence ................................................................... 29

Thermal Resistance ...................................................................... 8

Power-Off Sequence ................................................................... 30

ESD Caution .................................................................................. 8

PGIA Connections ..................................................................... 30

Pin Configuration and Function Descriptions ............................. 9

PGDA Connections ................................................................... 31

Typical Performance Characteristics ........................................... 11 PGIA Characteristics ................................................................. 11

Battery Current and Voltage Control Inputs (ISET and VSET) ....................................................................................................... 31

PGDA Characteristics ................................................................ 13

Loop Filter Amplifiers ............................................................... 32

CC and CV Loop Filter Amplifiers, Uncommitted Op Amp, and VSET Buffer ......................................................................... 15

Connecting to a PWM Controller (VCTRL Pin) ...................... 32

VINT Buffer ................................................................................ 17

Step by Step Design Example .................................................... 32

Current Sharing Amplifier ........................................................ 18

Additional Information ............................................................. 33

Comparators................................................................................ 19

Evaluation Board ............................................................................ 34

Reference Characteristics .......................................................... 20

Introduction ................................................................................ 34

Theory of Operation ...................................................................... 21

Features and Tests....................................................................... 34

Introduction ................................................................................ 21

Testing the AD8450-EVALZ ..................................................... 34

Programmable Gain Instrumentation Amplifier (PGIA) ..... 23

Using the AD8450 ...................................................................... 36

Programmable Gain Difference Amplifier (PGDA) .............. 24

Schematic and Artwork ............................................................. 37

CC and CV Loop Filter Amplifiers .......................................... 24

Outline Dimensions ....................................................................... 41

Compensation ............................................................................. 26

Ordering Guide .......................................................................... 41

Overvoltage and Overcurrent Comparators........................... 32

VINT Buffer ................................................................................ 26 MODE Pin, Charge and Discharge Control ........................... 26 7/14—Rev. 0 to Rev. A

REVISION HISTORY 8/15—Rev. A to Rev. B Changes to Table 2 ............................................................................ 8 Added Power Supply Sequencing Section and Power-On Sequence Section ............................................................................ 29 Added Power-Off Sequence .......................................................... 30 Added Additional Information Section ....................................... 33 Changes to Step 4: Determine the Control Voltage for the CC Loop, the Shunt Resistor, and the PGIA Gain Section .............. 33

Changes to General Description .....................................................1 Changes to Pin 39 and Pin 80 Descriptions ................................ 10 Changes to Introduction Section and Figure 50 ........................ 22 Changes to Figure 52...................................................................... 24 Changes to Figure 55...................................................................... 26 Changes to Current Sharing Bus and IMAX Output Section .. 27 Changes to Figure 58...................................................................... 28 Changes to Figure 59...................................................................... 30 Changes to Evaluation Board Section.......................................... 33 1/14—Revision 0: Initial Version

Rev. B | Page 2 of 41

Data Sheet

AD8450

SPECIFICATIONS AVCC = +25 V, AVEE = −5 V; AVCC = +15 V, AVEE = −15 V; DVCC = +5 V; PGIA gain = 26, 66, 133, or 200; PGDA gain = 0.2, 0.27, 0.4, or 0.8; TA = 25°C, unless otherwise noted. Table 1. Parameter CURRENT SENSE PGIA Internal Fixed Gains Gain Error Gain Drift Gain Nonlinearity Offset Voltage (RTI) Offset Voltage Drift Input Bias Current Temperature Coefficient Input Offset Current Temperature Coefficient Input Common-Mode Voltage Range Over Temperature Overvoltage Input Range Differential Input Impedance Input Common-Mode Impedance Output Voltage Swing Over Temperature Capacitive Load Drive Short-Circuit Current Reference Input Voltage Range Reference Input Bias Current Output Voltage Level Shift Maximum Scale Factor CMRR Gain = 26 Gain = 66 Gain = 133 Gain = 200 Temperature Coefficient PSRR Gain = 26 Gain = 66 Gain = 133 Gain = 200 Voltage Noise Gain = 26 Gain = 66 Gain = 133 Gain = 200 Voltage Noise, Peak-to-Peak Current Noise Current Noise, Peak-to-Peak

Test Conditions/Comments

Min

Typ

Max

Unit

±0.1 3 3 +110

V/V % ppm/°C ppm µV

26, 66, 133, 200 VISMEA = ±10 V TA = TMIN to TMAX VISMEA = ±10 V, RL = 2 kΩ Gain = 200, ISREFH and ISREFL pins grounded TA = TMIN to TMAX

−110

15 TA = TMIN to TMAX TA = TMIN to TMAX VISVP − VISVN = 0 V TA = TMIN to TMAX

AVEE + 2.3 AVEE + 2.6 AVCC − 55

0.6 30 150 2 10 AVCC − 2.4 AVCC − 2.6 AVEE + 55

150 150 AVEE + 1.5 AVEE + 1.7

TA = TMIN to TMAX

AVCC − 1.2 AVCC − 1.4 1000 40

ISREFH and ISREFL pins tied together VISVP = VISVN = 0 V ISREFL pin grounded ISREFH pin connected to VREF pin VISMEA/VISREFH ΔVCM = 20 V

AVEE

AVCC 5

17 6.8

20 8

23 9.2

mV mV/V

0.01

dB dB dB dB µV/V/°C

108 116 122 126 TA = TMIN to TMAX ΔVS = 20 V 108 116 122 126

µV/°C nA pA/°C nA pA/°C V V V GΩ GΩ V V pF mA V µA

122 130 136 140

dB dB dB dB

9 8 7 7 0.2 80 5

nV/√Hz nV/√Hz nV/√Hz nV/√Hz µV p-p fA/√Hz pA p-p

f = 1 kHz

f = 0.1 Hz to 10 Hz, all fixed gains f = 1 kHz f = 0.1 Hz to 10 Hz

Rev. B | Page 3 of 41

AD8450 Parameter Small Signal −3 dB Bandwidth Gain = 26 Gain = 66 Gain = 133 Gain = 200 Slew Rate VOLTAGE SENSE PGDA Internal Fixed Gains Gain Error Gain Drift Gain Nonlinearity Offset Voltage (RTO) Offset Voltage Drift Differential Input Voltage Range

Input Common-Mode Voltage Range

Differential Input Impedance Gain = 0.2 Gain = 0.27 Gain = 0.4 Gain = 0.8 Input Common-Mode Impedance Gain = 0.2 Gain = 0.27 Gain = 0.4 Gain = 0.8 Output Voltage Swing Over Temperature Capacitive Load Drive Short-Circuit Current Reference Input Voltage Range Output Voltage Level Shift Maximum Scale Factor CMRR Temperature Coefficient PSRR Output Voltage Noise Gain = 0.2 Gain = 0.27 Gain = 0.4 Gain = 0.8 Voltage Noise, Peak-to-Peak Gain = 0.2 Gain = 0.27 Gain = 0.4 Gain = 0.8

Data Sheet Test Conditions/Comments

Min

Typ

Max

1.5 630 330 220 5

ΔVISMEA = 10 V

MHz kHz kHz kHz V/µs

0.2, 0.27, 0.4, 0.8 VIN = ±10 V TA = TMIN to TMAX VBVMEA = ±10 V, RL = 2 kΩ BVREFH and BVREFL pins grounded TA = TMIN to TMAX Gain = 0.8, VBVN0 = 0 V, VBVREFL = 0 V AVCC = +15 V, AVEE = −15 V AVCC = +25 V, AVEE = −5 V Gain = 0.8, VBVMEA = 0 V AVCC = +15 V, AVEE = −15 V AVCC = +25 V, AVEE = −5 V

±0.1 3 3 500 4

V/V % ppm/°C ppm µV µV/°C

−16 −4

+16 +29

V V

−27 −7

+27 +50

V V

800 600 400 200

kΩ kΩ kΩ kΩ

240 190 140 90

kΩ kΩ kΩ kΩ V V pF mA V

AVEE + 1.5 AVEE + 1.7

TA = TMIN to TMAX

AVCC − 1.5 AVCC − 1.7 1000 30

BVREFH and BVREFL pins tied together BVREFL pin grounded BVREFH pin connected to VREF pin VBVMEA/VBVREFH ΔVCM = 10 V, all fixed gains, RTO TA = TMIN to TMAX ΔVS = 20 V, all fixed gains, RTO f = 1 kHz, RTI

Unit

AVEE 4.5 1.8 80

AVCC 5 2

5.5 2.2 0.05

100

mV mV/V dB µV/V/°C dB

325 250 180 105

nV/√Hz nV/√Hz nV/√Hz nV/√Hz

6 5 3 2

µV p-p µV p-p µV p-p µV p-p

f = 0.1 Hz to 10 Hz, RTI

Rev. B | Page 4 of 41

Data Sheet Parameter Small Signal −3 dB Bandwidth Gain = 0.2 Gain = 0.27 Gain = 0.4 Gain = 0.8 Slew Rate CONSTANT CURRENT AND CONSTANT VOLTAGE LOOP FILTER AMPLIFIERS Offset Voltage Offset Voltage Drift Input Bias Current Over Temperature Input Common-Mode Voltage Range Output Voltage Swing Over Temperature Closed-Loop Output Impedance Capacitive Load Drive Source Short-Circuit Current Sink Short-Circuit Current Open-Loop Gain CMRR PSRR Voltage Noise Voltage Noise, Peak-to-Peak Current Noise Current Noise, Peak-to-Peak Small Signal Gain Bandwidth Product Slew Rate CC to CV Transition Time UNCOMMITTED OP AMP Offset Voltage Offset Voltage Drift Input Bias Current Over Temperature Input Common-Mode Voltage Range Output Voltage Swing Over Temperature Closed-Loop Output Impedance Capacitive Load Drive Short-Circuit Current Open-Loop Gain CMRR PSRR Voltage Noise Voltage Noise, Peak-to-Peak Current Noise Current Noise, Peak-to-Peak Small Signal Gain Bandwidth Product Slew Rate

AD8450 Test Conditions/Comments

Min

Typ

Max

420 730 940 1000 0.8

TA = TMIN to TMAX VVCLN = AVEE + 1 V, VVCLP = AVCC − 1 V TA = TMIN to TMAX

kHz kHz kHz kHz V/µs

150 0.6 +5 +5 AVCC − 1.8 AVCC − 1 AVCC − 1

TA = TMIN to TMAX −5 −5 AVEE + 1.5 AVEE + 1.5 AVEE + 1.7 0.01

1000 1 40 140 ΔVCM = 10 V ΔVS = 20 V f = 1 kHz f = 0.1 Hz to 10 Hz f = 1 kHz f = 0.1 Hz to 10 Hz

100 100 10 0.3 80 5 3 1 1.5

ΔVVINT = 10 V

150 0.6 +5 +5 AVCC − 1.8 AVCC − 1.5 AVCC − 1.5

TA = TMIN to TMAX −5 −5 AVEE + 1.5 AVEE + 1.5 AVEE + 1.7

TA = TMIN to TMAX

TA = TMIN to TMAX

0.01 1000 40 140

RL = 2 kΩ ΔVCM = 10 V ΔVS = 20 V f = 1 kHz f = 0.1 Hz to 10 Hz f = 1 kHz f = 0.1 Hz to 10 Hz

100 100 10 0.3 80 5 3 1

ΔVOAVO = 10 V

Rev. B | Page 5 of 41

Unit

µV µV/°C nA nA V V V Ω pF mA mA dB dB dB nV/√Hz µV p-p fA/√Hz pA p-p MHz V/μs µs µV µV/°C nA nA V V V Ω pF mA dB dB dB nV/√Hz µV p-p fA/√Hz pA p-p MHz V/µs

AD8450 Parameter CURRENT SHARING BUS AMPLIFIER Nominal Gain Offset Voltage Offset Voltage Drift Output Voltage Swing Over Temperature Capacitive Load Drive Source Short-Circuit Current Sink Short-Circuit Current CMRR PSRR Voltage Noise Voltage Noise, Peak-to-Peak Small Signal −3 dB Bandwidth Slew Rate Transition Time CURRENT SHARING, VINT, AND CONSTANT VOLTAGE BUFFERS Nominal Gain Offset Voltage Offset Voltage Drift Input Bias Current Over Temperature Input Voltage Range Output Voltage Swing Current Sharing and Constant Voltage Buffers Over Temperature VINT Buffer Over Temperature Output Clamps Voltage Range VCLP Pin VCLN Pin Closed-Loop Output Impedance Capacitive Load Drive Short-Circuit Current PSRR Voltage Noise Voltage Noise, Peak-to-Peak Current Noise Current Noise, Peak-to-Peak Small Signal −3 dB Bandwidth Slew Rate OVERCURRENT AND OVERVOLTAGE FAULT COMPARATORS High Threshold Voltage Temperature Coefficient Low Threshold Voltage Temperature Coefficient Input Bias Current Input Voltage Range Differential Input Voltage Range

Data Sheet Test Conditions/Comments

Min

Typ

Max

1 150 0.6 AVCC − 1.5 AVCC − 1.7 1000

TA = TMIN to TMAX AVEE + 1.5 AVEE + 1.7

TA = TMIN to TMAX

40 0.5 ΔVCM = 10 V ΔVS = 20 V f = 1 kHz f = 0.1 Hz to 10 Hz

100 100 10 0.4 3 1 1.5

ΔVCS = 10 V

1 TA = TMIN to TMAX CV buffer only TA = TMIN to TMAX

TA = TMIN to TMAX TA = TMIN to TMAX VINT buffer only

V/V µV µV/°C V V pF mA mA dB dB nV/√Hz µV p-p MHz V/µs µs

−5 −5 AVEE + 1.5

150 0.6 +5 +5 AVCC − 1.8

V/V µV µV/°C nA nA V

AVEE + 1.5

AVCC − 1.5

V

AVEE + 1.7 VVCLN − 0.6 VVCLN − 0.6

AVCC − 1.5 VVCLP + 0.6 VVCLP + 0.6

V V V

VVCLN AVEE + 1

AVCC − 1 VVCLP

V V Ω pF mA dB nV/√Hz µV p-p fA/√Hz pA p-p MHz V/µs

1 1000 40 ΔVS = 20 V f = 1 kHz f = 0.1 Hz to 10 Hz f = 1 kHz, CV buffer only f = 0.1 Hz to 10 Hz

100 10 0.3 80 5 3 1

ΔVOUT = 10 V

With respect to OVPR and OCPR pins With respect to OVPR and OCPR pins

−45

OVPR, OCPR, OVPS, and OCPS pins

AVEE −7

Rev. B | Page 6 of 41

Unit

30 100 −30 −100 250

45

AVCC − 3 +7

mV µV/°C mV µV/°C nA V V

Data Sheet Parameter Fault Output Logic Levels Output Voltage High, VOH Output Voltage Low, VOL Propagation Delay Fault Rise Time Fault Fall Time VOLTAGE REFERENCE Nominal Output Voltage Output Voltage Error Temperature Drift Line Regulation Load Regulation Output Current, Sourcing Voltage Noise Voltage Noise, Peak-to-Peak DIGITAL INTERFACE, MODE INPUT Input Voltage High, VIH Input Voltage Low, VIL Mode Switching Time POWER SUPPLY Operating Voltage Range AVCC AVEE Analog Supply Range DVCC Quiescent Current AVCC AVEE DVCC TEMPERATURE RANGE For Specified Performance Operational

AD8450 Test Conditions/Comments FAULT pin (Pin 46) ILOAD = 200 µA ILOAD = 200 µA CLOAD = 10 pF CLOAD = 10 pF CLOAD = 10 pF

Min

Typ

4.5 0.5 500 150 150

With respect to AGND

2.5 ±1 10 40 400 10

TA = TMIN to TMAX ΔVS = 10 V ΔIVREF = 1 mA (source only) f = 1 kHz f = 0.1 Hz to 10 Hz MODE pin (Pin 39) With respect to DGND With respect to DGND

Max

100 5 2.0 DGND

AVCC − AVEE

7 6.5 40 −40 −55

Rev. B | Page 7 of 41

V V ns ns ns V % ppm/°C ppm/V ppm/mA mA nV/√Hz µV p-p

DVCC 0.8

V V ns

36 0 36 5

V V V V

10 10 70

mA mA µA

+85 +125

°C °C

500

5 −31 5 3

Unit

AD8450

Data Sheet

ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE

Table 2. Parameter Analog Supply Voltage (AVCC − AVEE) Digital Supply Voltage (DVCC − DGND) Maximum Voltage at Input Pins (ISVP, ISVN, BVPx, and BVNx) Minimum Voltage at Input Pins (ISVP, ISVN, BVPx, and BVNx) Maximum Voltage at All Input Pins, Except ISVP, ISVN, BVPx, and BVNx Minimum Voltage at All Input Pins, Except ISVP, ISVN, BVPx, and BVNx Maximum Digital Supply Voltage with Respect to the Positive Analog Supply (DVCC − AVCC) Minimum Digital Supply Voltage with Respect to the Negative Analog Supply (DVCC − AVEE) Maximum Digital Ground with Respect to the Positive Analog Supply (DGND − AVCC) Minimum Digital Ground with Respect to the Negative Analog Supply (DGND − AVEE) Maximum Analog Ground with Respect to the Positive Analog Supply (AGND − AVCC) Minimum Analog Ground with Respect to the Negative Analog Supply (AGND − AVEE) Maximum Analog Ground with Respect to the Digital Ground (AGND − DGND) Minimum Analog Ground with Respect to the Digital Ground (AGND − DGND) Operating Temperature Range Storage Temperature Range

Rating 36 V 36 V AVEE + 55 V AVCC − 55 V AVCC

The θJA value assumes a 4-layer JEDEC standard board with zero airflow. Table 3. Thermal Resistance Package Type 80-Lead LQFP

ESD CAUTION

AVEE +0.5 V −0.5 V +0.5 V −0.5 V +0.5 V −0.5 V +0.5 V −0.5 V −40°C to +85°C −65°C to +150°C

Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability.

Rev. B | Page 8 of 41

θJA 54.7

Unit °C/W

Data Sheet

AD8450

VINT

AVEE

IVE1

NC

IVE0

NC

ISET

OAVO

OAVN

AVCC

ISMEA

AVEE

VREF

ISREFH

AGND

ISREFLS

ISREFL

OAVP

CSH

IMAX

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61

60

VCLP

59

VCTRL

RGPS 3

58

VCLN

ISGP0 4

57

AVCC

ISGP0S 5

56

VINT

ISGP1 6

55

NC

ISGP1S 7

54

VVE1

ISVP 1 PIN 1

RGP 2

ISGP2 8

AD8450

53

VVE0

ISGP3 9

TOP VIEW (Not to Scale)

52

NC

RFBP 10

51

VVP0

RFBN 11

50

VSETBF

ISGN3 12

49

VSET

ISGN2 13

48

NC

ISGN1S 14

47

DVCC

ISGN1 15

46

FAULT

ISGN0S 16

45

DGND

ISGN0 17

44

OCPS

RGNS 18

43

OCPR

RGN 19

42

VREF

ISVN 20

41

OVPR

NOTES 1. NC = NO CONNECT.

11966-002

OVPS

MODE

AVCC

BVMEA

AVEE

BVN3S

BVN3

BVN2

BVN1

BVN0

BVREFLS

BVREFL

AGND

VREF

BVREFH

BVP0

BVP1

BVP2

BVP3

BVP3S

21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

Figure 2. Pin Configuration

Table 4. Pin Function Descriptions Pin No. 1, 20

Mnemonic ISVP, ISVN

Input/ Output 1 Input

2, 19

RGP, RGN

N/A

3, 18 4, 6, 8, 9, 12, 13, 15, 17 5, 7, 14, 16 10, 11 21, 35 22, 23, 24, 25, 31, 32, 33, 34 26, 42, 73 27

RGPS, RGNS ISGP0, ISGP1, ISGP2, ISGP3, ISGN3, ISGN2, ISGN1, ISGN0 ISGP0S, ISGP1S, ISGN1S, ISGN0S RFBP, RFBN BVP3S, BVN3S BVP3, BVP2, BVP1, BVP0, BVN0, BVN1, BVN2, BVN3 VREF BVREFH

N/A N/A

Description Current Sense Instrumentation Amplifier Positive (Noninverting) and Negative (Inverting) Inputs. Connect these pins across the current sense shunt resistor. Current Sense Instrumentation Amplifier Gain Setting Pins. Connect these pins to the appropriate resistor network gain pins to select the current sense gain (see Table 5). Kelvin Sense Pins for the Current Sense Instrumentation Amplifier Gain Setting Pins (RGP and RGN). Current Sense Instrumentation Amplifier Resistor Network Gain Pins (see Table 5).

N/A

Kelvin Sense Pins for the ISGP0, ISGP1, ISGN1, and ISGN0 Pins.

Output N/A Input

Current Sense Preamplifier Positive and Negative Outputs. Kelvin Sense Pins for the Voltage Sense Difference Amplifier Inputs BVP3 and BVN3. Voltage Sense Difference Amplifier Inputs. Each input pair (BVPx and BVNx) corresponds to a different voltage sense gain (see Table 6).

Output Input

28, 75 29 30

AGND BVREFL BVREFLS

N/A Input N/A

Voltage Reference Output Pins. VREF = 2.5 V. Reference Input for the Voltage Sense Difference Amplifier. To level shift the voltage sense difference amplifier output by approximately 5 mV, connect this pin to the VREF pin. Otherwise, connect this pin to the BVREFL pin. Analog Ground Pins. Reference Input for the Voltage Sense Difference Amplifier. The default connection is to ground. Kelvin Sense Pin for the BVREFL Pin. Rev. B | Page 9 of 41

AD8450

Data Sheet

Pin No. 36, 61, 72 38, 57, 70 37 39

Mnemonic AVEE AVCC BVMEA MODE

Input/ Output 1 N/A N/A Output Input

40 41

OVPS OVPR

Input Input

43

OCPR

Input

44 45 46 47 48, 52, 55, 63, 66 49 50 51 53 54 56, 62 58 59

OCPS DGND FAULT DVCC NC

Input N/A Output N/A N/A

VSET VSETBF VVP0 VVE0 VVE1 VINT VCLN VCTRL

Input Output Input Input Input Output Input Output

60 64 65 67 68 69 71 74

VCLP IVE1 IVE0 ISET OAVO OAVN ISMEA ISREFH

Input Input Input Input Output Input Output Input

76 77 78 79 80

ISREFL ISREFLS OAVP IMAX CSH

Input N/A Input Output N/A

1

Description Analog Negative Supply Pins. The default voltage is −5 V. Analog Positive Supply Pins. The default voltage is +25 V. Voltage Sense Difference Amplifier Output. TTL-Compliant Logic Input to Select the Charge or Discharge Mode. Low = discharge, high = charge. Noninverting Sense Input of the Overvoltage Protection Comparator. Inverting Reference Input of the Overvoltage Protection Comparator. Typically, this pin connects to the 2.5 V reference voltage (VREF). Inverting Reference Input of the Overcurrent Protection Sense Comparator. Typically, this pin connects to the 2.5 V reference voltage (VREF). Noninverting Sense Input of the Overcurrent Protection Sense Comparator. Digital Ground Pin. Overvoltage or Overcurrent Fault Detection Logic Output (Active Low). Digital Supply. The default voltage is +5 V. No Connect. There are no internal connections to these pins. Target Voltage for the Voltage Sense Control Loop. Buffered Voltage VSET. Noninverting Input of the Voltage Sense Integrator for Discharge Mode. Inverting Input of the Voltage Sense Integrator for Discharge Mode. Inverting Input of the Voltage Sense Integrator for Charge Mode. Minimum Output of the Voltage Sense and Current Sense Integrator Amplifiers. Low Clamp Voltage for VCTRL. Controller Output Voltage. Connect this pin to the input of the PWM controller (for example, the COMP pin of the ADP1972). High Clamp Voltage for VCTRL. Inverting Input of the Current Sense Integrator for Charge Mode. Inverting Input of the Current Sense Integrator for Discharge Mode. Target Voltage for the Current Sense Control Loop. Output of the Uncommitted Operational Amplifier. Inverting Input of the Uncommitted Operational Amplifier. Current Sense Instrumentation Amplifier Output. Reference Input for the Current Sense Amplifier. To level shift the current sense instrumentation amplifier output by approximately 20 mV, connect this pin to the VREF pin. Otherwise, connect this pin to the ISREFL pin. Reference Input for the Current Sense Amplifier. The default connection is to ground. Kelvin Sense Pin for the ISREFL Pin. Noninverting Input of the Uncommitted Operational Amplifier. Maximum Voltage of All Voltages Applied to the Current Sharing (CSH) Pin. Current Sharing Bus.

N/A means not applicable.

Rev. B | Page 10 of 41

Data Sheet

AD8450

TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, AVCC = +25 V, AVEE = −5 V, RL = ∞, unless otherwise noted.

PGIA CHARACTERISTICS 20

30

VALID FOR ALL GAINS

20 15 10 5 0 –5

0

5

10

15

20

25

30

OUTPUT VOLTAGE (V)

11966-003

–5

5 0 –5 –10 –15

0

5

10

15

20

Figure 6. Input Common-Mode Voltage vs. Output Voltage for AVCC = +15 V and AVEE = −15 V

15

15

10

10

INPUT CURRENT (mA)

GAIN = 200 5

0 GAIN = 26 –5

–10

AVCC = +15V AVEE = –15V

GAIN = 200 5

0 GAIN = 26 –5

0

5

10 15 20 25 30 35 40 45

INPUT VOLTAGE (V)

–15 –45–40–35–30–25–20–15–10 –5 0

11966-005

–15 –35 –30 –25 –20 –15 –10 –5

5 10 15 20 25 30 35 40 45

INPUT VOLTAGE (V)

Figure 4. Input Overvoltage Performance for AVCC = +25 V and AVEE = −5 V

11966-006

–10 AVCC = +25V AVEE = –5V

17.0

–5

OUTPUT VOLTAGE (V)

Figure 3. Input Common-Mode Voltage vs. Output Voltage for AVCC = +25 V and AVEE = −5 V

INPUT CURRENT (mA)

10

AVCC = +15V AVEE = –15V –20 –20 –15 –10

AVCC = +25V AVEE = –5V

–10 –10

15

11966-004

25

INPUT COMMON-MODE VOLTAGE (V)

INPUT COMMON-MODE VOLTAGE (V)

VALID FOR ALL GAINS

Figure 7. Input Overvoltage Performance for AVCC = +15 V and AVEE = −15 V 20

VALID FOR ALL GAINS

16.8

19

INPUT BIAS CURRENT (nA)

16.4 AVCC = +15V AVEE = –15V

16.2 16.0

AVCC = +25V AVEE = –5V

15.8 15.6

18 17 +IB

16

–IB 15 14

15.4

15.0 –15

–10

–5

0

5

10

15

20

25

INPUT COMMON-MODE VOLTAGE (V)

Figure 5. Input Bias Current vs. Input Common-Mode Voltage

12 –40 –30 –20 –10

0

10

20

30

40

50

60

70

TEMPERATURE (°C)

Figure 8. Input Bias Current vs. Temperature

Rev. B | Page 11 of 41

80

90

11966-008

13

15.2 11966-007

INPUT BIAS CURRENT (nA)

16.6

AD8450

Data Sheet

20

160

GAIN = 200 GAIN = 133 GAIN = 66 GAIN = 26

150

0

140

GAIN = 200

120

GAIN = 66

CMRR (dB)

GAIN ERROR (µV/V)

130

–20

–40 GAIN = 133

110 100 90

–60

80

GAIN = 26

70

–80

10

20

30

40

50

60

70

80

90

TEMPERATURE (°C)

50 0.1

11966-009

0

1

100

1k

10k

100k

100k

1M

FREQUENCY (Hz)

Figure 12. CMRR vs. Frequency

Figure 9. Gain Error vs. Temperature

0.3

10

11966-012

60

–100 –40 –30 –20 –10

160

AVCC = +25V AVEE = –5V

140

0.2

120

0

–0.1 GAIN = 200 GAIN = 133 GAIN = 66 GAIN = 26 0

10

20

30

40

50

60

70

80

90

TEMPERATURE (°C)

80 60 40

GAIN

20

200 133 66 26

AVCC

0 1

10

GAIN = 200 GAIN = 133 GAIN = 66

30

10 0 –10

10k

100k

FREQUENCY (Hz)

1M

10M

11966-011

GAIN (dB)

GAIN = 26 20

AVCC = +15V AVEE = –15V –20 100 1k

1k

10k

Figure 13. PSRR vs. Frequency

SPECTRAL DENSITY VOLTAGE NOISE (nV/√Hz)

40

100

FREQUENCY (Hz)

Figure 10. Normalized CMRR vs. Temperature

50

AVEE

100

GAIN = 200 GAIN = 133 GAIN = 66 GAIN = 26

RTI 10

1 0.1

1

10

100

1k

10k

100k

FREQUENCY (Hz)

Figure 14. Spectral Density Voltage Noise, RTI vs. Frequency

Figure 11. Gain vs. Frequency

Rev. B | Page 12 of 41

11966-014

–0.3 –40 –30 –20 –10

11966-010

–0.2

100

11966-013

PSRR (dB)

CMRR (µV/V)

0.1

Data Sheet

AD8450

PGDA CHARACTERISTICS 50

20 10 0 –10 –20 –30 –5

0

5

10

15

20

25

30

OUTPUT VOLTAGE (V)

10 0 –10 –20 –30 –40 –50 –20

–10

0

GAIN ERROR (ppm)

50

–20

–30

10k

100k

1M

FREQUENCY (Hz)

10

15

20

–100

0

10

20

30

40

50

60

70

80

90

TEMPERATURE (°C)

Figure 19. Gain Error vs. Temperature

3

2

–40

1

CMRR (µV/V)

–20

–60

–80

0

–1 GAIN = 0.80 GAIN = 0.40 GAIN = 0.27 GAIN = 0.20

–100

1k

10k

100k

FREQUENCY (Hz)

1M

GAIN = 0.80 GAIN = 0.40 GAIN = 0.27 GAIN = 0.20

–2

11966-020

CMRR (dB)

5

GAIN = 0.80 GAIN = 0.40 GAIN = 0.27 GAIN = 0.20

–200 –40 –30 –20 –10

VALID FOR ALL RATED SUPPLY VOLTAGES

–120 100

0

–50

Figure 16. Gain vs. Frequency

0

–5

–150

GAIN = 0.80 GAIN = 0.40 GAIN = 0.27 GAIN = 0.20 11966-019

VALID FOR ALL RATED SUPPLY VOLTAGES –50 100 1k

–10

Figure 18. Input Common-Mode Voltage vs. Output Voltage for AVCC = +15 V and AVEE = −15 V

0

–40

–15

OUTPUT VOLTAGE (V)

Figure 15. Input Common-Mode Voltage vs. Output Voltage for AVCC = +25 V and AVEE = −5 V

GAIN (dB)

20

–3 –40 –30 –20 –10

0

10

20

30

40

50

60

70

TEMPERATURE (°C)

Figure 20. Normalized CMRR vs. Temperature

Figure 17. CMRR vs. Frequency

Rev. B | Page 13 of 41

80

90

11966-018

–40 –10

30

11966-016

30

GAIN = 0.80 GAIN = 0.40 GAIN = 0.27 GAIN = 0.20

40

11966-017

40

INPUT COMMON-MODE VOLTAGE (V)

GAIN = 0.80 GAIN = 0.40 GAIN = 0.27 GAIN = 0.20

50

11966-015

INPUT COMMON-MODE VOLTAGE (V)

60

AD8450

Data Sheet AVEE

0.80 0.40 0.27 0.20

–20 –40 –60 –80 –100 –120

VALID FOR ALL RATED SUPPLY VOLTAGES

–140 10

100

1k

10k

FREQUENCY (Hz)

100k

11966-021

PSRR (dB)

AVCC

Figure 21. PSRR vs. Frequency

1k

GAIN = 0.80 GAIN = 0.40 GAIN = 0.27 GAIN = 0.20

RTI

100

10 0.1

1

10

100

1k

10k

100k

FREQUENCY (Hz)

Figure 22. Spectral Density Voltage Noise, RTI vs. Frequency

Rev. B | Page 14 of 41

11966-022

GAIN

SPECTRAL DENSITY VOLTAGE NOISE (nV/√Hz)

0

Data Sheet

AD8450

500

2.0

400

1.8

OUTPUT SOURCE CURRENT (mA)

300 AVCC = +15V AVEE = –15V

AVCC = +25V AVEE = –5V

100 0 –100 –200 –300

1.6 1.4

1.0 AVCC = +15V AVEE = –15V

0.8 0.6 0.4 0.2

–400 –10

–5

0

5

10

15

20

25

INPUT COMMON-MODE VOLTAGE (V)

0 –40 –30 –20 –10

11966-023

–500 –15

AVCC = +25V AVEE = –5V

1.2

0

10

Figure 23. Input Offset Voltage vs. Input Common-Mode Voltage for Two Supply Voltage Combinations

40

50

60

70

80

120

90

100

OPEN-LOOP GAIN (dB)

AVCC = +25V AVEE = –5V

70

90

–45.0 –67.5

80

INPUT BIAS CURRENT (pA)

30

Figure 26. Output Source Current vs. Temperature for Two Supply Voltage Combinations

100

60 50 40

20

TEMPERATURE (°C)

11966-026

200

CONSTANT CURRENT LOOP AND CONSTANT VOLTAGE LOOP AMPLIFIERS

AVCC = +15V AVEE = –15V

30

PHASE

80

–90.0

60

–112.5

40

–135.0 GAIN

20

–157.5

0

–180.0

–20

–202.5

PHASE (Degrees)

INPUT OFFSET VOLTAGE (µV)

CC AND CV LOOP FILTER AMPLIFIERS, UNCOMMITTED OP AMP, AND VSET BUFFER

20

–5

0

5

10

15

20

25

INPUT COMMON-MODE VOLTAGE (V)

–40 10

100

10k

100k

1M

–225.0 10M

FREQUENCY (Hz)

Figure 24. Input Bias Current vs. Input Common-Mode Voltage for Two Supply Voltage Combinations

Figure 27. Open-Loop Gain and Phase vs. Frequency

100

160

80

140 120

CMRR (dB)

60 40 20 0

100

UNCOMMITTED OP AMP

80 60 40

–20 –40 –40 –30 –20 –10

0

10

20

30

40

50

60

70

TEMPERATURE (°C)

80

CONSTANT CURRENT LOOP AND CONSTANT VOLTAGE LOOP FILTER AMPLIFIERS

20

–IB +IB 90

11966-025

INPUT BIAS CURRENT (nA)

1k

11966-027

–10

Figure 25. Input Bias Current vs. Temperature

0 10

100

1k

10k

FREQUENCY (Hz)

Figure 28. CMRR vs. Frequency

Rev. B | Page 15 of 41

100k

1M

11966-028

0 –15

11966-024

10

AD8450

Data Sheet 1.5

140 120

1.0

OUTPUT VOLTAGE (V)

+PSRR

PSRR (dB)

100 80 60 –PSRR

40

AVCC = +15V AVEE = –15V

0.5

TRANSITION

0

–0.5

–1.0

20

ISET

1k

10k

100k

1M

FREQUENCY (Hz)

1k

100

10

1 0.1

1

10

100

1k

–10

–5

0

5

10

15

20

TIME (µs)

Figure 31. CC to CV Transition

10k

100k

FREQUENCY (Hz)

11966-030

SPECTRAL DENSITY VOLTAGE NOISE (nV/√Hz)

Figure 29. PSRR vs. Frequency

–1.5 –15

Figure 30. Range of Spectral Density Voltage Noise vs. Frequency for the Op Amps and Buffers

Rev. B | Page 16 of 41

25

30

35

11966-031

100

11966-029

VCTRL

0 10

Data Sheet

AD8450

VINT BUFFER 0.5

6 CL = 100pF RL = 2kΩ

VCTRL OUTPUT WRT VCLP 0.4 0.3 0.2 0.1 VCLP AND VCLN REFERENCE 0 VALID FOR ALL RATED SUPPLY VOLTAGES

–0.1

4

OUTPUT VOLTAGE (V)

OUTPUT VOLTAGE SWING (V)

5

–0.2

3 2 1

–0.3 VCTRL OUTPUT WRT VCLN

0

0

10

20

30

40

50

60

70

80

90

TEMPERATURE (°C)

–1

11966-032

–0.5 –40 –30 –20 –10

0

10

15

20

25

30

35

40

TIME (µs)

Figure 32. Output Voltage Swing with Respect to VCLP and VCLN vs. Temperature

Figure 35. Large Signal Transient Response, RL = 2 kΩ, CL = 100 pF

15

0.20 CL = 10pF CL = 100pF CL = 510pF CL = 680pF CL = 1000pF

0.15

OUTPUT VOLTAGE (V)

10

OUTPUT VOLTAGE SWING (V)

5

11966-035

–0.4

5 TEMP

VCLP

VCLN

–40°C +25°C +85°C

0

–5

0.10 0.05 0 –0.05 –0.10

–10

1k

10k

100k

1M

LOAD RESISTANCE (Ω)

–0.20

11966-033

–15 100

0

2

3

4

5

6

7

8

9

10

TIME (µs)

Figure 33. Output Voltage Swing vs. Load Resistance at Three Temperatures

Figure 36. Small Signal Transient Response vs. Capacitive Load

6

100

5 OUTPUT IMPEDANCE (Ω)

VCLP 4 TEMP

3

VCLP

VCLN

–40°C 0°C +25°C +85°C

VIN = +6V/–1V 2 1

10

1

–1 10

15

20

25

30

35

OUTPUT CURRENT (mA)

40

Figure 34. Clamped Output Voltage vs. Output Current at Four Temperatures

0.1 10

100

1k

10k

100k

FREQUENCY (Hz)

Figure 37. Output Impedance vs. Frequency

Rev. B | Page 17 of 41

1M

11966-037

VCLN

0

11966-034

CLAMPED OUTPUT VOLTAGE (V)

1

11966-036

–0.15

AD8450

Data Sheet

CURRENT SHARING AMPLIFIER –0.20

3

VALID FOR ALL RATED SUPPLY VOLTAGES

2

OUTPUT VOLTAGE (V)

–0.25

–0.30

–0.35

–0.40

1

TRANSITION

0

–1

–2

–0.45

–0.50 –40 –30 –20 –10

0

10

20

30

40

50

60

70

TEMPERATURE (°C)

80

90

Figure 38. Output Sink Current vs. Temperature

–3 –15

–10

–5

0

5

10

15

20

25

30

TIME (µs)

Figure 39. Current Sharing Bus Transition Characteristics

Rev. B | Page 18 of 41

35

11966-039

ISMEA IMAX 11966-038

OUTPUT SINK CURRENT (mA)

AVCC = +15V AVEE = –15V

Data Sheet

AD8450

COMPARATORS 5

4 450

OUTPUT VOLTAGE (V)

PROPAGATION DELAY (ns)

500

HIGH TO LOW TRANSITION 400

LOW TO HIGH TRANSITION

350

VALID FOR ALL RATED SUPPLY VOLTAGES

3

TEMP ISOURCE

ISINK

–40°C +25°C +85°C

2

0

10

20

30

40

50

60

70

80

90

TEMPERATURE (°C)

Figure 40. Propagation Delay vs. Temperature

0

6

1400

5

1200

4 HIGH TO LOW TRANSITION

800 LOW TO HIGH TRANSITION

600

300

400

500

3 TA = –40°C TA = +25°C TA = +85°C

2 1

400

100

200

300

400

500

600

700

800

900

1000

LOAD CAPACITANCE (pF)

1000 900 800 700 600 HIGH TO LOW TRANSITION

400 300

LOW TO HIGH TRANSITION

200

100

1k

SOURCE RESISTANCE (Ω)

10k

11966-042

100 0 10

2.46

2.47

2.48

2.49

2.50

2.51

2.52

2.53

2.54

2.55

INPUT VOLTAGE (V)

Figure 44. Comparator Transfer Function at Three Temperatures

Figure 41. Propagation Delay vs. Load Capacitance

500

–1 2.45

Figure 42. Propagation Delay vs. Source Resistance

Rev. B | Page 19 of 41

11966-044

0

11966-041

0

200

PROPAGATION DELAY (ns)

200

Figure 43. Output Voltage vs. Output Current at Three Temperatures

1600

1000

100

OUTPUT CURRENT (µA)

HYSTERESIS (V)

PROPAGATION DELAY (ns)

0

11966-040

300 –40 –30 –20 –10

11966-043

1

AD8450

Data Sheet

REFERENCE CHARACTERISTICS 2.51

AVCC = +25V AVEE = –5V 1100

LOAD REGULATION (ppm/mA)

2.50

OUTPUT VOLTAGE (V)

1200

TA = +85°C TA = +25°C TA = 0°C TA = –20°C TA = –40°C

2.49

2.48

2.47

1000

900

800

700

1

3

2

4

5

6

7

8

9

10

OUTPUT CURRENT—SOURCING (mA)

600 –40 –30 –20 –10

2.7

2.6

2.5

2.4 –10

TA = +85°C TA = +25°C TA = 0°C TA = –20°C TA = –40°C –9

–8

–7

–6

–5

–4

–3

–2

OUTPUT CURRENT—SINKING (mA)

–1

0

11966-046

OUTPUT VOLTAGE (V)

2.8

20

30

40

50

60

70

80

90

Figure 47. Source and Sink Load Regulation vs. Temperature

SPECTRAL DENSITY VOLTAGE NOISE (nV/√Hz)

AVCC = +25V AVEE = –5V

10

TEMPERATURE (°C)

Figure 45. Output Voltage vs. Output Current (Sourcing) over Temperature

2.9

0

Figure 46. Output Voltage vs. Output Current (Sinking) over Temperature

Rev. B | Page 20 of 41

1k

100

10 0.1

1

10

100

1k

10k

100k

FREQUENCY (Hz)

Figure 48. Spectral Density Voltage Noise vs. Frequency

11966-048

0

11966-045

2.46

11966-047

AVCC = +25V AVEE = –5V

Data Sheet

AD8450

THEORY OF OPERATION INTRODUCTION

70

71

69

68

3

806Ω

+/–

+ –

100kΩ CS BUFFER

10kΩ

4

AVCC

+ –

0.2mA

19.2kΩ

9

10kΩ

1667Ω

625Ω

305Ω

202Ω

10

AVEE

VINT

53 AVEE

BATTERY CURRENT SENSING PGIA

52 VSET BUFFER

10kΩ –

1×

CONSTANT CURRENT AND VOLTAGE LOOP FILTER AMPLIFIERS

20kΩ

13

50 49

VCLP VCTRL VCLN AVCC VINT NC VVE1 VVE0 NC VVP0 VSETBF VSET

48 NC

14

47

AD8450

46

15 OVERCURRENT FAULT COMPARATOR

80kΩ

100kΩ

43

DGND OCPS OCPR

42 41

MODE 1 = CHARGE 0 = DISCHARGE

35

Figure 49. AD8450 Detailed Block Diagram

Rev. B | Page 21 of 41

36

37

38

39

OVPR

40

OVPS

34

MODE

33

AVCC

32

BVMEA

31

BVN3

30

BVN2

29

BVN1

28

27

OVERVOLTAGE FAULT COMPARATOR

NOR

FAULT

VREF

BVREFLS

BVP0

VREF

26

25

BVP1

24

BVP2

23

BVP3

BVP3S

22

45 44

100kΩ 100kΩ 100kΩ

BVREFL

20 21

100Ω

AGND

19

+

BATTERY VOLTAGE SENSING PGDA

BVN0

– +/–

+ –

DVCC

11966-049

100kΩ

10kΩ

79.9kΩ

18

10kΩ

10kΩ

10kΩ

16 17

51

+

100kΩ 100kΩ 100kΩ ISVN

54

+ –

50kΩ

RGN

NC

CV LOOP FILTER AMPLIFIER

8

BVREFH

RGNS

56

+ –

ISGN0

57 1.1mA

–

ISGN0S

IVE1

CC LOOP FILTER AMPLIFIER

+

ISGN1

AVEE

55

12

ISGN1S

59 58

+

6

11

60

–

CS BUS AVCC AMPLIFIER

1×

ISGN3 ISGN2

61

62

1×

AVEE

RFBN

63

64

–

7

RFBP

65

VINT BUFFER

ISGP1S

ISGP3

IVE0

66

67

+ UNCOMMITTED OP AMP

0.2mA

ISGP2

NC

ISET

OAVN

AVCC

ISMEA

72

73

AGND

2

5

AVEE

VREF

ISREFH

ISREFL

AGND 74

AVEE

ISGP1

75

76

BVN3S

ISGP0S

77

2.5V VREF

10kΩ

ISGP0

78

10kΩ

RGPS

79

1

10kΩ

RGP

OAVP

IMAX

CSH 80 ISVP

ISREFLS

To form and test a battery, the battery must undergo charge and discharge cycles. During these cycles, the battery terminal current and voltage must be precisely controlled to prevent battery failure or a reduction in the capacity of the battery. Therefore, battery formation and test systems require a high precision analog front end to monitor the battery current and terminal voltage.

OAVO

The analog front end of the AD8450 includes a precision current sense programmable gain instrumentation amplifier (PGIA) to measure the battery current, and a precision voltage sense programmable gain difference amplifier (PGDA) to measure the battery voltage. The gain programmability of the PGIA allows the system to set the battery charge/discharge current to any of four discrete values with the same shunt resistor. The gain programmability of the PGDA allows the system to handle up to four batteries in series (4S).

AD8450

Data Sheet Battery formation and test systems used to condition high current battery cells often employ multiple independent channels to charge or discharge high currents to or from the battery. To maximize efficiency, these systems benefit from circuitry that enables precise current sharing (or balancing) among the channels—that is, circuitry that actively matches the output current of each channel. The AD8450 includes a specialty precision amplifier that detects the maximum output current among several channels by identifying the channel with the maximum voltage at its PGIA output. This maximum voltage can then be compared to all the PGIA output voltages to actively adjust the output current of each channel.

Battery formation and test systems charge and discharge batteries using a constant current/constant voltage (CC/CV) algorithm. In other words, the system first forces a set constant current in or out of the battery until the battery voltage reaches a target value. At this point, a set constant voltage is forced across the battery terminals. The AD8450 provides two control loops—a constant current (CC) loop and a constant voltage (CV) loop—that transition automatically after the battery reaches the user defined target voltage. These loops are implemented via two precision specialty amplifiers with external feedback networks that set the transfer function of the CC and CV loops. Moreover, in the AD8450, these loops reconfigure themselves to charge or discharge the battery by toggling the MODE pin.

Figure 49 is a block diagram of the AD8450 that illustrates the distinct sections of the AD8450, including the PGIA and PGDA measurement blocks, the loop filter amplifiers, the fault comparators, and the current sharing circuitry. Figure 50 is a block diagram of a battery formation and test system.

Battery formation and test systems must also be able to detect overvoltage and overcurrent conditions in the battery to prevent damage to the battery and/or the control system. The AD8450 includes two comparators to detect overcurrent and overvoltage events. These comparators output a logic low at the FAULT pin when either comparator is tripped.

+ –

VISET

1×

CONSTANT VOLTAGE LOOP FILTER AMPLIFIER

CONSTANT CURRENT LOOP FILTER AMPLIFIER

VVSET C

OUTPUT FILTER

SYSTEM POWER CONVERSION AVEE

D

IVE0

D

IVE1

CV BUFFER

C

VVE0

D

VVE1

C

VVP0

AD8450 CONTROLLER

MODE SWITCHES (3) C = CHARGE D = DISCHARGE VINT

FAULT

BATTERY CURRENT

NOR OVERVOLTAGE COMPARATOR

OVERCURRENT COMPARATOR ISVP +

OVPS

OVPR VREF

OCPR

SENSE RESISTOR

PGIA

+

+

–

OCPS

ISVN

SYSTEM LOOP COMPENSATION

ISMEA BVMEA

BVPx + BATTERY

PGDA –

Figure 50. Signal Path of a Li-Ion Battery Formation and Test System Using the AD8450

Rev. B | Page 22 of 41

BVNx

11966-050

VSETBF

OUTPUT LEVEL DRIVERS SHIFTER POWER CONVERTER (SWITCHED OR LINEAR)

ADP1972 PWM

+ –

VSET

1×

VCTRL

–

SET BATTERY VOLTAGE

AVCC

VINT BUFFER

ISET

–

SET BATTERY CURRENT

Data Sheet

AD8450 The external PGIA gain is set by tying 10 kΩ feedback resistors between the inverting inputs of the PGIA preamplifiers (RGP and RGN pins) and the outputs of the PGIA preamplifiers (RFBP and RFBN pins) and by tying a gain resistor (RG) between the RGP and RGN pins. When using external resistors, the PGIA gain is

PROGRAMMABLE GAIN INSTRUMENTATION AMPLIFIER (PGIA) Figure 51 is a block diagram of the PGIA, which is used to monitor the battery current. The architecture of the PGIA is the classic 3-op-amp topology, similar to the Analog Devices industrystandard AD8221 and AD620. This architecture provides the highest achievable CMRR at a given gain, enabling high-side battery current sensing without the introduction of significant errors in the measurement. For more information about instrumentation amplifiers, see A Designer's Guide to Instrumentation Amplifiers.

Gain = 2 × (1 + 20 kΩ/RG) Note that the PGIA subtractor has a closed-loop gain of 2 to increase the common-mode range of the preamplifiers.

Reversing Polarity When Charging and Discharging Figure 50 shows that during the charge cycle, the power converter feeds current into the battery, generating a positive voltage across the current sense resistor. During the discharge cycle, the power converter draws current from the battery, generating a negative voltage across the sense resistor. In other words, the battery current polarity reverses when the battery discharges.

VREF POLARITY INVERTER + CURRENT SHUNT

ISVP

+/–

+

RGP

100kΩ ISREFH

PGIA 10kΩ

19.2kΩ

806Ω ISREFL

–

In the constant current (CC) control loop, this change in polarity can be problematic if the polarity of the target current is not reversed. To solve this problem, the AD8450 PGIA includes a multiplexer preceding its inputs that inverts the polarity of the PGIA gain. This multiplexer is controlled via the MODE pin. When the MODE pin is logic high (charge mode), the PGIA gain is noninverting, and when the MODE pin is logic low (discharge mode), the PGIA gain is inverting.

RFBP ISGP0, ISGP1, ISGP2, ISGP3 CONNECT FOR DESIRED GAIN

G = 2 SUBTRACTOR GAIN NETWORKS (4)

ISGN0, ISGN1, ISGN2, ISGN3

ISMEA

RFBN

PGIA Offset Option

RGN – CURRENT SHUNT

ISVN

– +/–

+

10kΩ

20kΩ

11966-051

POLARITY INVERTER MODE

Figure 51. PGIA Simplified Block Diagram

Gain Selection The PGIA includes four fixed internal gain options. The PGIA can also use an external gain network for arbitrary gain selection. The internal gain options are established via four independent three-resistor networks, which are laser trimmed to a matching level better than ±0.1%. The internal gains are optimized to minimize both PGIA gain error and gain error drift, allowing the controller to set a stable charge/discharge current over temperature. If the built in internal gains are not adequate, the PGIA gain can be set via an external three-resistor network. The internal gains of the PGIA are selected by tying the inverting inputs of the PGIA preamplifiers (RGP and RGN pins) to the corresponding gain pins of the internal three-resistor network (ISGP[0:3] and ISGN[0:3] pins). For example, to set the PGIA gain to 26, tie the RGP pin to the ISGP0 pin, and tie the RGN pin to the ISGN0 pin. See Table 5 for information about the gain selection connections.

As shown in Figure 51, the PGIA reference node is connected to the ISREFL and ISREFH pins via an internal resistor divider. This resistor divider can be used to introduce a temperature insensitive offset to the output of the PGIA such that the PGIA output always reads a voltage higher than zero for a zero differential input. Because the output voltage of the PGIA is always positive, a unipolar ADC can digitize it. When the ISREFH pin is tied to the VREF pin with the ISREFL pin grounded, the voltage at the ISMEA pin is increased by 20 mV, guaranteeing that the output of the PGIA is always positive for zero differential inputs. Other voltage shifts can be realized by tying the ISREFH pin to an external voltage source. The gain from the ISREFH pin to the ISMEA pin is 8 mV/V. For zero offset, tie the ISREFL and ISREFH pins to ground.

Battery Reversal and Overvoltage Protection The AD8450 PGIA can be configured for high-side or low-side current sensing. If the PGIA is configured for high-side current sensing (see Figure 50) and the battery is connected backward, the PGIA inputs may be held at a voltage that is below the negative power rail (AVEE), depending on the battery voltage. To prevent damage to the PGIA under these conditions, the PGIA inputs include overvoltage protection circuitry that allows them to be held at voltages of up 55 V from the opposite power rail. In other words, the safe voltage span for the PGIA inputs extends from AVCC − 55 V to AVEE + 55 V.

Rev. B | Page 23 of 41

AD8450

Data Sheet

PROGRAMMABLE GAIN DIFFERENCE AMPLIFIER (PGDA)

When the BVREFH pin is tied to the VREF pin with the BVREFL pin grounded, the voltage at the BVMEA pin is increased by 5 mV, guaranteeing that the output of the PGDA is always positive for zero differential inputs. Other voltage shifts can be realized by tying the BVREFH pin to an external voltage source. The gain from the BVREFH pin to the BVMEA pin is 2 mV/V. For zero offset, tie the BVREFL and BVREFH pins to ground.

Figure 52 is a block diagram of the PGDA, which is used to monitor the battery voltage. The architecture of the PGDA is a subtractor amplifier with four selectable inputs: the BVP[0:3] and BVN[0:3] pins. Each input pair corresponds to one of the internal gains of the PGDA: 0.2, 0.27, 0.4, and 0.8. These gain values allow the PGDA to funnel the voltage of up to four 5 V batteries in series (4S) to a level that can be read by a 5 V ADC. See Table 6 for information about the gain selection connections.

BVP3

100kΩ

BVP1

BVREFL

The constant current (CC) and constant voltage (CV) loop filter amplifiers are high precision, low noise specialty amplifiers with very low offset voltage and very low input bias current. These amplifiers serve two purposes:

BVREFH

•

BVP0 100kΩ

100kΩ

100kΩ

79.9kΩ

100Ω

50kΩ

+

PGDA

VREF

– 100kΩ

BVN2

100kΩ

100kΩ

BVN1

100kΩ

• 80kΩ

BVMEA

Figure 53 is the functional block diagram of the AD8450 CC and CV feedback loops for charge mode (MODE pin is logic high). For illustration purposes, the external networks connected to the loop amplifiers are simple RC networks configured to form single-pole inverting integrators. The outputs of the CC and CV loop filter amplifiers are coupled to the VINT pin via an analog NOR circuit (minimum output selector circuit), such that they can only pull the VINT node down. In other words, the loop amplifier that requires the lowest voltage at the VINT pin is in control of the node. Thus, only one loop amplifier, CC or CV, can be in control of the system charging control loop at any given time.

11966-152

BVN3

BVN0

Using external components, the amplifiers implement active loop filters that set the dynamics (transfer function) of the CC and CV loops. The amplifiers perform a seamless transition from CC to CV mode after the battery reaches its target voltage.

Figure 52. PGDA Simplified Block Diagram

The resistors that form the PGDA gain network are laser trimmed to a matching level better than ±0.1%. This level of matching minimizes the gain error and gain error drift of the PGDA while maximizing the CMRR of the PGDA. This matching also allows the controller to set a stable target voltage for the battery over temperature while rejecting the ground bounce in the battery negative terminal. Like the PGIA, the PGDA can also level shift its output voltage via an internal resistor divider that is tied to the PGDA reference node. This resistor divider is connected to the BVREFH and BVREFL pins.

I POWER IOUT BUS VCTRL IBAT

ISVP SENSE RESISTOR

R1

VISET

RS

ISVN

PGIA + GIA

ISMEA

ISET

POWER CONVERTER

C1

IVE1 –

CC LOOP AMPLIFIER

VINT

VINT BUFFER VCLP

–

+

ANALOG NOR

+

MINIMUM OUTPUT SELECTOR

VCTRL

1× + VBAT –

BVPx BVNx

PGDA

+

GDA – MODE 5V

VCLN

V3 – BVMEA

VSET

VVE1

CV LOOP AMPLIFIER

VVSET

V4

VINT V3 < VCTRL < V4

R2

C2

Figure 53. Functional Block Diagram of the CC and CV Loops in Charge Mode (MODE Pin High)

Rev. B | Page 24 of 41

11966-053

BVP2

CC AND CV LOOP FILTER AMPLIFIERS

Data Sheet

AD8450 The following steps describe how the AD8450 implements the CC/CV charging profile (see Figure 53). In this scenario, the battery begins in the fully discharged state, and the system has just been turned on such that IBAT = 0 A at Time 0.

The unity-gain amplifier (VINT buffer) buffers the VINT pin and drives the VCTRL pin. The VCTRL pin is the control output of the AD8450 and the control input of the power converter. The VISET and VVSET voltage sources set the target constant current and the target constant voltage, respectively. When the CC and CV feedback loops are in steady state, the charging current is set at IBAT_SS =

1.

VISET G IA × RS

2.

where: GIA is the PGIA gain. RS is the value of the shunt resistor. The target voltage is set at VBAT_SS =

3.

VVSET G DA

where GDA is the PGDA gain. Because the offset voltage of the loop amplifiers is in series with the target voltage sources, VISET and VVSET, the high precision of these amplifiers minimizes this source of error. Figure 54 shows a typical CC/CV charging profile for a Li-Ion battery. In the first stage of the charging process, the battery is charged with a constant current (CC) of 1 A. When the battery voltage reaches a target voltage of 4.2 V, the charging process transitions such that the battery is charged with a constant voltage (CV) of 4.2 V. 1.25

5

0.50

2

0.25

1

CC CHARGE ENDS

0

0 1

2

3

TIME (Hours)

4

7.

VOLTAGE (V)

3

5

11966-054

CURRENT (A)

6.

4

0.75

0

5.

TRANSITION FROM CC TO CV

CC CHARGE BEGINS

1.00

4.

Figure 54. Representative Constant Current to Constant Voltage Transition Near the End of a Battery Charging Cycle

Because the voltages at the ISMEA and BVMEA pins are below the target voltages (VISET and VVSET) at Time 0, both integrators begin to ramp, increasing the voltage at the VINT node. As the voltage at the VINT node increases, the voltage at the VCRTL node rises, and the output current of the power converter, IBAT, increases (assuming that an increasing voltage at the VCRTL node increases the output current of the power converter). When the IBAT current reaches the CC steady state value, IBAT_SS, the battery voltage is still below the target steady state value, VBAT_SS. Therefore, the CV loop tries to keep pulling the VINT node up while the CC loop tries to keep it at its current voltage. At this point, the voltage at the ISMEA pin equals VISET, so the CC loop stops integrating. Because the loop amplifiers can only pull the VINT node down due to the analog NOR circuit, the CC loop takes control of the charging feedback loop and the CV loop is disabled. As the charging process continues, the battery voltage increases until it reaches the steady state value, VBAT_SS, and the voltage at the BVMEA pin reaches the target voltage, VVSET. The CV loop tries to pull the VINT node down to reduce the charging current (IBAT) and prevent the battery voltage from rising any farther. At the same time, the CC loop tries to keep the VINT node at its current voltage to keep the battery current at IBAT_SS. Because the loop amplifiers can only pull the VINT node down due to the analog NOR circuit, the CV loop takes control of the charging feedback loop and the CC loop is disabled.

The analog NOR (minimum output selector) circuit that couples the outputs of the loop amplifiers is optimized to minimize the transition time from CC to CV control. Any delay in the transition causes the CC loop to remain in control of the charge feedback loop after the battery voltage reaches its target value. Therefore, the battery voltage continues to rise beyond VBAT_SS until the control loop transitions; that is, the battery voltage overshoots its target voltage. When the CV loop takes control of the charge feedback loop, it reduces the battery voltage to the target voltage. A large overshoot in the battery voltage due to transition delays can damage the battery; thus, it is crucial to minimize delays by implementing a fast CC to CV transition.

Rev. B | Page 25 of 41

AD8450

Data Sheet I POWER IOUT BUS VCTRL

PGIA + GIA

ISVP SENSE RESISTOR

R1

VISET

IBAT

RS

ISVN

ISMEA

IVE0

ISET

POWER CONVERTER

C1

VINT

CC LOOP AMPLIFIER

–

VINT BUFFER VCLP

–

ANALOG NOR

+

VCTRL

–

BVPx

+

PGDA GDA

BVNx

–

MODE 0V

CV LOOP AMPLIFIER

BVMEA

+

VCLN

V3

1× VSET

1× MINIMUM OUTPUT SELECTOR

V4

– VSETBF

VVP0

VVE0

R2

C2

VINT V3 < VCTRL < V4

VVSET

C2

R2

11966-055

+ VBAT

VSET BUFFER

Figure 55. Functional Block Diagram of the CC and CV Loops in Discharge Mode (MODE Pin Low)

Figure 55 is the functional block diagram of the AD8450 CC and CV feedback loops for discharge mode (MODE pin is logic low. In discharge mode, the feedback loops operate in a similar manner as in charge mode. The only difference is in the CV loop amplifier, which operates as a noninverting integrator in discharge mode. For illustration purposes, the external networks connected to the loop amplifiers are simple RC networks configured to form single-pole integrators (see Figure 55).

COMPENSATION In battery formation and test systems, the CC and CV feedback loops have significantly different open-loop gain and crossover frequencies; therefore, each loop requires its own frequency compensation. The active filter architecture of the AD8450 CC and CV loops allows the frequency response of each loop to be set independently via external components. Moreover, due to the internal switches in the CC and CV amplifiers, the frequency response of the loops in charge mode does not affect the frequency response of the loops in discharge mode. Unlike simpler controllers that use passive networks to ground for frequency compensation, the AD8450 allows the use of feedback networks for its CC and CV loop filter amplifiers. These networks enable the implementation of both PD (Type II) and PID (Type III) compensators. Note that in charge mode, both the CC and CV loops implement inverting compensators, whereas in discharge mode, the CC loop implements an inverting compensator and the CV loop implements a noninverting compensator. As a result, the CV loop in discharge mode includes an additional amplifier, VSET buffer, to buffer the VSET node from the feedback network (see Figure 55).

VINT BUFFER The unity-gain amplifier (VINT buffer) is a clamp amplifier that drives the VCTRL pin. The VCTRL pin is the control output of the AD8450 and the control input of the power converter (see Figure 53 and Figure 55). The output voltage range of this amplifier is bounded by the clamp voltages at the VCLP and VCLN pins such that VVCLN − 0.5 V < VVCTRL < VVCLP + 0.5 V The reduction in the output voltage range of the amplifier is a safety feature that allows the AD8450 to drive devices such as the ADP1972 pulse-width modulation (PWM) controller, whose input voltage range must not exceed 5.5 V (that is, the voltage at the COMP pin of the ADP1972 must be below 5.5 V).

MODE PIN, CHARGE AND DISCHARGE CONTROL The MODE pin is a TTL logic input that configures the AD8450 for either charge or discharge mode. A logic low (VMODE < 0.8 V) corresponds to discharge mode, and a logic high (VMODE > 2 V) corresponds to charge mode. Internal to the AD8450, the MODE pin toggles all SPDT switches in the CC and CV loop amplifiers and inverts the gain polarity of the PGIA.

Rev. B | Page 26 of 41

Data Sheet

AD8450

OVERCURRENT AND OVERVOLTAGE COMPARATORS The AD8450 includes overcurrent protection (OCP) and overvoltage protection (OVP) comparators to detect overvoltage and overcurrent conditions in the battery. Because the outputs of the comparators are combined by a NOR logic gate, these comparators output a logic low at the FAULT pin when either comparator is tripped (see Figure 49).

Alternatively, the outputs of the PGIA and PGDA can be tied directly to the sense inputs of the comparators (OCPS and OVPS pins) such that the voltages at the ISMEA and BVMEA pins are compared to the external reference voltages, VOCP_REF and VOVP_REF (see Figure 57). In this configuration, the FAULT pin registers a logic low (a fault condition) when VISMEA > VOCP_REF or

The OCP and OVP comparators can be configured to detect a fault in one of two ways. In the configuration shown in Figure 56, the voltages at the ISMEA and BVMEA pins are divided down and compared to the internal 2.5 V reference of the AD8450. In this configuration, the FAULT pin registers a logic low (a fault condition) when VISMEA >

R1 + R2 R2

VBVMEA > VOVP_REF ISVP +

ISMEA

PGIA

ISVN

–

BVPx

× 2.5 V

+

BVMEA

PGDA –

BVNx

or R3 + R4 R3

OVPS

× 2.5 V

VOVP_REF

OVPR

+ –

+ – VOCP_REF

ISVP +

ISMEA

+ –

ISVN

–

R1

BVPx

–

BVNx

R3 OVPS OVPR R4

+ –

NOR

VREF OCPR OCPS

FAULT

– +

Figure 57. OVP and OCP Comparator Configuration Using an External Reference (For Example, a DAC)

+ PGDA

OCPR OCPS

PGIA

BVMEA

NOR

FAULT

– + 11966-056

R2

Figure 56. OVP and OCP Comparator Configuration Using the Internal Reference

Rev. B | Page 27 of 41

11966-057

VBVMEA >

AD8450

Data Sheet

CURRENT SHARING BUS AND IMAX OUTPUT

By means of external resistors, the uncommitted operational amplifier is configured as a difference amplifier to measure the voltage difference between the IMAX and ISMEA nodes.

Battery formation and test systems that use multiple channels bridged together to condition high current battery cells require circuitry to balance the total output current among the channels. Current balance, or current sharing (CS), can be implemented by actively matching the output current of each channel during the battery charge/discharge process.

During the charge process, the charging current and, therefore, the voltage at the ISMEA pin, is slightly different in each channel due to mismatches in the components that make up each channel. Because the CS bus amplifiers are driven by their respective PGIAs and have output stages that can only pull up their output nodes, the amplifier that requires the highest voltage takes control of the CS bus. Therefore, the voltage at the CS bus is pulled up to match the VISMEA voltage of the channel with the largest output current.

The current sharing bus amplifier is a precision unity-gain specialty amplifier with an output stage that can only pull up its output node (the CSH pin). The amplifier is configured as a unity-gain buffer with its input connected to the ISMEA pin (the output of the PGIA). If the CSH pin is left unconnected, the voltage at the pin is a replica of the voltage at the ISMEA pin.

The output voltage of the uncommitted op amp in each channel is proportional to the difference between the channel’s output current and the largest output current. This output voltage can then be used to form a feedback loop that actively corrects the channel’s output current by adjusting the channel’s target current and target voltage, that is, adjusting VISET and VVSET voltages.

Figure 58 is a functional block diagram of the current sharing circuit. In this example, Channel 0 through Channel n are bridged together to charge a high current battery. The CS output of each channel is tied to a common bus (CS bus), which is buffered by the CS buffer amplifier to the IMAX pin.

CHANNEL 0

I_0

CS BUS AMPLIFIER ISVP I_0

+

ISVN

+

1

PGIA

RS0

UNCOMMITTED OP AMP

CS BUFFER

+

–

–

–

I_1 I_n ISMEA

AVEE

CS

OAVP

IMAX

OAVN

OAVO

R IBAT

R R CHANNEL 0

R

CORRECTION SIGNAL VCS − VISMEA

CHANNEL 1

CS BUS

Figure 58. Functional Block Diagram of the Current Sharing Circuit

Rev. B | Page 28 of 41

11966-158

CHANNEL n

Data Sheet

AD8450

APPLICATIONS INFORMATION This section describes how to use the AD8450 in the context of a battery formation and test system. This section includes a design example of a small scale model of an actual system. An evaluation board for the AD8450 is available and is described in the Evaluation Board section.

FUNCTIONAL DESCRIPTION The AD8450 is a precision analog front end and controller for battery formation and test systems. These systems use precision controllers and power stages to put batteries through charge and discharge cycles. Figure 59 shows the signal path of a simplified switching battery formation and test system using the AD8450 controller and the ADP1972 PWM controller. For more information about the ADP1972, see the ADP1972 data sheet. The AD8450 is suitable for systems that form and test NiCad, NiMH, and Li-Ion batteries and is designed to operate in conjunction with both linear and switching power stages. The AD8450 includes the following blocks (see Figure 49 and the Theory of Operation section for more information).   













Pin programmable gain instrumentation amplifier (PGIA) that senses low-side or high-side battery current. Pin programmable gain difference amplifier (PGDA) that measures the terminal voltage of the battery. Two loop filter error amplifiers that receive the battery target current and voltage and establish the dynamics of the constant current (CC) and constant voltage (CV) feedback loops. Minimum output selector circuit that combines the outputs of the loop filter error amplifiers to perform automatic CC to CV switching. Output clamp amplifier that drives the VCTRL pin. The voltage range of this amplifier is bounded by the voltage at the VCLP and VCLN pins such that it cannot overrange the subsequent stage. The output clamp amplifier can drive switching and linear power converters. Note that an increasing voltage at the VCTRL pin must translate to a larger output current in the power converter. Overcurrent and overvoltage comparators whose outputs are combined using a NOR gate to drive the FAULT pin. The FAULT pin presents a logic low when either comparator is tripped. 2.5 V reference that can be used as the reference voltage for the overcurrent and overvoltage comparators. The output node of the 2.5 V reference is the VREF pin. Current sharing amplifier that detects the maximum battery current among several charging channels and whose output can be used to implement current balancing. Logic input pin (MODE) that changes the configuration of the controller from charge to discharge mode. A logic high at the MODE pin configures charge mode; a logic low configures discharge mode.

POWER SUPPLY CONNECTIONS The AD8450 requires two analog power supplies (AVCC and AVEE), one digital power supply (DVCC), one analog ground (AGND), and one digital ground (DGND). AVCC and AVEE power all the analog blocks, including the PGIA, PGDA, op amps, and comparators. DVCC powers the MODE input logic circuit and the FAULT output logic circuit. AGND provides a reference and return path for the 2.5 V reference, and DGND provides a reference and return path for the digital circuitry. The rated absolute maximum value for AVCC − AVEE is 36 V, and the minimum operating AVCC and AVEE voltages are +5 V and −5 V, respectively. Due to the high PSRR of the AD8450 analog blocks, AVCC can be connected directly to the high current power bus (the input voltage of the power converter) without risking the injection of supply noise to the controller outputs. A commonly used power supply combination is +25 V and −5 V for AVCC and AVEE, and +5 V for DVCC. The +25 V rail for AVCC provides enough headroom to the PGIA such that it can be connected in a high-side current sensing configuration with up to four batteries in series (4S). The −5 V rail for AVEE allows the PGDA to sense accidental reverse battery conditions (see the Reverse Battery Conditions section). Connect decoupling capacitors to all the supply pins. A 1 μF capacitor in parallel with a 0.1 μF capacitor is recommended.

POWER SUPPLY SEQUENCING  As detailed in the absolute maximum ratings table (see Table 2), the voltage at any input pin other than ISVP, ISVN, BVPx, and BVNx cannot exceed the positive analog supply (AVCC) by more than 0.5 V and cannot be exceeded by the analog negative supply (AVEE) by 0.5V. Additionally, supply and ground pins (DVCC, DGND, and AGND) cannot exceed the positive analog supply (AVCC) by more than 0.5 V and cannot be exceeded by the analog negative supply (AVEE) by 0.5V. Therefore, power-on and power-off sequencing may be required to comply with the absolute maximum ratings. Failure to comply with the absolute maximum ratings can result in functional failure or damage to the internal ESD diodes. Damaged ESD diodes can cause parametric failures and cannot provide full ESD protection, reducing reliability.

POWER-ON SEQUENCE To power on the device, take the following steps: 1. 2. 3. 4.

Turn on AVCC Turn on AVEE Turn on DVCC Turn on the input signals

The positive analog supply (AVCC) and the negative analog supply (AVEE) may be turned on simultaneously.

Rev. B | Page 29 of 41

AD8450

Data Sheet

POWER-OFF SEQUENCE

Table 5. PGIA Gain Connections

To power off the device, take the following steps:

PGIA Gain 26 66 133 200

Turn off the input signals. Turn off DVCC. Turn off AVEE. Turn off AVCC.

PGIA CONNECTIONS For a description of the PGIA, see the Theory of Operation section, Figure 49, and Figure 51. The internal gains of the PGIA (26, 66, 133, and 200) are selected by hardwiring the appropriate pin combinations (see Table 5). CONSTANT VOLTAGE LOOP FILTER AMPLIFIER

ISET

VCTRL

LEVEL SHIFTER

ADP1972 PWM

C

OUTPUT DRIVERS

OUTPUT FILTER

D

DC-TO-DC POWER CONVERTER

AD8450 CONTROLLER

IVE0

C = CHARGE D = DISCHARGE IVE1

D VVE0

C VVE1

FAULT

VINT

BATTERY CURRENT

NOR OVERVOLTAGE COMPARATOR

OVERCURRENT COMPARATOR ISVP +

+

OVPS

OVPR VREF

OCPR

SENSE RESISTOR

PGIA –

OCPS

ISVN

EXTERNAL PASSIVE COMPENSATION NETWORK

ISMEA BVMEA

BVPx + BATTERY

PGDA –

Figure 59. Complete Signal Path of a Battery Test or Formation System Suitable for Li-Ion Batteries

Rev. B | Page 30 of 41

BVNx

11966-059

D VVP0

C CV BUFFER

AVEE MODE SWITCHES (3)

–

VSETBF

1×

CC AND CV GATES

+ –

VSET

1×

AVCC

VINT BUFFER

+ –

CONSTANT CURRENT LOOP FILTER AMPLIFIER

SET BATTERY VOLTAGE

Gain = 2 × (1 + 20 kΩ/RG)

–

SET BATTERY CURRENT

Connect RGN (Pin 19) to ISGN0 (Pin 17) ISGN1 (Pin 15) ISGN2 (Pin 13) ISGN3 (Pin 12)

If a different gain value is desired, connect 10 kΩ feedback resistors between the inverting inputs of the PGIA preamplifiers (RGP and RGN pins) and the outputs of the PGIA preamplifiers (RFBP and RFBN pins). Also, connect a gain resistor (RG) between the RGP and RGN pins. When using external resistors, the gain of the PGIA is

The positive analog supply (AVCC) and the negative analog supply (AVEE) may be turned off simultaneously.

+

1. 2. 3. 4.

Connect RGP (Pin 2) to ISGP0 (Pin 4) ISGP1 (Pin 6) ISGP2 (Pin 8) ISGP3 (Pin 9)

Data Sheet

AD8450

Current Sensors

Set the PGDA gain value to attenuate the voltage of up to four 5 V battery cells in series to a full-scale voltage of 4 V. For example, a 5 V battery voltage is attenuated to 4 V using the gain of 0.8, and a 20 V battery voltage (four 5 V batteries in series) is attenuated to 4 V using the gain of 0.2. This voltage scaling enables the use of a 5 V ADC to read the battery voltage at the BVMEA output pin.

Two common options for current sensors are isolated current sensing transducers and shunt resistors. Isolated current sensing transducers are galvanically isolated from the power converter and are affected less by the high frequency noise generated by switch mode power supplies. Shunt resistors are less expensive and easier to deploy. If a shunt resistor sensor is used, a 4-terminal, low resistance shunt resistor is recommended. Two of the four terminals conduct the battery current, whereas the other two terminals conduct virtually no current. The terminals that conduct no current are sense terminals that are used to measure the voltage drop across the resistor (and, therefore, the current flowing through it) using an amplifier such as the PGIA of the AD8450. To interface the PGIA with the current sensor, connect the sense terminals of the sensor to the ISVP and ISVN pins of the AD8450 (see Figure 60).

Optional Low-Pass Filter The AD8450 is designed to control both linear regulators and switching power converters. Linear regulators are generally noise free, whereas switch mode power converters generate switching noise. Connecting an external differential low-pass filter between the current sensor and the PGIA inputs reduces the injection of switching noise into the PGIA (see Figure 60). ISVP

4-TERMINAL IBAT SHUNT

RGP

DUT

+ –

RFBP ISGPx LPF

10kΩ

IBAT_SS =

10kΩ

11966-060

–

Figure 60. 4-Terminal Shunt Resistor Connected to the Current Sense PGIA

In constant voltage mode, when the CV feedback loop is in steady state, the VSET input sets the battery voltage as follows:

PGDA CONNECTIONS

VBAT_SS =

For a description of the PGDA, see the Theory of Operation section, Figure 49, and Figure 52. The internal gains of the PGDA (0.2, 0.27, 0.4, and 0.8) are selected by connecting the appropriate input pair to the battery terminals (see Table 6). Table 6. PGDA Gain Connections PGDA Gain 0.8 0.4 0.27 0.2

Connect Battery Positive Terminal to BVP0 (Pin 25) BVP1 (Pin 24) BVP2 (Pin 23) BVP3 (Pin 22)

VISET G IA × RS

where: GIA is the PGIA gain. RS is the value of the shunt resistor.

20kΩ

RGN +

The voltages at the ISET and VSET input pins set the target battery current and voltage for the constant current (CC) and constant voltage (CV) loops. These inputs must be driven by a precision voltage source (or a DAC connected to a precision reference) whose output voltage is referenced to the same voltage as the PGIA and PGDA reference pins (ISREFH/ISREFL and BVREFH/BVREFL, respectively). For example, if the PGIA reference pins are connected to AGND, the voltage source connected to ISET must also be referenced to AGND. In the same way, if the PGDA reference pins are connected to AGND, the voltage source connected to VSET must also be referenced to AGND.

+ –

RFBN

ISVN

BATTERY CURRENT AND VOLTAGE CONTROL INPUTS (ISET AND VSET)

10kΩ

RGn ISGNx

The output voltage of the AD8450 PGDA can be used to detect a reverse battery connection. A −5 V rail for AVEE allows the output of the PGDA to go below ground when the battery is connected backward. Therefore, the condition can be detected by monitoring the BVMEA pin for a negative voltage.

In constant current mode, when the CC feedback loop is in steady state, the ISET input sets the battery current as follows:

20kΩ 10kΩ

Reverse Battery Conditions

VVSET G DA

where GDA is the PGDA gain. Therefore, the accuracy and temperature stability of the formation and test system are dependent not only on the precision of the AD8450, but also on the accuracy of the ISET and VSET inputs.

Connect Battery Negative Terminal to BVN0 (Pin 31) BVN1 (Pin 32) BVN2 (Pin 33) BVN3 (Pin 34)

Rev. B | Page 31 of 41

AD8450

Data Sheet

LOOP FILTER AMPLIFIERS The AD8450 has two loop filter amplifiers, also known as error amplifiers (see Figure 59). One amplifier is for constant current control (CC loop filter amplifier), and the other amplifier is for constant voltage control (CV loop filter amplifier). The outputs of these amplifiers are combined using a minimum output selector circuit to perform automatic CC to CV switching. Table 7 lists the inputs of the loop filter amplifiers for charge mode and discharge mode. Table 7. Integrator Input Connections Feedback Loop Function Control the Current While Discharging a Battery Control the Current While Charging a Battery Control the Voltage While Discharging a Battery Control the Voltage While Charging a Battery

Reference Input ISET

Feedback Terminal IVE0

ISET

IVE1

VSET

VVE0

VSET

VVE1

OVERVOLTAGE AND OVERCURRENT COMPARATORS The reference inputs of the overvoltage and overcurrent comparators can be driven with external voltage references or with the internal 2.5 V reference (adjacent VREF pin). If external voltage references are used, the sense inputs can be driven directly by the PGIA and PGDA output nodes, ISMEA and BVMEA, respectively. If the internal 2.5 V reference is used, the sense inputs can be driven by resistor dividers, which attenuate the voltage at the ISMEA and BVMEA nodes. For more information, see the Overcurrent and Overvoltage Comparators section.

STEP BY STEP DESIGN EXAMPLE This section describes the systematic design of a 1 A battery charger/discharger using the AD8450 controller and the ADP1972 pulse-width modulation (PWM) controller. The power converter used in this design is a nonisolated buck boost dc-to-dc converter. The target battery is a 4.2 V fully charged, 2.7 V fully discharged Li-Ion battery.

Step 1: Design the Switching Power Converter

The CC and CV amplifiers in charge mode and the CC amplifier in discharge mode are inverting integrators, whereas the CV amplifier in discharge mode is a noninverting integrator. Therefore, the CV amplifier in discharge mode uses an extra amplifier, the VSET buffer, to buffer the VSET input pin (see Figure 49). Also, the CV amplifier in discharge mode uses the VVP0 pin to couple the signal from the BVMEA pin to the integrator.

CONNECTING TO A PWM CONTROLLER (VCTRL PIN) The VCTRL output pin of the AD8450 is designed to interface with linear power converters and with pulse-width modulation (PWM) controllers such as the ADP1972. The voltage range of the VCTRL output pin is bounded by the voltages at the VCLP and VCLN pins, as follows: VVCLN − 0.5 V < VVCTRL < VVCLP + 0.5 V Because the maximum rated input voltage at the COMP pin of the ADP1972 is 5.5 V, connect the clamp voltages of the output amplifier to +5 V (VCLP) and ground (VCLN) to prevent overranging of the COMP input. As an additional precaution, install an external 5.1 V Zener diode from the COMP pin to ground with a series 1 kΩ resistor connected between the VCTRL and COMP pins. Consult the ADP1972 data sheet for additional applications information. Given the architecture of the AD8450, the controller requires that an increasing voltage at the VCTRL pin translate to a larger output current in the power converter. If this is not the case, a unity-gain inverting amplifier can be added in series with the AD8450 output to add an extra inversion.

Select the switches and passive components of the buck boost power converter to support the 1 A maximum battery current. The design of the power converter is beyond the scope of this data sheet; however, there are many application notes and other helpful documents available from manufacturers of integrated driver circuits and power MOSFET output devices that can be used for reference.

Step 2: Identify the Control Voltage Range of the ADP1972 The control voltage range of the ADP1972 (voltage range of the COMP input pin) is 0.5 V to 4.5 V. An input voltage of 4.5 V results in the highest duty cycle and output current, whereas an input voltage of 0.5 V results in the lowest duty cycle and output current. Because the COMP pin connects directly to the VCTRL output pin of the AD8450, the battery current is proportional to the voltage at the VCTRL pin. For information about how to interface the ADP1972 to the power converter switches, see the ADP1972 data sheet.

Step 3: Determine the Control Voltage for the CV Loop and the PGDA Gain The relationship between the control voltage for the CV loop (the voltage at the VSET pin), the target battery voltage, and the PGDA gain is as follows: CV Battery Target Voltage =

VVSET PGDA Gain

In charge mode, for a CV battery target voltage of 4.2 V, the PGDA gain of 0.8 maximizes the dynamic range of the PGDA. Therefore, select a CV control voltage of 3.36 V. In discharge mode, for a CV battery target voltage of 2.7 V, the CV control voltage is 2.16 V.

Rev. B | Page 32 of 41

Data Sheet

AD8450

Step 4: Determine the Control Voltage for the CC Loop, the Shunt Resistor, and the PGIA Gain The relationship between the control voltage for the CC loop (the voltage at the ISET pin), the target battery current, and the PGIA gain is as follows: CC Battery Target Current =

VISET RS × PGIA Gain

The voltage across the shunt resistor is as follows: Shunt Resistor Voltage =

VISET PGIA Gain

Selecting the highest PGIA gain of 200 reduces the voltage across the shunt resistor, minimizing dissipated power and inaccuracies due to self heating. For a PGIA gain of 200 and a target current of 1 A, choosing a 20 mΩ shunt resistor results in a control voltage of 4 V. When selecting a shunt resistor, pay close attention to the resistor style and construction. For low power applications, many surface-mount (SMD), temperature stable styles are available that solder to a mating pad on a printed circuit board (PCB). For optimum accuracy, specify a 4-terminal shunt resistor that provides separate high current and sense terminals. This type of resistor directs the majority of the battery current through a high current path. An additional pair of terminals provides a separate connection for the input leads to the PGIA, avoiding the power loss inherent to forcing the full battery current through the distance to the PGIA pins. Because the bias current is so low, the sense error is significantly less than if the battery current were to transverse the additional lead length.

Step 5: Choose the Control Voltage Sources The input control voltages (the voltages at the ISET and VSET pins) can be generated by an analog voltage source such as a voltage reference or by a digital-to-analog converter (DAC). In both cases, select a device that provides a stable, low noise output voltage. If a DAC is preferred, Analog Devices offers a wide range of precision converters. For example, the AD5668 16-bit DAC provides up to eight 0 V to 4 V sources when connected to an external 2 V reference. To maximize accuracy, the control voltage sources must be referenced to the same potential as the outputs of the PGIA and PGDA. For example, if the PGIA and PGDA reference pins are connected to AGND, connect the reference pins of the control voltage sources to AGND.

Step 6: Select the Compensation Devices Feedback controlled switching power converters require frequency compensation to guarantee loop stability. There are many references available about how to design the compensation for such power converters. The AD8450 provides active loop-filter erroramplifiers for the CC and CV control loops that can implement PI, PD, and PID compensators using external passive components.

ADDITIONAL INFORMATION Additional information relative to using the AD8450 is available in the AN-1319, Compensator Design for a Battery Charge/Discharge Unit Using the AD8450 or the AD8451.

Rev. B | Page 33 of 41

AD8450

Data Sheet

EVALUATION BOARD INTRODUCTION

FEATURES AND TESTS

Figure 61 is a photograph of the AD8450-EVALZ. The evaluation board is a convenient standalone platform for evaluating the major elements of the AD8450 (such as the PGIA and PGDA). The circuit architecture is particularly suitable for evaluating PID loop compensation when connected within an operating charge/discharge system. Four separate loop dynamic networks are available for constant current charge and discharge, and constant voltage charge and discharge. The network subcircuits are shown on the right hand side of the board schematic (Figure 62).

The AD8450-EVALZ contains many user friendly features to facilitate evaluation of the AD8450 performance. Numerous connectors, test loops, and points facilitate the attachment of scope probes and cables, and I/O switches conveniently exercise various device options. The schematic item abbreviation TP signifies a test loop. Prior to testing, install Jumpers TST1 through TST5 and move the Shunts RUN1 through RUN5 to a single pin to open the connection. Connect +25 V at AVCC, −5 V at AVEE, and +5 V at DVCC.

PGIA and Offset PGIA Gain Test Apply 10 mV dc across TPISVP and TPISVN. For bench testing, connect ISVN to ground using an external jumper. Use the ISGN switch to select the desired PGIA gain option, and measure the output voltage at TPISMEA or TPIMAX (referenced to ground). For gains of 26, 66, 133, and 200, the output voltages are 260 mV, 660 mV, 1.33 V, and 2 V, respectively. Subtract any residual offset voltages from the output reading before calculating the gain.

11966-061

SMA connectors provide shielded access to the highly sensitive programmable gain instrumentation amplifier (PGIA) and the programmable gain difference amplifier (PGDA). SMA connectors ISET and VSET are the constant current and constant voltage control inputs. The ISMEA and VCTRL outputs, current and voltage alarm references, and trigger voltages are accessible for testing. The MODE switch selects either the charge or discharge option. Figure 62 is a schematic of the AD8450-EVALZ. Table 8 lists and describes the various switches and their functions and lists the SMA connector I/O.

TESTING THE AD8450-EVALZ

Figure 61. Photograph of the AD8450-EVALZ

Rev. B | Page 34 of 41

Data Sheet

AD8450

Table 8. AD8450-EVALZ Test Switches and Their Functions Switch ISGN BVGN IS_REF

Function PGIA gain switch PGDA gain switch Selects between offset options for the PGIA

BV_REF

Selects input source option for the BVREFH pin

MODE RUN_TEST1

Selects charge or discharge mode Configures the ISET and VSET inputs to test the integrators.

RUN_TEST2

Configures the ISET and VSET outputs to test the integrators.

1

Operation The ISGN switch selects one of four fixed gain values: 26, 66, 133, or 200. The BVGN switch selects one of four fixed gain values: 0.2, 0.27, 0.4, or 0.8. NORM: 0 V reference. 20mV: offsets the PGIA reference by 20 mV. EXT: An externally supplied reference voltage is applied to the PGIA. NORM: Overvoltage (OV) reference applied. 5mV: The BVDA is offset by 5 mV. EXT: An externally supplied reference voltage is applied to the BVDA. The MODE switch selects CHG (logic high) or DISCH (logic low). RUN: The ISET and VSET inputs are connected to SMA connectors ISET and VSET. TEST: connectors the ISET and VSET inputs to the 2.5 V reference. RUN: configures the ISET and VSET outputs as integrators. TEST: configures the ISET and VSET outputs as followers.

Default Position1 User select N/A NORM

NORM

CHG RUN

RUN

N/A means not applicable.

Table 9. AD8450-EVALZ SMA Connector Functions Connector ISVP ISVN BVP BVN ISET VSET VCTRL CS_BUS

Function Input from the battery current sensor to the PGIA positive input. Input from the battery current sensor to the PGIA negative input. Input from the battery positive voltage terminal to the PGDA positive input. Input from the battery negative voltage terminal to the PGDA negative input. Input to the AD8450 ISET pin. Input to the AD8450 VSET pin. AD8450 control voltage output to the PWM or analog power supply COMP input. AD8450 current sharing input/output bus.

PGIA in an Application The differential inputs of the PGIA assume the use of a highside current shunt in series with the battery. To connect the evaluation board in an application, simply connect the ISVP and ISVN to the positive and negative shunt connections. Be sure that both inputs are floating (ungrounded). The ISVP and ISVN inputs tolerate the full AVCC common-mode voltage applied to the board.

Simple Offset Test

PGDA and Offset Simple Test The PGDA has four gain options (0.8, 0.4, 0.27, and 0.2) selected with the four-position BVGN slide switch. Set the BV_REF switch to the NORM position. Test the PGDA amplifier in the same manner as PGIA. Apply 1 V dc between TPBVP and TPBVN. Measure the output voltages at TPBVMEA. The output voltages are 0.8 V, 0.4 V, 0.27 V, and 0.2 V, respectively, at the four BVGN switch positions.

Short the PGIA inputs from TPISVP to TPISVN to one of the black ground loops. The ISMEA output is 0 V ± the residual offset voltage multiplied by the gain. Move the IS_REF switch to the 20 mV position to increase ISMEA by 20 mV.

PGDA in an Application

Offset in an Application

PGDA Offset

In certain instances, the system operates with various ground voltage levels. Although the PGIA is differential and floating, it may be advantageous to refer the PGIA to a ground at or near the battery load.

The BV_REF offset works just the same as the IS_REF except that the fixed offset is 5 mV. Simply use the BV_REF switch to select the option. For an external offset reference, move the BV_REF switch to EXT and connect a wire from the TPBREFL and TPBREFH test loops to the desired reference points.

For connection to an application, simply connect the input terminal across the battery. It is good practice to take advantage of the differential input to achieve the most accurate measurements.

Rev. B | Page 35 of 41

AD8450

Data Sheet

Overload Comparators

CC and CV Integrator Tests

The AD8450 features identical fault sensing comparators for overcurrent (OCPS pin) and overvoltage (OVPS pin) to help protect against battery damage. The reference pins, OVPR and OCPR, are hardwired via 0 Ω resistors, R27 and R28, to the 2.5 V reference. The outputs of the comparators are connected together internally, and are active low in the event of an overdrive of either parameter.

The RUN_TEST1 and RUN_TEST2 switches provide all the circuit switching required to test the integrator. Set RUN_TEST1 to the TEST position and apply 2.5 V to the ISET and VSET inputs; then read 2.5 V at the VCTRL output. Set RUN_TEST2 to TEST_CC, then TEST_CV, and the VCTRL output voltage still measures 2.5 V.

For reference, the sense pins are set at 20% greater than the reference. For other sense voltage ratios, simply calculate a new value for the resistor divider. The 2.49 kΩ resistor was selected as an easy equivalent to the 2.5 V reference, the 499 Ω resistors to the ISMEA and BVMEA as 20% greater. These values were selected for an experimental 1 A charge/discharge system built in the lab. Other ratios and values are user selected.

The uncommitted op amp is configured as a follower (R24 is installed between the OAVN pin and the OAVO pin). The input pin, OAVP, is jumper connected to ground via OAVP. To test the uncommitted op amp, simply connect a jumper from TP2.5V and Pin 1 of Jumper OAVP. The output TPOAVO reads 2.5 V.

As a basic test or experiment, simply apply enough voltage at the PGIA or PGDA inputs to exceed 3 V at ISMEA or BVMEA. The FAULT output pin switches from 5 V to 0 V if either input exceeds the sense trigger level.

VSET Buffer The VSET buffer is a unity gain, voltage follower pin accessible for testing. Apply a voltage up to 5 V at the VSET input, and measure the output at TPVSETBF.

CV and CC Loop Filter Amplifiers The constant voltage (CV) and constant current (CC) integrators are identical circuits and are the two active integrator elements of the master loop compensation and switching block (see Figure 49). Except for their external connections, the two circuits are identical and are tested in the same way, sequentially. The integrator outputs are analog OR’ed together, creating the VCTRL output to the input of an external pulse-width modulation controller. As shown in Figure 49, the integrator op amp inputs are called IVE0, IVE1, VVE0, VVE1, and VVP0. The first two letters (IV or VV) signify the constant current or constant voltage integrator. The third letter identifies the noninverting input (P) or the inverting input (E for error input). The final digit (0 or 1) indicates the state of the mode circuit (0 for discharge and 1 for charge). Because the integrators are connected in parallel, a static test of either integrator requires disabling the other by forcing the output to the supply rail, reverse biasing the transistor/diode gate.

Uncommitted Op Amp

USING THE AD8450 Except for the power converter and accessories, such as filters and current sensing, the AD8450-EVALZ includes all of the signal path elements necessary to implement a battery charging/ forming system (see Figure 59). The AD8450 is usable with either linear or switch mode power converters. Switching converters typically generate higher noise levels than linear; however, switching converters are the most popular by far because of significantly higher efficiency and lower cost. Regardless of the power converter architecture used, the PID loop must be configured to reflect the phase shift and gain of the power stage. Circuit simulation is helpful with this task. On the right hand side of Figure 62 are four universal loop compensation circuits. All or part of the circuits are usable for installing fixed components when the AD8450-EVALZ is connected to a battery system for design verification. There are two feedback amplifiers, but four potentially distinctive separate configurations. The types and values of passive components vary according to the power converter and its characteristics. To use the board for setting up a charging system, replace the 10 kΩ resistors in the feedback (there are no capacitors installed) and connect the measured feedback voltages by installing jumpers RUN1 through RUN5. Remove jumpers TST1 through TST5 and install capacitors associated with the integrator.

Rev. B | Page 36 of 41

CS

+5V

+ C8 10 µF 35V

DVCC

25V

+ C4 10 µF 35 V

25 V

5V

8

ISVN

½ ISGN

AVCC

−5V

3

5

1

200

4

2

26

133

66

R21 0Ω

10

17 ISGN0 18 RGNS

ISGN0

ISGN0S

15 ISGN1 16 ISGN0S

12 ISGN3 13 ISGN2 14 ISGN1S

9 ISGP3 10 RFBP 11 RFBN

7 ISGP1S 8 ISGP2

3 RGPS 4 ISGP0 5 ISGP0S 6 ISGP1

1 ISVP 2 RGP

R22 0Ω

TPISREFL

ISGN1

ISGN1S

ISGN2

RFBN ISGN3

RFBP

ISGP3

ISGP1S ISGP2

ISGPOS ISGP1

RGPS ISGP0

RGP

TPISVP

OAVP

ISREFL

IAREF

BVP3S

GND_BVP

TPBVP

½ BVGN

0.2

1

0.27

3

2 4

RGNS RGN 19 RGN ISVN 20 ISVN TPISVN

TPRGN

200

9 133

26 6 7 66

½ ISGN

TPRGP

TP _IMAX

−5V C7 10 µF + 35 V

TPAVEE

ISVP

CS _BUS

AVCCRET

DVCCRET

5

8

5

TPOAVP

7

2.5V

BVP

TP 2.5V

0.8

0.4

2

6

4 EXT

NORM 1 3

20mV

C5 10 µF 10V

2

3 5mV

4

5 NORM

BVREF

TPBREFH

7

6

8 EXT

7

BVN

6

0.8

0.4

AD8450 X1

C18 10µF DAREF 10V BVDAREF

1

C20 1 µF 50V

ISET

VSET

8

9

½ BVGN

2

3

GND_BVN

TPBVN

10

0.2

0.27

2

3 RUN

TP_VSET TP_ISET

OAVN R24 0Ω

TPISMEA −5V

TP _ISREFH

24 BVP1 25 BVP0

2.5V

IS_REF

VREF 26 VREF 27 BVREFH

AVEERET

BVP3

AGND 75 ISREFH 74 VREF 73 BREFH

ISIAREF

BVP2

CR3 5.1V

R20 1kΩ

TEST 1

1

RUN_ TEST1

25V

C9 0.1µF 50V

C21 1µF 50V

DVCC 47

DISCH

3

TPBVMEA

MODE

1

2

CLMP_ VCTRL

R17 0Ω

R28 0Ω

R27 0Ω

R29 2.49kΩ

C19 10µF 10V

ISMEA

C25 0.1µF 50V

VSET

CR1 TPVCLN 5.1V

R31 2.49kΩ

R25 499Ω

4

T_CC 3 T_CV

TPVCTRL R18 1kΩ

R30 499Ω

DRVOVPS

OVPR

OCPR

OCPS

FAULT

5V CHG 2

TPMODE

OVPR 41

OCPR 43 VREF 42

OCPS 44

FAULT 46 DGND 45

1 RUN

RUN_ TEST2

VINT

TPVSETBF TPVSET

VSET 49 NC 48 NC 5V

NC 52 NC VVP0 51 VSETBF 50

NC 55 NC VVE1 VVE1 54 VVE0 53

AVCC 57 VINT 56

VCLN 58 VINT

TPVCLP

5V

VSET

R16 0Ω

CR2 5.1V

−5V

2.5V

TP−5V

R19 1kΩ

VCLP 60 VCTRL 59

VINT 62 AVEE 61

GND 5 GND 6 GND 7 GND 8

BVP1

AVEE 72 ISMEA 71

28 AGND TPBREFL BREFL 29 BVREFL BREFLS 30 BVREFLS BVN0 31 BVN0 BVN1 32 BVN1

CSH 80 IMAX 79 BVP0

IVE0 65 IVE1 64 NC 63 NC

BVN3S 35 BVN3S −5V 36 AVEE BVMEA 37 BVMEA

ISREFLS OAVP 78 ISREFLS 77 ISREFL 76

21 BVP3S 22 BVP3 23 BVP2

AVCC 70 25V OAVN 69 OAVO OAVO 68 ISET 67 NC 66 NC 33 BVN2 34 BVN3 BVN2

Figure 62. Schematic of the AD8450 Evaluation Board BVN3

Rev. B | Page 37 of 41 38 AVCC MODE 39 MODE OVPS 40 OVPS

GND 1 GND 2 GND 3 GND 4

5

7

6

VVE1

VCTRL

TVVE1 8

BVMEA

VVP0

VSETBF

BVMEA

ISMEA

ISMEA TP7 TP8

TP5

RUN 5

R11 0Ω TP4

TP3

RUN 4

R6 0Ω

TP12

TP6

CV -DISCHARGE

TP25

R12 0Ω TP26

RUN 3

CV -CHARGE

TP2

RUN 2

R1 0Ω

CC -DISCHARGE

RUN 1

R7 0Ω

TP36

R2 10 kΩ

TP9

TP24

TP27

TP38

TP34

TP39

TP35

R13 10 kΩ

TP32

C22 TBD DNI

TP17

R10 10 kΩ

TP31

C12 TBD DNI

TP23

TP33

R14 10 kΩ

TP30

VVP0

VVE0

TP45

TP46

TP44

TP51

TP47

TP52

TP19

TP62

TP63

TST 5

TP60

C19 TBD DNI

TP59

TST 4

TP58

C11 TBD DNI

TP57

TST 3

TP50 TP56

C13 TBD DNI

R9 10 kΩ

TP43

TP18

C24 TBD DNI

C15 TBD DNI

R5 10 kΩ

TP42

TP61

TST 2

TP49 TP55

C10 TBD DNI

TP54

C17 TBD DNI

R15 10 kΩ

TP41

R4 10 kΩ

TP14

TP1

TST 1

TP53

C14 TBD DNI

TP48

C6 TBD DNI

TP13

C3 TBD DNI TP11

R3 10 kΩ TP40

TVVE1

IVE0

TIVE1

TVVE1

(5)

TP37

C23 TBD DNI

TP16

TP10

R8 10 kΩ

TP29

C1 TBD DNI

TP15

TP28

LOOP COMPENSATION FIELD C2 TBD DNI

CC -CHARGE

VINT

Data Sheet AD8450

SCHEMATIC AND ARTWORK 11966-062

Data Sheet

11966-063

AD8450

11966-064

Figure 63. Top Silkscreen of the AD8450-EVALZ

Figure 64. AD8450-EVALZ Primary Side Copper

Rev. B | Page 38 of 41

AD8450

11966-065

Data Sheet

11966-066

Figure 65. AD8450-EVALZ Secondary Side Copper

Figure 66. AD8450-EVALZ Power Plane

Rev. B | Page 39 of 41

Data Sheet

11966-067

AD8450

Figure 67. AD8450-EVALZ Ground Plane

Rev. B | Page 40 of 41

Data Sheet

AD8450

OUTLINE DIMENSIONS 0.75 0.60 0.45

16.20 16.00 SQ 15.80

1.60 MAX

61

80

60

1 PIN 1

14.20 14.00 SQ 13.80

TOP VIEW (PINS DOWN)

0.15 0.05

SEATING PLANE

0.20 0.09 7° 3.5° 0° 0.10 COPLANARITY

VIEW A

20

41 40

21

VIEW A

0.65 BSC LEAD PITCH

ROTATED 90° CCW

0.38 0.32 0.22

COMPLIANT TO JEDEC STANDARDS MS-026-BEC

051706-A

1.45 1.40 1.35

Figure 68. 80-Lead Low Profile Quad Flat Package [LQFP] (ST-80-2) Dimensions shown in millimeters

ORDERING GUIDE Model 1 AD8450ASTZ AD8450ASTZ-RL AD8450-EVALZ 1

Temperature Range −40°C to +85°C −40°C to +85°C

Package Description 80-Lead Low Profile Quad Flat Package [LQFP] 80-Lead Low Profile Quad Flat Package [LQFP] Evaluation Board

Z = RoHS Compliant Part.

©2014–2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D11966-0-8/15(B)

Rev. B | Page 41 of 41

Package Option ST-80-2 ST-80-2