Idea Transcript
PLL Frequency Synthesizer ADF4108
Data Sheet FEATURES
GENERAL DESCRIPTION
8.0 GHz bandwidth 3.2 V to 3.6 V power supply Separate charge pump supply (VP) allows extended tuning voltage in 3.3 V systems Programmable, dual-modulus prescaler 8/9, 16/17, 32/33, or 64/65 Programmable charge pump currents Programmable antibacklash pulse width 3-wire serial interface Analog and digital lock detect Hardware and software power-down mode Loop filter design possible with ADIsimPLL 4 mm × 4 mm, 20-lead chip scale package
The ADF4108 frequency synthesizer can be used to implement local oscillators in the upconversion and downconversion sections of wireless receivers and transmitters. It consists of a low noise digital PFD (phase frequency detector), a precision charge pump, a programmable reference divider, programmable A and B counters, and a dual-modulus prescaler (P/P + 1). The A (6-bit) and B (13-bit) counters, in conjunction with the dual-modulus prescaler (P/P + 1), implement an N divider (N = BP + A). In addition, the 14-bit reference counter (R counter), allows selectable REFIN frequencies at the PFD input. A complete phase-locked loop (PLL) can be implemented if the synthesizer is used with an external loop filter and voltage controlled oscillator (VCO). Its very high bandwidth means that frequency doublers can be eliminated in many high frequency systems, simplifying system architecture and reducing cost.
APPLICATIONS Broadband wireless access Satellite systems Instrumentation Wireless LANs Base stations for wireless radio
FUNCTIONAL BLOCK DIAGRAM AVDD
DVDD
VP
RSET
CPGND REFERENCE
14-BIT R COUNTER
REFIN
PHASE FREQUENCY DETECTOR
CHARGE PUMP
CP
14 R COUNTER LATCH CLK DATA LE
24-BIT INPUT REGISTER
FUNCTION LATCH
22
FROM SDOUT FUNCTION LATCH
A, B COUNTER LATCH
CURRENT SETTING 1
CURRENT SETTING 2
CPI3 CPI2 CPI1
CPI6 CPI5 CPI4 HIGH-Z
19
AVDD
MUXOUT
MUX
13
N = BP + A
RFINA RFINB
LOCK DETECT
13-BIT B COUNTER
SDOUT
LOAD PRESCALER P/P + 1 LOAD
M3 M2 M1
6-BIT A COUNTER
ADF4108
AGND
06015-001
6 CE
DGND
Figure 1.
Rev. E
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ADF4108
Data Sheet
TABLE OF CONTENTS Features .............................................................................................. 1
Phase Frequency Detector and Charge Pump........................ 10
Applications ....................................................................................... 1
MUXOUT and Lock Detect...................................................... 10
General Description ......................................................................... 1
Input Shift Register .................................................................... 10
Functional Block Diagram .............................................................. 1
Latch Summary........................................................................... 11
Revision History ............................................................................... 2
Reference Counter Latch Map .................................................. 12
Specifications..................................................................................... 3
AB Counter Latch Map ............................................................. 13
Timing Characteristics ................................................................ 5
Function Latch Map ................................................................... 14
Absolute Maximum Ratings............................................................ 6
Initialization Latch Map ............................................................ 15
ESD Caution .................................................................................. 6
Function Latch ............................................................................ 16
Pin Configuration and Function Descriptions ............................. 7
Initialization Latch ..................................................................... 17
Typical Performance Characteristics ............................................. 8
Power Supply Considerations ................................................... 17
Theory of Operation ........................................................................ 9
Interfacing ....................................................................................... 18
Reference Input Stage................................................................... 9
ADuC812 Interface .................................................................... 18
RF Input Stage ............................................................................... 9
ADSP-21xx Interface ................................................................. 18
Prescaler (P/P + 1)........................................................................ 9
PCB Design Guidelines for Chip Scale Package......................... 19
A and B Counters ......................................................................... 9
Outline Dimensions ....................................................................... 20
R Counter ...................................................................................... 9
Ordering Guide .......................................................................... 20
REVISION HISTORY 4/13—Rev. D to Rev. E Changed RFINA to RFINB Parameter from ±320 mV to ±600 mV, Table 3 ................................................................................................ 6
12/07—Rev. 0 to Rev. A
Changes to Figure 3 .......................................................................... 7 Updated Outline Dimensions (Changed CP-20-1 to CP-20-6)...... 20 Changes to Ordering Guide .......................................................... 20
Removed TSSOP Package ................................................. Universal Changes to Features ..........................................................................1 Changes to Table 1 Endnote 10 and Endnote 11...........................4 Changes to Table 3.............................................................................6 Deleted Figure 3 .................................................................................7 Changes to Table 4.............................................................................7 Changes to Figure 10 and Figure 11................................................8 Updated Outline Dimensions ....................................................... 20 Deleted Figure 24............................................................................ 20 Changes to Ordering Guide .......................................................... 20
9/11—Rev. A to Rev. B
4/06—Revision 0: Initial Version
1/13—Rev. C to Rev. D Change to Table 1 .................................................................................... 4 Added RFINA to RFINB Parameter, Table 4 ..................................... 6
7/12—Rev. B to Rev. C
Changes to Normalized Phase Noise Floor (PNSYNTH) Parameter and Endnote 9, Table 1 ..................................................................... 4 Added Normalized 1/f Noise (PN1_f) Parameter and Endnote 10, Table 1 ................................................................................................ 4 Changes to Figure 3 and Table 4 ..................................................... 7 Updated Outline Dimensions ....................................................... 20
Rev. E | Page 2 of 20
Data Sheet
ADF4108
SPECIFICATIONS AVDD = DVDD = 3.3 V ± 2%, AVDD ≤ VP ≤ 5.5 V, AGND = DGND = CPGND = 0 V, RSET = 5.1 kΩ, dBm referred to 50 Ω, TA = TMIN to TMAX, unless otherwise noted. Table 1. Parameter RF CHARACTERISTICS RF Input Frequency (RFIN) RF Input Sensitivity Maximum Allowable Prescaler Output Frequency 3 REFIN CHARACTERISTICS REFIN Input Frequency REFIN Input Sensitivity 4 REFIN Input Capacitance REFIN Input Current PHASE DETECTOR Phase Detector Frequency 6 CHARGE PUMP ICP Sink/Source High Value Low Value Absolute Accuracy RSET Range ICP Three-State Leakage Sink and Source Current Matching ICP vs. VCP ICP vs. Temperature LOGIC INPUTS VIH, Input High Voltage VIL, Input Low Voltage IINH, IINL, Input Current CIN, Input Capacitance LOGIC OUTPUTS VOH, Output High Voltage VOH, Output High Voltage IOH, Output High Current VOL, Output Low Voltage POWER SUPPLIES AVDD DVDD VP IDD (AIDD + DIDD) 7 IP Power-Down Mode (AIDD + DIDD) 8
B Version 1
B Chips 2 (Typ)
Unit
1.0/8.0 −5/+5 300
1.0/8.0 −5/+5 300
GHz min/max dBm min/max MHz max
P=8
325
325
MHz max
P = 16
20/250 0.8/VDD 10 ±100
20/250 0.8/VDD 10 ±100
MHz min/max V p-p min/max pF max µA max
For f < 20 MHz, ensure SR > 50 V/µs Biased at AVDD/2 5
104
104
MHz max
Test Conditions/Comments See Figure 11 for input circuit For lower frequencies, ensure slew rate (SR) > 320 V/µs
Programmable; see Figure 18 5 625 2.5 3.0/11 1 2 1.5 2
5 625 2.5 3.0/11 1 2 1.5 2
mA typ µA typ % typ kΩ typ nA typ % typ % typ % typ
1.4 0.6 ±1 10
1.4 0.6 ±1 10
V min V max µA max pF max
1.4 VDD − 0.4 100 0.4
1.4 VDD − 0.4 100 0.4
V min V min µA max V max
3.2/3.6 AVDD AVDD/5.5 17 0.4 10
3.2/3.6 AVDD AVDD/5.5 17 0.4 10
V min/max V min/max mA max mA max µA typ
Rev. E | Page 3 of 20
With RSET = 5.1 kΩ With RSET = 5.1 kΩ See Figure 18 1 nA typical; TA = 25°C 0.5 V ≤ VCP ≤ VP − 0.5 V 0.5 V ≤ VCP ≤ VP − 0.5 V VCP = VP/2
Open-drain output chosen; 1 kΩ pull-up resistor to 1.8 V CMOS output chosen IOL = 500 µA
AVDD ≤ VP ≤ 5.5 V 15 mA typ TA = 25°C
ADF4108 Parameter NOISE CHARACTERISTICS Normalized Phase Noise Floor (PNSYNTH) 9 Normalized 1/f Noise (PN1_f) 10 Phase Noise Performance 11 7900 MHz Output 12 Spurious Signals 7900 MHz Output12
Data Sheet B Version 1
B Chips 2 (Typ)
Unit
Test Conditions/Comments
−223
−223
dBc/Hz typ
PLL loop B/W = 500 kHz, measured at 100 kHz offset
−122
−122
dBc/Hz typ
−81
−81
dBc/Hz typ
10 kHz offset; normalized to 1 GHz @ VCO output @ 1 kHz offset and 1 MHz PFD frequency
−82
−82
dBc typ
@ 1 MHz offset and 1 MHz PFD frequency
Operating temperature range (B version) is −40°C to +85°C. The B chip specifications are given as typical values. This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency that is less than this value. 4 AVDD = DVDD = 3.3 V. 5 AC coupling ensures AVDD/2 bias. 6 Guaranteed by design. Sample tested to ensure compliance. 7 TA = 25°C; AVDD = DVDD = 3.3 V; P = 32; RFIN = 8 GHz, fPFD = 200 kHz, REFIN = 10 MHz. 8 TA = 25°C; AVDD = DVDD = 3.3 V; R = 16,383; A = 63; B = 891; P = 32; RFIN = 7.0 GHz. 9 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log N (where N is the N divider value) and 10 log FPFD. PNSYNTH = PNTOT − 10 log FPFD − 20 log N. 10 The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency, fRF, and at a frequency offset, f, is given by PN = PN1_f + 10 log(10 kHz/f) + 20 log(fRF/1 GHz). All phase noise measurements were performed with the EV-ADF4108EBZ1 and the Agilent E5500 phase noise system. Both the normalized phase noise floor and flicker noise are modeled in ADIsimPLL. 11 The phase noise is measured with the EV-ADF4108EB1Z evaluation board, with the ZComm CRO8000Z VCO. The spectrum analyzer provides the REFIN for the synthesizer (fREFOUT = 10 MHz @ 0 dBm). 12 fREFIN = 10 MHz; fPFD = 1 MHz; fRF = 7900 MHz; N = 7900; loop B/W = 30 kHz, VCO = ZComm CRO8000Z. 1 2 3
Rev. E | Page 4 of 20
Data Sheet
ADF4108
TIMING CHARACTERISTICS AVDD = DVDD = 3.3 V ± 2%, AVDD ≤ VP ≤ 5.5 V, AGND = DGND = CPGND = 0 V, RSET = 5.1 kΩ, dBm referred to 50 Ω, TA = TMIN to TMAX, unless otherwise noted. Table 2. Parameter1 t1 t2 t3 t4 t5 t6 2
Unit ns min ns min ns min ns min ns min ns min
Test Conditions/Comments DATA to CLOCK setup time DATA to CLOCK hold time CLOCK high duration CLOCK low duration CLOCK to LE setup time LE pulse width
Guaranteed by design but not production tested. Operating temperature range (B Version) is −40°C to +85°C.
t3
t4
CLOCK
t1 DATA
DB23 (MSB)
t2 DB22
DB2
DB1
DB0 (LSB) (CONTROL BIT C1)
t6
(CONTROL BIT C2) LE
t5 06015-002
1
Limit2 (B Version) 10 10 25 25 10 20
LE
Figure 2. Timing Diagram
Rev. E | Page 5 of 20
ADF4108
Data Sheet
ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter AVDD to GND 1 AVDD to DVDD VP to GND VP to AVDD Digital I/O Voltage to GND Analog I/O Voltage to GND REFIN, RFINA, RFINB to GND RFINA to RFINB Operating Temperature Range Industrial (B Version) Storage Temperature Range Maximum Junction Temperature CSP θJA Thermal Impedance (Paddle Soldered) Reflow Soldering Peak Temperature (60 sec) Time at Peak Temperature Transistor Count CMOS Bipolar 1
Rating −0.3 V to +3.9 V −0.3 V to +0.3 V −0.3 V to +5.8 V −0.3 V to +5.8 V −0.3 V to VDD + 0.3 V −0.3 V to VP + 0.3 V −0.3 V to VDD + 0.3 V ±600 mV −40°C to +85°C −65°C to +125°C 150°C 30.4°C/W
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. This device is a high performance RF integrated circuit with an ESD rating of