Idea Transcript
CENG 311 COMPUTER ARCHITECTURE 2017-2018 Fall Semester A.1. Homepage: http://www.iyte.edu.tr/~tolgaayav/courses/ceng311 A.2. Lecture: Tuesday 9:45 - 12:30 (Course), Thursday 10:45 - 12:30 (Lab) A.3. Credits: 3+2 A.4. Instructor: Asst. Prof. Tolga AYAV, Ph.D. (Telephone: 750 7878) A.5. Syllabus A.6. Lab Assistants: B.1. Objective of the Course: Basic computer organization and design. MIPS architecture. Microprocessor design and implementation using FPGAs. VHDL. Assembly. Pipelining and other performance issues. B.2. Prerequisites: CENG214 Logic Design. C.1. Course Contents: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14.
Introduction to Computer Architecture and Basic Computer Organization (Lab: Introduction) Arithmetic for Computers (Lab: Fundamentals of VHDL language) MIPS architecture and Assembly (Lab: VHDL programming and simulation) Design of Dedicated and General-Purpose Datapath (Lab: Datapath implementation and simulation with Modelsim - I ) VHDL, Introduction to FPGA (Lab: Datapath implementation and simulation with Modelsim - II ) Design of a very simple microprocessor: µ311 (week 1) (Lab: Implementation and integration of µ311 units) Design of a very simple microprocessor: µ311 (week 2) (Lab: Testing µ311 microprocessor) Design and Connection of I/O units, Interrupt Mechanism (Lab: Application of interrupt mechanism with µ311) Pipelining, µ311 Assembly (Lab: Development of assembler and linker for µ311) 8086 Based Computer Design (Lab: 8086 Assembly Programming - I ) 8086 Assembly Programming - I (Lab: 8086 Assembly Programming - II ) 8086 Assembly Programming - II (Lab: 8086 Assembly Programming - III ) Segmentation and Paging, Real and Protected modes, Memory Organization (Lab: Fundamentals of Kernel Design) Multitasking (Lab: µOSx311 Micro-Kernel Design)
C.2. Course Schedule: 4/10: Lecture 1 - Introduction 11/10: Lecture 2 - VHDL Programming Language 18/10: Lecture 3 - MIPS architecture and Assembly 25/10: Lecture 4 - Data Path Design 1/11: Design of µ311 microprocessor-1 8/11: Design of µ311 microprocessor-2 15/11: Control Unit Design 22/11: µ311 I/O communication 29/11: µ311 Interrupt mechanism 6/12: 80x86 Architecture 13/12: Assembly Programming in 80x86/Linux - 1 20/12: Assembly Programming in 80x86/Linux - 2 27/12: Kernel Development for 80x86 3/1/2018: Preliminaries of kernel µOSx311 D. Lecture Notes: Lecture -1 Introduction Lecture -2 Intro to VHDL Lecture -3 Datapath Design Lecture -6 I/O Communication Design Notes of Microprocessor µ311 (Last update: 19/12/2017 13:30) (Problematic issues like zero flag, push, pop, call, ret have been corrected.) Assembler for µ311 Executable: as311 (for Linux 64 bit) Source: as311.c Lecture - 8-9-10 80x86 Assembly Programming on Linux ---------------------------------------------------------------Kernel Development for 80x86 IMPORTANT NOTE: The last lecture will be on January 3th at 9:45. We had to move the lab session to its official slot, Thursday Jan 04th, 13:30 since the lab is occupied on Wednesday! Midterm Results (NEW) E. Grading: Written Midterm Exam I: %30 Written Final Exam: %45 Laboratory work: %25 Old exam questions: 2013, 2014 , 2015Final , 2013 Final with answers
F. Books: David A. Patterson, John L. Hennessy. Computer Organization and Design . 3rd Ed. 2005. Morgan Kaufmann Pub
G. Laboratory: Date
Work
Presentation to instructor
5/10
No Lab
12/10
Introduction (Full adder + 8 bit FA)
19/10
ALU Design. Read the feuille.
26/10
DataPath Design (RF,register,buffers,addsub,etc.) Read the feuille.
2/11
Simulation
Datapath simulation
9/11
Control Unit
16/11
Midterm I
23/11
Assembling datapath and control unit design
Completing the processor with datapath and control unit (upabs3.vhd=dp.vhd+cu.vhd). 30/11
7/12
Setting up a test bench with upabs3, clock circuit and 1k ROM (testbench.vhd=clock.vhd+upabs3.vhd+ROM.vhd).
Adding a RAM to the configuration (testbench.vhd=clock.vhd+upabs3.vhd+ROM.vhd+RAM.vhd).
Simulation of the processor. Put this simple program into the ROM: movi a, 82H mov b, a Demonstrate that your microprocessor executes the above program.
Demonstration of the interrupt mechanism.
14/12
Interrupt mechanism. (Connect a ROM as a program memory and a 1k RAM for ISRs and stack. You can use partial address decoding)
Your main program and the interrupt service routine could be as follows: STA: nop mov b, a jmp STA ISR1: movi a, 55 ret No need to use INTA signal, since we have only one interrupt source. Trigger the interrupt by forcing INT pin in the simulator. Place ISR1 code in the appropriate place in the RAM.
21/12
Demonstrate your project with the assembly program provided by the lab instructor during the lab Simulation and Testing of your session. microprocessor.
28/12
Assembly Programming - Linking C and Assembly files . (Read the feuille.)
Demonstrate your program
04/01/2018 Thursday! Demonstration of u311 13:30
OSx311. Download the initial kernel. Read Lab work here.
H. Bibliography: Brey, B.B. (1991). The Intel Microprocessors. 3rd Ed. New York and Toronto : Macmillan. Mano, M. (1988). Computer Engineering: Hardware Design. Englewood Cliffs, NJ: Prentice-Hall . Tanenbaum, A.S. (1999). Structured Computer Organization. 4th Ed. Englewood Cliffs, NJ: Prentice- Hall. Herman Lam, John O'Malley, Fundamentals of Computer Engineering: Logic Design and Microprocessors, Wiley. Enoch O. Hwang, Digital Logic and Microprocessor Design with VHDL.
I. Materials and Useful Links There might be some other materials in password protected area . Please ask the instructor for the username and password of this course.