CMOS RF Circuit for Wireless Applications - Hindawi [PDF]

EURASIP Journal on Wireless Communications and Networking

CMOS RF Circuit for Wireless Applications Guest Editors: Kris Iniewski, Mourad El-Gamal, and Robert Bogdan Staszewski

EURASIP Journal on Wireless Communications and Networking

CMOS RF Circuits for Wireless Applications

EURASIP Journal on Wireless Communications and Networking

CMOS RF Circuits for Wireless Applications Guest Editors: Kris Iniewski, Mourad El-Gamal, and Robert Bogdan Staszewski

Copyright © 2006 Hindawi Publishing Corporation. All rights reserved. This is a special issue published in volume 2006 of “EURASIP Journal on Wireless Communications and Networking.” All articles are open access articles distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Editor-in-Chief Phillip Regalia, Institut National des Telecommunications, France

Associate Editors Thushara Abhayapala, Australia Farid Ahmed, USA Alagan Anpalagan, Canada N. Arumugam, Singapore Anthony Boucouvalas, UK Lin Cai, Canada Biao Chen, USA Pascal Chevalier, France Chia-Chin Chong, USA Huaiyu Dai, USA Soura Dasgupta, USA Petar Djuric, USA Mischa Dohler, France Abraham O. Fapojuwo, Canada Michael Gastpar, USA Alex Gershman, Germany Wolfgang Gerstacker, Germany David Gesbert, France

Fary Z. Ghassemlooy, UK Christian Hartmann, Germany Stefan Kaiser, Germany George K. Karagiannidis, Greece Hyung-Myung Kim, Korea C. C. Ko, Singapore Visa Koivunen, Finland Richard Kozick, USA Bhaskar Krishnamachari, USA Sangarapillai Lambotharan, UK Vincent Lau, Hong Kong David I. Laurenson, UK Tho Le-Ngoc, Canada Tongtong Li, USA Wei Li, USA Yonghui Li, Australia Zhiqiang Liu, USA Stephen McLaughlin, UK

Marc Moonen, Belgium Eric Moulines, France Sayandev Mukherjee, USA Kameswara Rao Namuduri, USA A. Pandharipande, The Netherlands Athina Petropulu, USA H. Vincent Poor, USA Brian Sadler, USA Ivan Stojmenovic, Canada Lee Swindlehurst, USA Sergios Theodoridis, Greece Lang Tong, USA Luc Vandendorpe, Belgium Yang Xiao, USA Xueshi Yang, USA Lawrence Yeung, Hong Kong Dongmei Zhao, Canada Weihua Zhuang, Canada

Contents CMOS RF Circuits for Wireless Applications, Kris Iniewski, Mourad El-Gamal, and Robert Bogdan Staszewski Volume 2006 (2006), Article ID 86753, 2 pages Novel Radio Architectures for UWB, 60 GHz, and Cognitive Wireless Systems, Danijela Cabric, Mike S. W. Chen, David A. Sobel, Stanley Wang, Jing Yang, and Robert W. Brodersen Volume 2006 (2006), Article ID 17957, 18 pages Transceiver Design for Multiband OFDM UWB, D. M. W. Leenaerts Volume 2006 (2006), Article ID 43917, 8 pages Error Control Coding in Low-Power Wireless Sensor Networks: When Is ECC Energy-Efficient?, Sheryl L. Howard, Christian Schlegel, and Kris Iniewski Volume 2006 (2006), Article ID 74812, 14 pages Charge-Domain Signal Processing of Direct RF Sampling Mixer with Discrete-Time Filters in Bluetooth and GSM Receivers, Yo-Chuol Ho, Robert Bogdan Staszewski, Khurram Muhammad, Chih-Ming Hung, Dirk Leipold, and Kenneth Maggio Volume 2006 (2006), Article ID 62905, 14 pages A Sigma-Delta ADC with Decimation and Gain Control Function for a Bluetooth Receiver in 130 nm Digital CMOS, Jinseok Koh, Gabriel Gomez, Khurram Muhammad, R. Bogdan Staszewski, and Baher Haroun Volume 2006 (2006), Article ID 71249, 8 pages Design and Characterization of a 5.2 GHz/2.4 GHz ΣΔ Fractional-N Frequency Synthesizer for Low-Phase Noise Performance, John W. M. Rogers, Foster F. Dai, Calvin Plett, and Mark S. Cavin Volume 2006 (2006), Article ID 48489, 11 pages Noise and Spurious Tones Management Techniques for Multi-GHz RF-CMOS Frequency Synthesizers Operating in Large Mixed Analog-Digital SOCs, Adrian Maxim Volume 2006 (2006), Article ID 24853, 26 pages CMOS Silicon-on-Sapphire RF Tunable Matching Networks, Ahmad Chamseddine, James W. Haslett, and Michal Okoniewski Volume 2006 (2006), Article ID 86531, 11 pages Using MEMS Capacitive Switches in Tunable RF Amplifiers, John Danson, Calvin Plett, and Niall Tait Volume 2006 (2006), Article ID 16518, 9 pages Modeling and Characterization of VCOs with MOS Varactors for RF Transceivers, Pedram Sameni, Chris Siu, Shahriar Mirabbasi, Hormoz Djahanshahi, Marwa Hamour, Krzysztof Iniewski, and Jatinder Chana Volume 2006 (2006), Article ID 93712, 12 pages Parametric Conversion Using Custom MOS Varactors, Howard Chan, Zhongbo Chen, Sebastian Magierowski, and Krzysztof (Kris) Iniewski Volume 2006 (2006), Article ID 12945, 16 pages

Transient and Steady-State Analysis of Nonlinear RF and Microwave Circuits, Lei (Lana) Zhu and Carlos E. Christoffersen Volume 2006 (2006), Article ID 32097, 11 pages

Hindawi Publishing Corporation EURASIP Journal on Wireless Communications and Networking Volume 2006, Article ID 86753, Pages 1–2 DOI 10.1155/WCN/2006/86753

Editorial CMOS RF Circuits for Wireless Applications Kris Iniewski,1 Mourad El-Gamal,2 and Robert Bogdan Staszewski3 1 Department

of Electrical & Computer Engineering, University of Alberta, ECERF Building, Edmonton, AB, Canada T6G 2V4 of Electrical & Computer Engineering, McGill University, McConnell Engineering Building, Room 633, 3480 University Street, Montreal, PQ, Canada H3A-2A7 3 Digital RF Processor Group, Texas Instruments, Dallas, TX 75243, USA 2 Department

Received 20 June 2006; Accepted 20 June 2006 Copyright © 2006 Kris Iniewski et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Advanced concepts for wireless communications present a vision of technology that is embedded in our surroundings and practically invisible, but present whenever required. From established radio techniques like GSM, 802.11, or Bluetooth to more emerging like ultra-wideband (UWB) or smart dust moats, a common denominator for future progress is the underlying CMOS technology. Although the use of deepsubmicron CMOS processes allows for an unprecedented degree of scaling in digital circuitry, it complicates implementation and the integration of traditional RF circuits. The explosive growth of standard cellular radios and radically different new wireless applications makes it imperative to find architectural and circuit solutions to these design problems. This special EURASIP issue contains carefully selected 12 papers that represent state-of-the-art CMOS designs for wireless applications. The first group of three papers from University of California at Berkeley, Philips Research, and the University of Alberta discusses various system aspects in the context of CMOS implementation. Cabric et al. propose novel radio architectures that might be used at 60 GHz and for cognitive radios. Leenaerts presents one of the first CMOS circuit implementations of the ultra-wideband (UWB) technology. Howard et al. delineate conditions under which error control coding (ECC) is efficient from an energy point of view in wireless sensor networks (WSNs). While it is true that heterogeneous circuits and architectures originally developed for their native technologies cannot be effectively integrated “as is” into highly scaled CMOS processes, one might ask the question whether those functions can be ported into more CMOS-friendly architectures to reap all the benefits of the digital design and flow. It is not predestined that RF wireless frequency synthesizers be always charge-pump-based PLLs with VCOs, RF transmit upconverters be I/Q modulators, receivers use only Gilbert cell

or passive continuous-time mixers. Performance of modern CMOS transistors is nowadays good enough for multi-GHz RF applications. The following four papers from Texas Instruments, Carleton University, and Silicon Labs describe the RF CMOS circuit design challenges. Ho et al. present a key component of RF direct processing—the RF sampling mixer. The circuit is used in Bluetooth and GSM applications. Koh et al. propose a novel sigma-delta ADC with embedded decimation and gain control. The remaining two papers in that group address challenges of phase-locked loop (PLL) design for RF applications. Rogers et al. provide a tutorial on phase noise modeling for fractional PLLs, while Maxim presents solutions for effective power supply filtering and their effects on PLL performance. Low power has been always important for wireless communications. With new developments in wireless sensor networks and wireless systems for medical applications, the power dissipation is becoming the number one issue. Traditional wireless markets like cellular telephony or wireless LANs demand low power as well. This calls for innovative design methodologies at the circuit and component levels to address this rigorous requirement. The third group of papers from the University of British Columbia (UBC), Carleton University, and the University of Calgary addresses some of the circuit problems at the component and technology levels. Chamseddine et al. propose a new structure for an RF switch implemented in a systemon-sapphire (SoS) technology. Danson et al. show how a MEMS technology can be used to improve RF performance, using an LNA and a power amplifier as examples. Sameni et al. introduce a new model for VCO modeling, while Chan et al. present a novel application for parameter conversion using a MOS varactor as a key device.

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Effective CMOS RF design would not be possible without proper electronic design automation (EDA) tools. The last paper of the special issue by Zhu et al. from Lakehead University reviews some circuit simulation techniques used for RF simulations. The special issue would not be possible without the dedicated efforts of many reviewers for which the editors are very grateful. We hope that the collected research papers can help in fulfilling a gap between the two communities of CMOS circuit designers and experts in wireless communication theories. Kris Iniewski Mourad El-Gamal Robert Bogdan Staszewski

Kris Iniewski is an Associate Professor at the Electrical Engineering and Computer Engineering Department, University of Alberta. He is also a President of CMOS Emerging Technologies, Inc., a consulting company in Vancouver. His research interests are in advanced CMOS devices and circuits for ultra-low-power wireless systems, medical imaging, and optical networks. From 1995 to 2003, he was with PMC-Sierra and held various technical and management positions in Research & Development and Strategic Marketing. Prior to joining PMC-Sierra, from 1990 to 1994, he was an Assistant Professor at the University of Toronto’s Electrical Engineering and Computer Engineering Department. He has published over 80 research papers in international journals and conferences. He holds 18 international patents granted in USA, Canada, France, Germany, and Japan. He is a frequent invited speaker and consults for multiple organizations internationally. He received his Ph.D. degree in electronics (with honors) from the Warsaw University of Technology (Warsaw, Poland) in 1988. Together with Carl McCrosky and Dan Minoli he is an author of Data Networks-VLSI and Optical Fibre (Wiley, 2006). He is also an editor of Emerging Wireless Technologies (CRC Press, 2006). Mourad El-Gamal is an Associate Professor of electrical engineering at McGill University, Montreal, Canada, where he holds the William Dawson Scholar Chair. He is also the President of InfiniteChips, Inc., a company that provides integrated circuit solutions for a variety of markets. In 2002 he was the Director then VP Engineering at MEMSCAP in France—a 165-employee public company. He oversaw the business and technical aspects in different sites around the world related to RF-MEMS devices, RFICs, and millimeter-wave passive circuits. He published over 60 technical papers, and one book chapter on lowvoltage 5-GHz RFIC front ends. Dr. El-Gamal served as a Guest Editor for the IEEE Journal of Solid-State Circuits, and is currently an Associate Editor of the IEEE Transactions on Circuits and Systems. He is on the Executive Committee of the IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM), a Member of the Emerging Technologies Committee of the IEEE Custom Integrated Circuits Conference (CICC), and a Member of the Analog Signal Processing Committee of the IEEE Circuits and Systems (CAS)

Society. Earlier, he worked for the French telecommunications company ALCATEL, and for IBM. He regularly serves as consultant for microelectronics companies. He holds one patent and has three patents pending. Robert Bogdan Staszewski received the B.S.E.E. (summa cum laude), M.S.E.E., and Ph.D. degrees from the University of Texas at Dallas in 1991, 1992, and 2002, respectively. From 1991 to 1995, he was with Alcatel Network Systems in Richardson, Tex, working on Sonnet cross-connect systems for fiber optics communications. He joined Texas Instruments in Dallas, Tex, in 1995 where he is currently a Distinguished Member of Technical Staff. Between 1995 and 1999, he has been engaged in advanced CMOS read channel development for hard disk drives. In 1999 he costarted a Digital RF Processor (DRPTM ) Group within Texas Instruments with a mission to invent new digitally intensive approaches to traditional RF functions for integrated radios in deep-submicron CMOS processes. He currently leads the DRP system and design development for transmitters and frequency synthesizers. He has authored and coauthored 60 journal and conference publications and holds 25 issued and 35 pending US patents. His research interests include deep-submicron CMOS architectures and circuits for frequency synthesizers, transmitters, and receivers.

Hindawi Publishing Corporation EURASIP Journal on Wireless Communications and Networking Volume 2006, Article ID 17957, Pages 1–18 DOI 10.1155/WCN/2006/17957

Novel Radio Architectures for UWB, 60 GHz, and Cognitive Wireless Systems Danijela Cabric, Mike S. W. Chen, David A. Sobel, Stanley Wang, Jing Yang, and Robert W. Brodersen Berkeley Wireless Research Center, University of California, Berkeley, CA 94704, USA Received 18 October 2005; Revised 17 January 2006; Accepted 19 January 2006 There are several new radio systems which exploit novel strategies being made possible by the regulatory agencies to increase the availability of spectrum for wireless applications. Three of these that will be discussed are ultra-wideband (UWB), 60 GHz, and cognitive radios. The UWB approach attempts to share the spectrum with higher-priority users by transmitting at power levels that are so low that they do not cause interference. On the other hand, cognitive radios attempt to share spectra by introducing a spectrum sensing function, so that they are able to transmit in unused portions at a given time, place, and frequency. Another approach is to exploit the advances in CMOS technology to operate in frequency bands in the millimeter-wave region. 60 GHz operation is particularly attractive because of the 7 GHz of unlicensed spectrum that has been made available there. In this paper, we present an overview of novel radio architecture design approaches and address challenges dealing with high-frequencies, widebandwidths, and large dynamic-range signals encountered in these future wireless systems. Copyright © 2006 Danijela Cabric et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

1.

INTRODUCTION

The demand for wireless connectivity and crowding of unlicensed spectra has pushed the regulatory agencies to be ever more aggressive in providing new ways to use spectra. In the past, the approach for spectrum allocation was based on specific band assignments designated for a particular service, as illustrated by the Federal Communications Commission’s (FCC) frequency allocation chart. This spectrum chart contains overlapping allocations in most frequency bands and seems to indicate a high degree of spectrum scarcity. While spectrum efficiency of some radio systems is improving (e.g., cell phone and WiFi bands), they are faced with increasing interference that limits network capacity and scalability. On the other hand, some bands are poorly utilized. Measurements taken in downtown Berkeley (Figure 1) reveal a typical utilization of roughly 30% below 3 GHz, and 0.5% in the 3–6 GHz frequency band. In order to promote more flexibility in spectrum sharing, the FCC has provided new opportunities for unlicensed spectrum usage with fewer restrictions on radio parameters. Three new opportunities in spectrum access have thus been introduced: (1) an underlay approach with severe restrictions on transmitted power levels with a requirement to operate over “ultra-” wide bandwidths (UWB); (2) an

opening of 7 GHz of unlicensed spectrum at millimeter-wave frequencies (around 60 GHz) where oxygen absorption limits long-distance interference; (3) an overlay approach based on avoidance of higher-priority users through the use of spectrum sensing (cognitive radios). The potential opening of these new spectra introduces new opportunities for vastly more wireless connectivity. As indicated in Table 1, these three radio system are (or should be) allowed to operate in 500 MHz or wider spectrum. Therefore, the design of highthroughput radios with 100 Mb/s to even 1 Gb/s data rates is achievable at moderate-to-low spectrum efficiencies. The power limitations and wireless channel propagation characteristics for these bands dictate the range capability which extends from 1 m to 10 km, so that a wide variety of communication modes can be supported with these three new wireless radio technologies. This regulatory shift also has major implications on radio architectures since traditional narrowband radio design techniques are not applicable. Spectrum sharing required in UWB and CR over wide bands implies frequency agility and significant dynamic range improvements of radio front-ends. In addition, new radio functions are required which involve high sensitivity sensing and modulation schemes robust to strong interferers and low signal-to-noise regimes. Interference avoidance through operation at microwave frequencies

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Table 1: Potential system-level specifications consistent with FCC regulations and IEEE standards where they exist. Cognitive radios∗ do not have an allocation at this time. Systems

UWB radio (UWB)

60 GHz radio (60 GHz)

Cognitive radio∗ (CR)

Spectrum access Carrier Bandwidth Data rates Spectrum efficiency Range

Underlay [0–1], [3–10] GHz > 500 MHz 100–500 Mb/s ∼ 0.1–1 b/s/Hz 1–10 m

Unlicensed [57–64] GHz > 1 GHz > 1 Gb/s ∼ 1 b/s/Hz ∼ 10 m

Overlay [0–1], [3–10] GHz > 500 MHz ∼ 10–1000 Mb/s ∼ 0.1–10 b/s/Hz 1 m–10 km

architectures, signal processing techniques, and analog circuits. A low-complexity impulse radio architecture, together with its building blocks, will be given as an example of these new opportunities.

Measured power (dB)

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0

1

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5 ×109

Figure 1: Spectrum utilization measurement (0–6 GHz).

introduces challenges in RF circuit implementation to ensure that the eventual solution is cost-effective. In this paper, we present major opportunities and challenges of this new era in CMOS radio design, focusing on the three radio systems outlined in Table 1. Radio architectures which address the unique new requirements of these radios will be discussed including the analog and digital circuit partitioning, and the issues involved in antenna, RF, mixedsignal, and digital circuits. 2.

UWB RADIOS

In 2002, the FCC released the use of ultra-wideband (UWB) transmission in several frequency bands (0–960 MHz, 3.1– 10.6 GHz, and 22–29 GHz) with an effective isotropic radiation power (EIRP) below −41.3 dBm/MHz and requiring operation at larger than 500 MHz signal bandwidth [1]. The large bandwidth enables short-range high-datarate communication and the possibility to perform highresolution positioning. The new challenge for UWB radio implementation is to fully exploit the wideband nature for lower power and a less costly solution than by increasing the efficiency of narrowband techniques such as occurring in the standard 802.11n. A new opportunity using nonsinusoidal carriers, so-called impulse radios, has allowed designers to take a fundamentally new approach to radio

Low-complexity impulse radio architecture

The most discussed application of UWB is for short-range, high-speed, indoor communications. Two competing approaches have been introduced: one utilizing frequencyhopping OFDM and the other employing the impulse radio technique with direct-sequence coding. OFDM signaling strategy is essentially a scaled-up version of 802.11a/g system, which has the benefit of combating multipaths and potential power allocation for optimizing channel capacity. A major challenge of this approach is that the overall complexity is on the order of present 802.11 systems, which means that opportunities for dramatic cost and power reductions are unlikely. For example on the transmitter side, a wideband OFDM radio requires high-speed digital-to-analog converter, upconversion mixers, oscillators, and power amplifier with linearity and peak-to-average ratio (PAR) constraints because of the multicarrier transmission [2]. On the other hand, an impulse radio simply uses a pulser to drive the antenna, and radiates a passband pulse shaped by the response of the wideband antenna and potential bandpass filters, as shown in Figure 2. The most popular modulation schemes using this approach are antipodal signaling or pulse-position modulation which have dramatically reduced linearity requirements at the expense of increased timing sensitivity. The high-level schematic of an impulse radio architecture shown in Figure 2 shows the potential reduction in the complexity on the receiver side. Instead of the conventional heterodyne topology utilizing one or two mixing stages to downconvert the passband signal, the proposed receiver directly subsamples the incoming signal after amplification. This is accomplished by sampling at a rate below the Nyquist rate of the RF signal, but at or above the Nyquist rate of the data itself. The sampled and digitally converted data are processed by an optimized digital matched filter for optimal detection. The proposed system avoids wideband analog processing with increased digital processing, which results in a more efficient solution than conventional UWB implementations which have typically adopted a direct-conversion architecture [3–6] that results in significant increases in power dissipation.

UWB antenna

90 shifts

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Danijela Cabric et al.

Q (a) UWB attenna

Bp

Digital backend

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(b)

Figure 2: Transceiver of (a) one-stage heterodyne for OFDM approach, (b) proposed subsampling impulse radio.

2.2. UWB impulse radio frontend

C1

L1

2.2.1. Circuit modeling methodology for UWB small antennas Ideally, the design of UWB antennas should satisfy several requirements: broad impedance bandwidth, high radiation efficiency, small size, omnidirectional radiation pattern, and broad radiation pattern bandwidth. These properties are generally strong functions of the antenna electrical size, and they are particularly challenging for the 0–1 GHz band, which is particularly interesting because of its good material penetration properties. The ability to design circuits that can provide efficient power transfer into the antenna (a good impedance match) and have an antenna pattern that is waveform omnidirectional is strongly dependent on the antenna size relative to the wavelength over the bandwidth of interest. For antennas that are electrically small, the impedance match is difficult to maintain, but the actual radiation pattern is almost constant over frequency; for antennas operating close to the first resonant frequency, the impedance match is good and the radiation pattern is only a weak function of frequency; however for antennas operating well above the first resonant frequency, while the impedance match is good, the radiation pattern changes rapidly with frequency. UWB antenna design is thus about designing the antenna around the first resonant frequency to achieve simultaneous impedance matching and constant radiation pattern over a wide bandwidth. The state-of-the-art UWB antennas report up to 4 : 1 impedance bandwidth but less than 3 : 1 bandwidth meeting both impedance and radiation pattern requirements [7–10]. Due to the limited impedance matching bandwidth, it is expected that the antenna impedance will deviate from 50 Ω, and will contribute waveform dispersion at both the transmitter and the receiver. How to capture the waveform dispersion, model the antenna impedance, and design the corresponding interface circuitry thus imposes a significant challenge in a UWB front-end design. A circuit modeling methodology that bridges the gap between UWB antenna and circuit design is thus necessary.

+ C2

L2

Rrad

Vrad −

(a)

L2

L1

C1

C2

Rrad

+ Vrad −

(b)

Figure 3: Degenerated Foster canonical forms for (a) electric antennas, and (b) magnetic antennas.

Generally, antennas are linear, passive elements and their input impedances can be represented by Foster canonical forms [11]. For UWB antennas of interest, one operates the antennas in the regime that their radiation pattern is constant with frequency, that is, below the second resonant frequency, so the Foster canonical forms can be degenerated to that shown in Figure 3. Figure 3(a) models electric antennas like dipoles and monopoles, and Figure 3(b) models magnetic antennas like loop antennas. The circuit models can be thought of as a load resistor Rrad with an LC bandpass filter in the front.

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EURASIP Journal on Wireless Communications and Networking 1.5 1 1 Amplitude (V)

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Figure 4: Time-domain waveforms of the 6 cm dipole antenna: (a) source voltage waveform with −10 dB bandwidth DC-2 GHz; (b) normalized Vrad from SPICE and Erad (θ = 90o ) from XFDTD.

The advantage of being waveform-omnidirectional, for which the waveforms of the radiated E-fields propagating in all directions are the same and thus differ only in magnitude, allows a simple antenna model to be built, which can be simulated on highly efficient circuit simulator instead of full electromagnetic simulation. An example is given on modeling a dipole antenna. By fitting the input impedance of the circuit in Figure 3(a) to that of a 6 cm dipole antenna from FDTD simulation [12] using an optimization tool, we obtain C1 = 0.68 pF, L1 = 1.24 nH, C2 = 0.64 pF, L2 = 4.91 nH, and Rrad = 187 Ω. The resulting impedances from SPICE and FDTD match very well up to 5 GHz, which is almost twice the first resonant frequency. A 0.6-nanosecond-wide Gaussian voltage waveform is then sent into the antenna through a 50 Ω resistor (Figure 4(a)), and the voltage waveform Vrad and the far-zone E-field at θ = 90◦ at 1 m away from the antenna are derived in SPICE and FDTD, respectively. After scaling and time shifting, Figure 4(b) shows that the two normalized waveforms match well indicating the effectiveness of the model. 2.2.2. Design of UWB pulse generator In the past, UWB pulses were generated by circuits using exotic devices such as GaAs photoconductive switches, steprecovery diodes (SRD), tunnel diodes, or avalanche transistors. With the increased performance of scaled CMOS device size keeping scaling down and the device fT enhanced, it is now possible to implement subnanosecond pulse generators using existing CMOS technologies and integrate it with other circuit blocks on a chip. Ideally, after the antenna transfer function is derived as discussed in the previous section, a waveform meeting the FCC spectral mask can be generated by driving the antenna

with the deconvolved waveform. The traditional way of doing this is to implement a linear power amplifier preceded by a high-speed digital-to-analog converter (DAC) with high resolution. However, high-performance DACs require significant power, and since the UWB transmitter is regulated to sub-mW power levels, it will lead to very poor power efficiency. An alternative is to use simple circuitry generating square pulses (similar to a 1-bit DAC) and filter them before the antenna. Figure 5 shows the proposed 2-PAM/PPM UWB transmitter that generates pulses below 960 MHz. A four-transistor balanced H-bridge driver is used to implement the voltage source. An off-chip filter/matching network helps to shape the waveform before it reaches the antenna. The H-bridge is driven by a predriver, which is further triggered by a timing circuitry. If a digital bit “1” is meant to be sent, transistors MP2 and MN1 are first turned on. A current will flow from Vdd through MP2 to the antenna, and through MN1 to ground. V1 is raised immediately to Vdd, and V2 is pulled down to 0. The differential output voltage of the Hbridge (V out = V1 − V2 ) is thus a rising step from 0 to Vdd. In the second half of the period, transistor MP2 is turned off and MN2 is turned on. V1 then drops immediately to 0. The differential output voltage is thus a falling step from Vdd to 0. A rectangular pulse with magnitude equal to Vdd and pulse width equal to the interval between the switched-on times of MP2 and MN2 is formed. All the transistors are turned off by the end of the period. In contrast, if a digital bit “0” is meant to be transmitted, transistors MP1 and MN2 are first turned on, followed by the turn on of MN1 . A negative differential rectangular pulse can then be formed. 2.2.3. Design of UWB low-noise amplifier Since the LNA is the circuit block that connects to the receiving antenna, its impedance will affect the waveform

Danijela Cabric et al.

5 H-bridge Filter

Data Clk

Timing circuit

Predriver

Antenna

M p1 M p2 V1

+ Vrad

V2 MN1 MN2

−

Figure 5: A CMOS pulse generator driving an electric antenna.

Vbp

Vin+

VinVout-

Vout+

Vbf Vbn

Figure 6: The < 1 GHz shunt-feedback/common-gate hybrid LNA.

dispersion. Also, if off-chip filters are to be used for band limiting, 50-ohm matching is desirable. Since the in-band interference of UWB systems is much greater than the ambient noise, noise figure requirements can be relaxed to achieve lower power. A sub-mW UWB CMOS LNA has been proposed for the M independent array coefficients is sufficient to obtain the estimation of spatial distribution. After identifying the frequency-spatial location of M strongest primary users through least-square estimation on these K measurements, array coefficients are set to attenuate their directions of arrivals. Figure 21 shows the outlined algorithm performance for the case of two strong primary users whose power is 30– 40 dB larger than average power in other frequency bands. After the optimal coefficients are applied, dynamic range reduces by approximately 22 dB (saving 3-4 bits in A/D converter) using a 4-element antenna array. Therefore, spatial filtering techniques could relax requirements for the implementation of RF wideband sensing frontend. 4.2. Signal processing for spectrum sensing After reliable reception and sampling of a wideband signal, digital signal processing techniques should be utilized to further increase radio sensitivity by processing gain, and for primary user identification based on knowledge of the signal characteristics. The key issue in spectrum sensing is the detection of weak signals in noise with a very small probability of miss detection. 4.2.1. Matched filter and energy detector A matched filter is the optimal detector in a sense that it can also demodulate signals due to coherent signal processing.

The processing gain is linearly proportional to the number of samples N: SNRout = N · SNRin . This gain is achievable under perfect frequency/timing synchronization and channel estimation required for coherent reception, but in lowSNR regimes heavily relies on the overhead of training pilot sequence. Therefore, a matched filter implementation complexity is prohibitively large since the cognitive radio would almost have to have a receiver for every primary user’s system. An energy detector is the suboptimal detector due to noncoherent signal processing, which only integrates squared samples. The processing gain is SNRout = N · SNR2in which in case of a very small SNRin becomes significantly inferior to the matched filter due to quadratic scaling. The signal is detected by comparing the output of the energy detector with a threshold dependent on the estimated noise power. As a result, a small estimation error in the noise power causes significant performance loss of the energy detector. At the low SNRs of interest, the energy detector completely fails in the detection of weak signals. Even though the implementation simplicity (Figure 22) of the energy detector makes it a favorable candidate, the requirement to estimate the noise power of the actual RF transceiver within a fraction of a dB would be difficult to achieve. In practice, it would require a calibration of noise figure and gains of a wideband RF frontend across the whole frequency range. In addition, an energy detector does not differentiate between modulated signals, noise, and interference. Since, it cannot recognize the interference, it cannot benefit from adaptive signal processing for cancelling the interferer. Furthermore, spectrum policy for using the band is constrained only to primary users, so a cognitive user should treat noise and other secondary users differently. Lastly, an energy detector does not work for spread-spectrum signals: directsequence and frequency-hopping signals, for which more sophisticated signal processing algorithms need to be devised.

Danijela Cabric et al.

15 0 −30

30 40

FFT = 128 bins 4 antennas, 8 sweeps Avg. SNR = 10 dB per subcarrier 2 strong PUs α1 = 45◦ , P1 = 40 dB, k = 100 bin α2 = 70◦ , P1 = 30 dB, k = 50 bin

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Figure 21: An example of dynamic range reduction using antenna arrays: (a) simulation parameters; (b) optimal array response; (c) large dynamic-range signal; (d) spatially filtered signal.

Threshold

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Energy detect

Figure 22: Implementation of an energy detector using Welch periodogram averaging.

4.2.2. Cyclostationary feature detector Cyclostationary feature detectors have the ability to extract distinct features of modulated signals such as sine-wave carrier, symbol rate, and modulation type. These features are detected by analyzing a spectral correlation function that is a two-dimensional transform, in contrast with powerspectrum density being one-dimensional transform [26]. The main advantage of spectral correlation function is that it discriminates the noise energy from modulated signal energy. This property is a result of the fact that noise is a widesense stationary signal with no correlation, while modulated signals are cyclostationary with spectral correlation due to embedded redundancy of signal periodicities. Therefore, a

cyclostationary feature detector is a better alternative than energy detector due to its robustness to unknown noise variance. Implementation of a spectrum correlation function for cyclostationary feature detection is depicted in Figure 23. It can be designed as augmentation of the energy detector from Figure 22 with a single correlator block. Detected features are number of signals, their modulation types, symbol rates and presence of interferers. Figure 24 illustrates the advantages of cyclostationary detection versus energy detection for continuous phase 4-FSK modulated signals. Distinct pattern of 4-FSK modulation in a spectral correlation function is preserved even in low SNR = −20 dB while energy detector is limited by the large noise. Its implementation complexity is increased by N 2 complex multiplications to perform the cross-correlation of the N-point FFT outputs, while the energy detector has the complexity of an N-point FFT. 5.

CONCLUSION

The demand for wireless connectivity has pushed the regulatory agencies to be ever more aggressive in providing new ways to use spectra. The radio systems that are made possible by these new opportunities allow for new optimization at the architectural, circuit, and algorithm levels. Three of these

16

EURASIP Journal on Wireless Communications and Networking

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new radio systems were discussed with some examples of solutions to the new challenges that are being posed. There are clearly further opportunities in all of these new approaches for designers to express their creativity, so it is an exciting time to be a radio designer and an architect. ACKNOWLEDGEMENT This work was supported by an ARO Grant no. 065861, DARPA TEAM Project, MARCO Contract CMU 2001-CT888, and the industrial members of BWRC.

[3]

[4]

[5]

REFERENCES [6] [1] FCC, First Report and Order, FCC 02-48, February 2002. [2] A. Aggarwal, D. Leenaerts, R. van de Beek, et al., “A low power implementation for the transmit path of a UWB transceiver,”

in Proceedings of IEEE Custom Integrated Circuits Conference (CICC ’05), San Jose, Calif, USA, September 2005. J. Bergervoet, K. Harish, G. van der Weide, et al., “An interference robust receive chain for UWB radio in SiGe BiCMOS,” in Proceedings of IEEE International Solid-State Circuits Conference (ISSCC ’05), San Francisco, Calif, USA, February 2005. A. Ismail and A. Abidi, “A 3.1 to 8.2GHz direct conversion receiver for MB-OFDM UWB communications,” in Proceedings of IEEE International Solid-State Circuits Conference (ISSCC ’05), San Francisco, Calif, USA, February 2005. S. Lida, K. Tanaka, H. Suzuki, et al., “A 3.1 to 5GHz CMOS DSSS UWB transceiver for WPANs,” in Proceedings of IEEE International Solid-State Circuits Conference (ISSCC ’05), San Francisco, Calif, USA, February 2005. B. Razavi, T. Aytur, F.-R. Yang, et al., “A 0.13 /spl μ/m CMOS UWB transceiver,” in Proceedings of IEEE International SolidState Circuits Conference (ISSCC ’05), vol. 1, San Francisco, Calif, USA, February 2005.

Danijela Cabric et al. [7] S.-Y. Suh, W. Stutzman, W. Davis, A. Waltho, and J. Schiffer, “A novel CPW-fed disc antenna,” in Proceedings of IEEE APS/URSI Symposium Digest, vol. 3, pp. 2919–2922, Monterey, Calif, USA, June 2004. [8] T. G. Ma and S. K. Jeng, “Planar miniature tapered-slotfed annular slot antennas for ultra-wideband radios,” IEEE Transactions on Antennas Propagation, vol. 53, no. 3, pp. 1194– 1202, 2005. [9] H. G. Schantz, “Bottom fed planar elliptical UWB antennas,” in Proceedings of IEEE Conference on Ultra Wideband Systems and Technologies (UWBST ’03), pp. 219–223, Reston, Va, USA, November 2003. [10] S. Wang, A. M. Niknejad, and R. W. Brodersen, “Modeling omnidirectional small antennas for UWB applications,” in Proceedings of IEEE AP-S/URSI Symposium Digest, vol. 2, pp. 1295–1298, Monterey, Calif, USA, June 2004. [11] D. Cheng, Field and Wave Electromagnetics, Addison Wesley, Reading, Mass, USA, 1989. [12] C. Balanis, Antenna Theory: Analysis and Design, John Wiley & Sons, New York, NY, USA, 2nd edition, 1997. [13] S. Wang, A. M. Niknejad, and R. W. Brodersen, “A submW 960-MHz Ultra-wideband CMOS LNA,” in Proceedings of IEEE Radio Frequency Integrated Circuits Symposium (RFIC ’05), Long Beach, Calif, USA, June 2005. [14] R. G. Vaughan, N. L. Scott, and D. R. White, “The theory of bandpass sampling,” IEEE Transactions on Signal Processing, vol. 39, no. 9, pp. 1973–1984, 1991. [15] K. Ohata, K. Maruhashi, M. Ito, et al., “Wireless 1.25Gb/s transceiver module at 60GHz-band,” in Proceedings of IEEE International Solid-State Circuits Conference (ISSCC ’02), San Francisco, Calif, USA, February 2002. [16] C. H. Doan, S. Emami, A. M. Niknejad, and R. W. Brodersen, “Millimeter-wave CMOS design,” IEEE Journal of Solid-States Circuits, vol. 40, no. 1, pp. 144–155, 2005. [17] M. R. Williamson, G. E. Athanasiadou, and A. R. Nix, “Investigating the effects of antenna directivity on wireless indoor communication at 60GHz,” in Proceedings of 8th IEEE International Symposium on Personal, Indoor and Mobile Radio Communications (PIMRC ’97), Helsinki, Finland, September 1997. [18] C. Rapp, “Effects of HPA-nonlinearity on a 4-DPSK/OFDMsignal for a digital sound broadcasting system,” in Proceedings of the 2nd European Conference on Satellite Communications, pp. 179–184, Liege, Belgium, October 1991. [19] M. Tiebout, H.-D. Wohlmuth, and W. Simburger, “1 V 51GHz fully-integrated VCO in 0.12 μm CMOS,” in Proceedings of IEEE International Solid-State Circuits Conference Dig. Tech. (ISSCC ’02), vol. 1, pp. 300–468, San Francisco, Calif, USA, February 2002. [20] P. F. M. Smulders and L. M. Correia, “Characterization of propagation in 60 GHz radio channels,” Electronics & Communication Engineering Journal, vol. 9, no. 2, pp. 73–80, 1997. [21] X. Jiang, Z. Wang, and M. F. Chang, “A 2Gs/s 6b ADC in 0.18um CMOS,” in Proceedings of IEEE International SolidState Circuits Conference Dig. Tech. Papers (ISSCC ’03), pp. 322–323, San Francisco, Calif, USA, February 2003. [22] FCC, ET Docket no. 03-322. Notice of Proposed Rule Making and Order, December 2003. [23] D. Cabric, S. M. Mishra, and R. W. Brodersen, “Implementation issues in spectrum sensing for cognitive radios,” in Proceedings of 38th Annual Asilomar Conference on Signals, Systems and Computers, Pacific Grove, Calif, USA, November 2004.

17 [24] R. H. Walden, “Analog-to-digital converters survey and analysis,” IEEE Journal on Selected Areas in Communications, vol. 17, no. 4, pp. 539–550, 1999. [25] D. Cabric and R. W. Brodersen, “Physical layer design issues unique to cognitive radio systems,” in Proceedings of 16th IEEE International Symposium on Personal, Indoor and Mobile Radio Communications (PIMRC ’05), Berlin, Germany, September 2005. [26] W. A. Gardner, “Signal interception: a unifying theoretical framework for feature detection,” IEEE Transactions on Communications, vol. 36, no. 8, pp. 897–906, 1988. Danijela Cabric received the Dipl. Ing. degree from the University of Belgrade, Yugoslavia, in 1998, and the M.S. degree in electrical engineering from the University of California, Los Angeles, in 2001. She is currently working toward the Ph.D. degree in electrical engineering at the University of California, Berkeley, under Professor Brodersen, where she is a member of the Berkeley Wireless Research Center. In 2001, she was with Innovics Wireless, Los Angeles, where she worked as a Senior System Design Engineer on the algorithm development for a dual-antenna WCDMA mobile receiver. In 2004, she held internship position with Intel Corporation, Santa Clara, where she worked on the system design of a cognitive radio in the UHF TV band. Her current research interests include cognitive radio physical layer design and multiple-antenna system implementation. Mike S. W. Chen received the B.S. degree from National Taiwan University, Taipei, Taiwan, in 1998, and the M.S. degree from University of California, Berkeley (UC Berkeley) in 2002, both in electrical engineering. He is currently working towards the Ph.D. degree at UC Berkeley, where he is a member of Berkeley Wireless Research Center. His current research interests include low-power and high-speed mixedsignal circuits, Ultra-wideband system design, digital baseband and digital ASIC implementations. He achieved an honourable mention in Asian Pacific Mathematics Olympiad, 1994. He was the recipient of UC Regents Fellowship at Berkeley in 2000. David A. Sobel received an A.B. degree in engineering sciences from Harvard University, Cambridge, Mass, in 1997. He received an M.S. degree in electrical engineering from the University of California, Berkeley, in 2000. He is currently working towards a Ph.D. degree at the University of California, Berkeley, where he is a member of the Berkeley Wireless Research Center. His doctoral research focuses on the design of baseband analog integrated circuits for high-speed wireless communications. Since 2000, he has been a Staff Engineer at Broadcom Corporation, San Jose, Calif, where he has been involved in the design of analog integrated circuits for communications applications. He is the author of six patents.

18 Stanley Wang received the B.S. and M.S. degrees from National Taiwan University, Taiwan, in 1998 and 2000, respectively, and Ph.D. degree from the University of California, Berkeley, in 2005, all in electrical engineering. His current research is focused on CMOS RFIC and UWB antenna design. He was awarded the Micro Fellowship 20002001 and the Intel Robert Noyce Fellowship 2003–2005. He was the recipient of the Best Student Paper Award at the IEEE Radio Frequency Integrated Circuits Symposium, 2005. Jing Yang received her B.S. degree in automation from Tsinghua University, China, in 2001, and the M.S. degree in electrical engineering from the University of California, Berkeley, in 2004. She is currently working towards the Ph.D. degree at the University of California, Berkeley under Professor Brodersen. Her research interests include architectures and implementation of interference cancellation for the future wideband radios, and front-end design for cognitive radio systems. Robert W. Brodersen received the B.S. degrees in electrical engineering and mathematics from the California State Polytechnic University, Pomona, Calif, in 1966, the Engineering and Masters of Science degrees from the Massachusetts Institute of Technology (MIT), Cambridge, in 1968, and the Ph.D. degree in engineering from MIT in 1972. He received the award Honor Doctor of Technology (Technologie Doctor Honoris Causa) from the Lund University, Sweden, 1999. From 1972 till 1976, he was a member of the Technical Staff, Central Research Laboratory, Texas Instruments, Dallas. He joined the faculty at the University of California, Berkeley in 1976 where he is currently the John R. Whinnery Distinguished Professor in the Department of Electrical Engineering and Computer Science. He is also the coscientific Director of the Berkeley Wireless Research Center (BWRC) where his research focus is new applications of integrated circuits as applied to personal communications systems with emphasis on wireless communications, low-power design, and the CAD tools necessary to support these activities.

EURASIP Journal on Wireless Communications and Networking

Hindawi Publishing Corporation EURASIP Journal on Wireless Communications and Networking Volume 2006, Article ID 43917, Pages 1–8 DOI 10.1155/WCN/2006/43917

Transceiver Design for Multiband OFDM UWB D. M. W. Leenaerts Philips Research, 5656 AE, Eindhoven, The Netherlands Received 14 October 2005; Accepted 9 January 2006 Ultra-wideband (UWB) is an emerging broadband wireless technology enabling data rates up to 480 Mbps. This paper provides an overview of recent design approaches for several circuit functions that are required for the implementation of multiband OFDM UWB transceivers. A number of transceiver and synthesizer architectures that have been proposed in literature will be reviewed. Although the technology focus will be on CMOS, also some design techniques implemented in BiCMOS technologies will be presented. Copyright © 2006 D. M. W. Leenaerts. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

1.

INTRODUCTION

Short-range communication systems (so-called wireless personal area network (WPAN) systems) with ranges of up to 10 m are becoming popular in replacing cables and in enabling new consumer applications. Examples such as Bluetooth and ZigBee, which operate in the 2.4 GHz ISM band, have however a limited data rate, typically about 1 Mbps, which is insufficient for many applications like fast transfer of large files (e.g., wireless USB) and high-quality video streaming. In order to increase the data rate to several hundreds of Mbps, a higher bandwidth is preferred over a larger SNR. This became possible at the moment the FCC released spectrum for UWB in the US spanning from 3.1 to 10.6 GHz with an average transmit power level of only −41.3 dBm/MHz [1, 2]. Several proposals have since then been presented to realize a short-range high data rate communication link. At present, both direct-sequence impulse communication and multiband OFDM UWB systems are under consideration as a standard. The standard proposed by the multiband OFDM alliance (MBOA) is based on subdivision of the large available bandwidth in subbands of 528 MHz (see Figure 1) [2]. The data is QPSK-OFDM modulated on 128 subcarriers. Various modes are defined with data rates up to 480 Mbps. In the mandatory mode of operation (Mode 1), a frequency-hopping scheme in the three lower bands is implemented. Using only the three lower bands allows the use of a bandpass prefilter to reduce the interferer level of the 5 GHz ISM band. After each symbol period of 312.5 ns, a 9.5 ns guard time is available for hopping to the next band.

This paper intends to give an overview of the current status in multiband OFDM-based UWB systems. Section 2 will discuss the most important system specifications. Section 3 will highlight the progress made on receiver building blocks and Section 4 will focus on transmitter building blocks. Various design aspects on the synthesizer will be discussed in Section 5. Several (fully) integrated transceivers will be discussed in Section 6 and finally some concluding remarks are stated in Section 7. Although the emphasis of this paper will be on progress that is made on implementations in CMOS technology, some BiCMOS transceivers and circuits will be discussed as well. 2.

UWB TRANSCEIVER SPECIFICATIONS

UWB receiver design is challenging, as it simultaneously requires a low noise density in a large bandwidth and a high linearity since large interferers can be present close to the used frequency band. An interferer scenario is required to determine the amount of filtering needed. On the transmit side, the challenge is in achieving a tunable, flat gain response over a 1.584 GHz bandwidth. Probably the most challenging block is the synthesizer due to the fast-hopping requirement. 2.1.

Receiver requirements

For the receiver, the noise figure (NF) can be obtained from the system NFsystem according to NF = NFsystem − ILprefilter with ILprefilter the insertion loss of the prefilter. For a threeband system, the MBOA proposal assumes an NFsystem equal to 6 dB. For the 55 Mbps mode, this reflects a sensitivity level

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EURASIP Journal on Wireless Communications and Networking Band group #1

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of −83.5 dBm with an SNR of −5 dB. For the highest data rate of 480 Mbps, the SNR is 6 dB and therefore the sensitivity level is increased to −72 dB. To achieve graceful coexistence with other wireless technologies such as 802.11 WLAN and Bluetooth, an interferer robust receiver is needed. The MBOA interference scenario recommendation is depicted in Figure 2, indicating that even when a realistic 20 dB of prefiltering is taken into account, linearity requirements are severe. Most UWB systems target an input IP2 (iIP2) requirement above +20 dBm and an iIP3 requirement in the order of −9 dBm. Due to the strong interferers, there are severe filter requirements at IF as well. Consider the case where the closest 802.11a interferer is located only 398 MHz away from the edge of subband #3 centered at 4.488 GHz (5.15 GHz − 4.752 GHz) at a distance of 0.2 m while the wanted UWB signal is transmitted from 10 m distance. In such a case the filter has to provide more than 35 dB of attenuation relative to DC at 662 MHz offset. In a similar way, for the upper band of 802.11a an attenuation of 46 dB is required at an offset of 1.3 GHz. 2.2. Transmitter requirements A key requirement for a UWB transmitter is that the spectral density limit of −41.3 dBm/MHz must be met. Based on this emission mask and the frequency hopping specification, the maximum transmit power can be calculated as −9.5 dBm. Assuming a power loss of about 2.5 dB between antenna and

PA, the power that needs to be generated is −7.0 dBm. Study on the effect of nonlinearity on OFDM signals indicates that a back-off of 2–4 dB ensures acceptable degradation [3]. 2.3.

Synthesizer requirements

As the radio has to cover at least the lower three bands as defined in the MBOA and since most likely a zero-IF architecture is used, the synthesizer needs to provide quadrature signals at the center frequencies of the bands at 3432 MHz, 3960 MHz, and 4488 MHz. The I/Q mismatch must be lower than −30 dBc. In the MBOA proposal, frequency hopping between two subbands occurs once every symbol period of 312.5 ns. This period contains a 60.6 ns suffix, which is followed by a 9.5 ns guard interval in which the frequency hopping should be accomplished. The demands on the purity of the generated carriers are also stringent due to the presence of strong interferer signals. All spurious tones in the 5 GHz range must be below −50 dBc to avoid down-conversion of strong out-of-band WLAN interferers into the wanted bands. For the same reason, the spurious tones in the 2 GHz range should be below −45 dBc to allow co-existence with the systems operating in the 2.4 GHz ISM band, such as 802.11 b/g and Bluetooth. Finally, to ensure that the system SNR will not degrade by more than 0.1 dB due to intercarrier modulation, the overall integrated phase noise should not exceed 3.5 degrees rms. This can be recalculated to a phase noise requirement of −100 dBc/Hz at 1 MHz offset from the carrier.

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3.

RF RECEIVER BUILDING BLOCKS

Vcc Tr

In addition to the receiver requirements, the low-noise amplifier (LNA) must provide broadband input matching and a broadband transfer. Several design options have been proposed in literature. One possibility is to use a bandpass filter at the input in combination with an inductively degenerated (cascode) stage. In this way the reactive part of the input impedance will be cancelled over a wide frequency band [4, 5]. In Figure 3(a), L1 together with C1 form the shunt branch of the filter, the series branch is formed by L2 together with the baseemitter capacitance [4]. Implemented in a 0.18 µm SiGe BiCMOS process, the LNA achieves an NF below 3 dB and an insertion gain above 20 dB. Distributed amplifiers also achieve wideband behavior. Where in mm-wave design coplanar wave guides or striplines are used to implement the transmission lines, silicon implementations use integrated inductors and capacitors as the lumped element replacement circuits for the transmission line. An example is shown in Figure 3(b), where a two-stage distributed amplifier is depicted. Although the resistive part of the inductors causes an increase in the NF, practical NF values around 3 dB are still achievable in 0.18 µm CMOS [6, 7], similar to those achieved in SiGe BiCMOS technologies [8]. An alternative CMOS LNA topology is presented in [9]. Here a common-gate input stage is loaded with three switched cascode devices with tanks resonating at the center frequency of each of the three bands. Note that the load switching must occur with the same speed as the hopping across the bands, that is, 9.5 ns. Noise figures between 5–7 dB and gains above 20 dB can be obtained. Current feedback by means of a feedback resistor is also a quite commonly used method to broaden the bandwidth of the input match. In [10] a cascode topology including resistive feedback and a tuned load achieves an NF of 4 dB and a gain of 16 dB in a 0.18 µm CMOS process. Current feedback together with voltage feedback using an integrated transformer is demonstrated in [11]. This LNA (see Figure 4)

IF

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consists of a cascode input stage (Q1 and Q2), followed by a voltage buffer (Q3 and Q4) known as a white emitter follower. There is voltage feedback by means of a transformer, formed by merging the collector coil and emitter degeneration coil of the input stage. In addition, there is current feedback formed by R1 and C1. This compound feedback mechanism gives high linearity, and also allows for matching of the input impedance to 50 Ω over the lower three bands, without the need for additional external matching components. Due to the channel width of 528 MHz, most receivers apply a zero-IF architecture to relax the bandwidth requirements for the baseband filters and converters. In such an architecture, the LNA is in most cases directly followed by a (Gilbert) down-mixer. In Figure 4, the subsequent mixer contains a combined common-emitter/common-base lowerstage, which is a well-known active balun structure [12]. It is highly degenerated by emitter resistors to obtain the required linearity. A fully balanced eight-transistor switching core has been used, which creates both the I and Q baseband signals. Noise caused by cross-conduction is reduced to a minimum by appropriate shaping of the LO drive signals. These signals should ideally be sinusoidal signals, but as they are the

4

EURASIP Journal on Wireless Communications and Networking Vdd R1 M3 From upconverter Vbias

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output of frequency dividers, they also contain higher-order harmonics. A mixer with a variable gain range is demonstrated in [3, 9]. Here, the load resistor is decomposed into binary weighted segments so as to create dB steps in the gain. Implemented in 0.13 µm CMOS, a 30 dB gain is obtained over a large output bandwidth. High-order filtering at IF/baseband is needed to achieve sufficient attenuation. The large bandwidth in combination with high linearity involves a careful distribution of gain, filtering, and noise. In [11], the baseband filter/VGA has been implemented as a fifth-order Chebyshev-like filter. The gain can be varied between 16 dB and 46 dB with 6 dB steps, and the bandwidth can be tuned in a range of 232 MHz to 254 MHz. At 662 MHz offset an attenuation of −57 dBr has been achieved. A fourth-order Sallen-and-Key filter has been used in [9], while in [13] a fifth-order elliptic filter has been used. In the latter case, the on-chip filter is a passive LC filter and, therefore, it is perfectly linear. 4.

RF TRANSMITTER BUILDING BLOCKS

A crucial aspect of a UWB transmitter is the need of power control to ensure that the transmitted level does not exceed the −41.3 dBm/MHz limit (−14 dBm across 528 MHz). Furthermore, as with WLAN systems, RF impairments (e.g., I/Q mismatch, phase noise, carrier feed-through) must be kept to a minimum. The RF power amplifier (PA) is in most cases based on an inductively loaded (cascode) transistor. An example is shown in Figure 5, where transistors M1 to M3 are used to implement a differential to single-ended structure [9]. Transistor M4 delivers an output level of −10 dBm. A straightforward approach has been used in [14], resulting in a −7 dBm output power level. By varying the bias, the gain of the amplifier can be varied with 6 dB. Again, also the distributed amplifier has been proposed. In [15] a four-stage amplifier has been implemented in a

0.13 µm CMOS process, resulting in a compression point of +3.5 dBm. In this case the transmission lines are implemented as micro-striplines. Where in [9] an up-conversion circuit has been used based on resistively degenerated passive mixers along with a current feedback amplifier, two single-side-band Gilbert mixers have been used in [14]. The needed voltage-tocurrent converter as under stage for the Gilbert mixer core also implements a gain variation mechanism. 5.

FAST-HOPPING SYNTHESIZER

A particularly challenging building block of the UWB receiver is the frequency synthesizer. A classical integer-N PLL with programmable loop divider ratio is unable to perform hopping within 9.5 ns, because such a PLL would require a loop bandwidth in the order of at least several hundreds of MHz and a reference frequency of several GHz. The high reference frequency contrasts the frequency resolution of 528 MHz. The high loop bandwidth, apart from being impractical, is in conflict with the phase noise demand [17]. The same argument holds for a fractional-N PLL synthesizer, where the required high loop bandwidth is also hard to combine with the stringent spurious tone demands. A straightforward frequency synthesizer architecture would be to use three separate PLLs (each generating one of the three required carrier frequencies) in combination with an output multiplexer. This is only practical in those cases where RC ring oscillators can fulfill the requirements. Three LC-oscillators-based PLLs will raise issues with respect to frequency pulling and occupation of die area.The option of using ring oscillators has been used in [9] for a three-band UWB system in a 0.13 µm CMOS process, where each PLL consumes 15 mW from a 1.5 V supply voltage. Most other proposed synthesizer concepts are based on frequency translation, where two frequencies can be added or subtracted by means of a single-sideband (SSB) mixer

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Figure 7: Measured spectral output of the synthesizer in [16] when generating the LO for band #3.

(Figure 6). Synthesizers using this method are also known as multitone generators. The problem of SSB mixing lies in the inherently generated spurious tones, for example, due to nonlinear behavior of the mixer. In this scheme the third harmonic of the 528 MHz signal (at 1584 MHz) is particularly troublesome because, after mixing with 3960 MHz, this harmonic will cause a spur at either 3960 + 1584 MHz = 5544 MHz or at 3960 − 1584 MHz = 2376 MHz. Both spurs are close to possible strong interferer signals (5 GHz and 2.4 GHz ISM bands, resp.) and this may result in UWB signal corruption. Because the 528 MHz signal is the output of a static divide-bytwo circuit in the implementation of Figure 6, its harmonic content will inevitably be strong. Due to the use of quadrature signals, the third harmonic of +528 MHz is located at −1584 MHz. In [16] an integrated notch filter at the divideby-two output (Figure 5) was used to place a notch at this

frequency. In this way, all spurious tones in the 5 GHz band are below −50 dBc, as can be seen from Figure 7. The fully integrated synthesizer consumes 73 mW from a 2.7 V supply and achieves frequency hopping within 1 ns. To eliminate the need for two PLLs, the 3960 MHz signal needs to be divided by 7.5 to derive a 528 MHz signal. The challenge lies in the design of this divider, especially because of the need for quadrature signals with a 50% duty cycle. In [18] this is accomplished by two modified versions of the Miller divider, one realizing ÷3 and the other ÷2.5. The regenerative loop naturally leads to quadrature outputs and 50% duty cycle. Realized in 0.18 µm CMOS, the image suppression of the divider is −20 dBc while consuming 18 mW from a 1.8 V supply. One other possibility is demonstrated in [19]. Division by 7.5 has been realized using a frequency divider by 1.5 and a subsequent divider by 5 with postprocessing to make

6

EURASIP Journal on Wireless Communications and Networking 7920 MHz VCO REF

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Notch-filter

Figure 8: Single PLL, single SSB mixer synthesizer implementation.

clean quadrature signals (Figure 8). The single PLL, single SSB mixer concept consumes 52 mW from a 2.7 V supply. Again due to additional filtering, out-of-band spurious tones are below −50 dBc. The integrated phase noise is below 2 degrees rms and the measured hopping speed is well below the required 9.5 ns. In literature several proposals have been published in case the higher frequency bands also must be covered. A sevenband synthesizer based on two PLLs and one inductively loaded SSB mixer has been published in [20]. Fabricated in a 0.18 µm CMOS technology, it achieves a sideband rejection of 37 dB. Covering the same bands can also be achieved using a 16 GHz VCO, 2 SSB mixers, and only divide-by-two blocks [13]. A 12-band architecture based on three PLLs and two SSB mixers has been proposed in [3]. Multiplexing and routing of all RF signals will be challenging in this concept. 6.

RF TRANSCEIVERS FOR MB-OFDM UWB

As said, due to the wide channel bandwidth, the receiver and transmitter signal paths of UWB systems naturally employ direct conversion, that is, zero-IF. Such a direct conversion 3-band OFDM UWB transceiver has been demonstrated in [9]. The receiver consists of an LNA, quadrature mixers, a fourth-order Sallen-and-Key filter, and a first-order lowpass stage. The LO frequencies are synthesized using three independent PLLs using a 66 MHz reference frequency. This allows a wide PLL loop bandwidth to suppress VCO phase noise. The transmitter uses the inductively loaded PA output stage of Figure 5. It is important to note that the LNA and PA share the same pin connected to the antenna. Designed in a 0.13 µm CMOS technology, this transceiver provides a total gain in the range of 69 to 73 dB and an NF in the range of 5.5 to 8.4 dB across the three bands. The circuit consumes 105 mW from a 1.5 V supply. A direct conversion architecture for seven-band OFDM UWB has been proposed in [13]. The seven carrier frequencies are generated from a single 16 GHz VCO (see Figure 9). The circuit has been fabricated in a 0.18 µm SiGe BiCMOS process and achieves an NF of 3.3–4.1 dB and a conversion gain of 52 dB. The current consumption is 88 mA from a 2.7 V supply. A fully integrated receiver front end has been integrated in a SiGe BiCMOS technology with an NPN- fT of 70 GHz

/32 PLL QVCO 16 GHz

RFin

Frequency synthesizer

WB LNA

Filter

VGA

BB-I

Filter

VGA

BB-Q

Figure 9: Receiver architecture used in [13]. The PLL is implemented off-chip.

[21]. The block diagram and chip micrograph are shown in Figure 10. The chip with a total area of 4 mm2 has been packaged in an HVQFN package and mounted on an FR4 board. Digital control blocks for tuning the VCOs and the IF filter as well as a bandgap unit have also been implemented. The measured performance is provided in Table 1 [21], indicating that low noise figures can be achieved for complete receivers. The transmit chain is published in [14] and features wideband elliptic baseband filters, a VGA with dynamic range of 12 dB, an up-conversion mixer, and an RF output stage with a power of −7 dBm. The current consumption is 43 mA at 2.7 V for the complete transmit path. Finally, some interesting studies on low-power UWB transceiver architectures have been presented in [22, 23]. The architectures are based on the use of distributed design approaches in the LNA and down-mixer circuits. 7.

CONCLUDING REMARKS

Several circuit design techniques for multiband UWB have been discussed. Challenging design aspects in UWB are the combination of wideband behavior at radio frequencies and baseband in combination with low noise figures and high linearity, as well as the required fast LO hopping. Currently most UWB transceivers are realized in a BiCMOS technology. However, recently presented circuit techniques and achievements in CMOS indicate that CMOS transceivers will start competing with their BiCMOS counterparts.

D. M. W. Leenaerts

7 Integrated on-chip

RF input LNA, mixer

BB filter

2 mm

Multitone generator

I Pre-filter

BB outputs

ADC

Q

LNA Mixer

BB amplifier/filter

Synthesizer

2 mm (a)

(b)

Figure 10: Chip photograph (a) and block diagram (b) of a fully integrated UWB receiver.

Table 1: Measured data of the receiver of Figure 10 (assuming 20 dB attenuation by prefilter). Parameter Current consumption Noise figure Input IP2 Input IP3 Maximum gain VCO phase noise Integrated phase noise In-band spurs Out-of-band spurs Hopping speed 1 Requirement

Required

Measured

Info

— < 6.6 dB1 > +20 dBm > −9 dBm — < −100 dBc/Hz < 3.5 degrees rms < −30 dBc

78 mA @ 2.5 V 4.5 dB +25 dBm −6 dBm 59 dB −104 dBc/Hz 1 degrees rms < −30 dBc

— On PCB, center of IF band, LO is 3960 MHz fin1 : 5 GHz ISM, fin2 : GSM1900 fin1 : 5 GHz ISM, fin2 : 5 GHz ISM Power gain from RF input to base band output At 1 MHz offset Integrated from 0 to 50 MHz —

< −50 dBc < −45 dBc

< −50 dBc < −45 dBc

For 5 GHz ISM For 2.4 GHz ISM

< 9.5 ns

< 1 ns

For all allowed hopping sequences

is < 4.6 dB assuming a pre-filter insertion loss of 2 dB.

ACKNOWLEDGMENT The author would like to acknowledge the much-appreciated inputs from the Philips UWB team, both in Eindhoven as well as in San Jose, Calif. REFERENCES [1] http://www.ieee802.org/15/pub/TG3a.html. [2] “‘Multi-band OFDM Physical Layer Proposal for IEEE 802.15 Task Group 3a’,” IEEE P802.15 Working Group for Wireless Personal Area Networks, March 2004. [3] B. Razavi, H.-C. Kang, C.-C. Hsu, and C.-C. Lee, “Multiband UWB transceivers,” in Proceedings of the IEEE Custom Integrated Circuits Conference (CICC ’05), pp. 140–147, San Jose, Calif, USA, September 2005. [4] A. Ismail and A. Abidi, “A 3 to 10 GHz LNA using a wideband LC-ladder matching network,” in Proceedings of IEEE International Solid-State Circuits Conference (ISSCC ’04), vol. 1, pp. 384–534, San Francisco, Calif, USA, February 2004.

[5] A. Bevilacqua and A. M. Niknejad, “An ultra-wideband CMOS LNA for 3.1 to 10.6 GHz wireless receivers,” in Proceedings of IEEE International Solid-State Circuits Conference (ISSCC ’04), vol. 1, pp. 382–533, San Francisco, Calif, USA, February 2004. [6] P. Heydari, D. Lin, A. Shameli, and A. Yazdi, “Design of CMOS distributed circuits for multiband UWB wireless receivers [LNA and mixer],” in Proceedings of IEEE Radio Frequency Integrated Circuits (RFIC ’05), pp. 695–698, Long Beach, Colo, USA, June 2005. [7] P. Heydari and D. Lin, “A performance optimized CMOS distributed LNA for UWB receivers,” in Proceedings of the IEEE Custom Integrated Circuits Conference (CICC ’05), pp. 330– 333, San Jose, Calif, USA, September 2005. [8] M. Tsai, K.-Y. Lin, and H. Wang, “A 5.4mW LNA using a 0.35µm SiGe BiCMOS technology for 3.1-10.6GHz UWB wireless receivers,” in Proceedings of the IEEE Custom Integrated Circuits Conference (CICC ’05), pp. 337–340, San Jose, Calif, USA, September 2005. [9] B. Razavi, T. Aytur, F.-R. Yang, et al., “A 0.13 µm CMOS UWB transceiver,” in Proceedings of IEEE International Solid-State

8

[10]

[11]

[12] [13]

[14]

[15]

[16]

[17]

[18]

[19]

[20]

[21]

[22]

[23]

EURASIP Journal on Wireless Communications and Networking Circuits Conference (ISSCC ’05), vol. 1, pp. 216–594, San Francisco, Calif, USA, February 2005. S. Iida, K. Tanaka, H. Suzuki, et al., “A 3.1 to 5 GHz CMOS DSSS UWB transceiver for WPANs,” in Proceedings of IEEE International Solid-State Circuits Conference (ISSCC ’05), vol. 1, pp. 214–594, San Francisco, Calif, USA, February 2005. J. Bergervoet, K. Harish, G. van der Weide, et al., “An interference robust receive chain for UWB radio in SiGe BiCMOS,” in Proceedings of IEEE International Solid-State Circuits Conference (ISSCC ’05), vol. 1, pp. 200–593, San Francisco, Calif, USA, February 2005. G. Chevallier and E. F. Stikvoort, Transformer Circuit, Double-Balanced Mixer, US patent 5825231. A. Ismail and A. Abidi, “A 3.1 to 8.2 GHz direct conversion receiver for MB-OFDM UWB communications,” in Proceedings of IEEE International Solid-State Circuits Conference (ISSCC ’05), vol. 1, pp. 208–593, San Francisco, Calif, USA, February 2005. S. Aggarwal, D. M. W. Leenaerts, R. van de Beek, et al., “A low power implementation for the transmit path of a UWB transceiver,” in Proceedings of the IEEE Custom Integrated Circuits Conference (CICC ’05), pp. 148–151, San Jose, Calif, USA, September 2005. C. Grewing, K. Winterberg, S. van Waasen, et al., “Fully integrated distributed power amplifier in CMOS technology, optimized for UWB transmitters,” in Proceedings of IEEE Radio Frequency Integrated Circuits Symposium (RFIC ’04), pp. 87– 90, Fort Worth, Tex, USA, June 2004. D. M. W. Leenaerts, R. van de Beek, G. van der Weide, et al., “A SiGe BiCMOS 1ns fast hopping frequency synthesizer for UWB radio,” in Proceedings of IEEE International Solid-State Circuits Conference (ISSCC ’05), vol. 1, pp. 202–593, San Francisco, Calif, USA, February 2005. D. M. W. Leenaerts, J. van der Tang, and C. S. Vaucher, Circuit Design for RF Transceivers, Kluwer Academic, Dordrecht, The Netherlands, 2001. C.-C. Lin and C.-K. Wang, “A regenerative semi-dynamic frequency divider for mode-1 MB-OFDM UWB hopping carrier generation,” in Proceedings of IEEE International Solid-State Circuits Conference (ISSCC ’05), vol. 1, pp. 206–207, San Francisco, Calif, USA, February 2005. R. van de Beek, D. M. W. Leenaerts, and G. van der Weid, “A fast-hopping single-PLL 3-band UWB synthesizer in 0.25µm SiGe BiCMOS,” in Proceedings of the 31st European Solid-State Circuits Conference (ESSCIRC ’05), pp. 173–176, Grenoble, France, September 2005. J. Lee and D. Chiu, “A 7-band 3-8 GHz frequency synthesizer with 1 ns band-switching time in 0.18 µm CMOS technology,” in Proceedings of IEEE International Solid-State Circuits Conference (ISSCC ’05), vol. 1, pp. 204–593, San Francisco, Calif, USA, February 2005. R. Roovers, D. M. W. Leenaerts, J. Bergervoet, et al., “An interference-robust receiver for ultra-wideband radio in SiGe BiCMOS technology,” IEEE Journal of Solid-State Circuits, vol. 40, no. 12, pp. 2563–2572, 2005. P. Heydari, “Design considerations for low-power ultra wideband receivers,” in Proceedings of IEEE 6th International Symposium on Quality of Electronic Design (ISQED ’05), pp. 668– 673, San Jose, Calif, USA, March 2005. P. Heydari, “A study of low-power ultra wideband radio transceiver architectures,” in Proceedings of Wireless Communications and Networking Conference (WCNC ’05), vol. 2, pp. 758–763, New Orleans, La, USA, March 2005.

D. M. W. Leenaerts received the Ph.D. degree in electrical engineering from Eindhoven University of Technology, Eindhoven, the Netherlands, in 1992. From 1992 to 1999, he was with Eindhoven University of Technology as an Associate Professor with the Microelectronic Circuit Design Group, involved in analog circuit design and nonlinear circuit theory. In 1995, he was a Visiting Scholar with the Department of Electrical Engineering and Computer Science, University of California, Berkeley. In 1997, he was an Invited Professor with the Technical University of Lausanne (EPFL), Lausanne, Switzerland. Since 1999, he has been a Principal Scientist with Philips Research Laboratories, Eindhoven, where he is involved in RF integrated transceiver design, especially for WLAN/WPAN applications. He has published over 150 papers in scientific and technical journals and conference proceedings and holds several patents. He has coauthored several books, including Circuit Design for RF Transceivers (Kluwer, Boston, Mass, 2001). He served as an IEEE Distinguished Lecturer and Associate Editor of the IEEE Transactions on Circuits and Systems: Part I. Currently he serves as a Member in the AdCom of the Solid-State Circuits Society. He is a Fellow of the IEEE.

Hindawi Publishing Corporation EURASIP Journal on Wireless Communications and Networking Volume 2006, Article ID 74812, Pages 1–14 DOI 10.1155/WCN/2006/74812

Error Control Coding in Low-Power Wireless Sensor Networks: When Is ECC Energy-Efficient? Sheryl L. Howard, Christian Schlegel, and Kris Iniewski Department of Electrical & Computer Engineering, University of Alberta, Edmonton, AB, Canada T6G 2V4 Received 31 October 2005; Revised 10 March 2006; Accepted 21 March 2006 This paper examines error control coding (ECC) use in wireless sensor networks (WSNs) to determine the energy efficiency of specific ECC implementations in WSNs. ECC provides coding gain, resulting in transmitter energy savings, at the cost of added decoder power consumption. This paper derives an expression for the critical distance dCR , the distance at which the decoder’s energy consumption per bit equals the transmit energy savings per bit due to coding gain, compared to an uncoded system. Results for several decoder implementations, both analog and digital, are presented for dCR in different environments over a wide frequency range. In free space, dCR is very large at lower frequencies, suitable only for widely spaced outdoor sensors. In crowded environments and office buildings, dCR drops significantly, to 3 m or greater at 10 GHz. Interference is not considered; it would lower dCR . Analog decoders are shown to be the most energy-efficient decoders in this study. Copyright © 2006 Sheryl L. Howard et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

1.

INTRODUCTION

Wireless sensor networks are currently being considered for many communications applications, including industrial, security surveillance, medical, environment and weather monitoring, among others. Due to limited embedded battery lifetime at each sensor node, minimizing power consumption in the sensors and processors is crucial to successful and reliable network operation. Power and energy efficiency is of paramount interest, and the optimal WSN design should consume the minimum amount of power needed to provide reliable communication. New approaches in transmitter and system design have been proposed to lower the required power in the sensor network [1–14]. Error control coding (ECC) is a classic approach used to increase link reliability and lower the required transmitted power. However, lowered power at the transmitter comes at the cost of extra power consumption due to the decoder at the receiver. Stronger codes provide better performance with lower power requirements, but have more complex decoders with higher power consumption than simpler error control codes. If the extra power consumption at the decoder outweighs the transmitted power savings due to using ECC, then ECC would not be energy-efficient compared with an uncoded system. Previous research using ECC in wireless sensor networks focused primarily on longtime industry-standard codes such

as Reed-Solomon and convolutional codes. A hybrid scheme choosing the most energy-efficient combination of ECC and ARQ is considered in [15], using checksums, CRCs, Reed-Solomon and convolutional codes. A predictive errorcorrection algorithm is presented in [16] which uses data correlation, but is not an error control code, as there is no encoding. Power-aware, system-level techniques including modulation and MAC protocals, as well as differing rate and constraint length convolutional coding, are considered in [17] to reduce system energy consumption in wireless microsensor networks. Depending on the required bit error rate (BER), a higher rate convolutional code, or no coding at all, could be the most energy-efficient approach. This paper examines several different decoder implementations for a range of ECC types, including block codes, convolutional codes, and iteratively decoded codes such as turbo codes [18] and low-density parity-check codes (LDPCs) [19]. Both digital and analog implementations are considered. Analog implementations seem a natural choice for low-power applications due to their minimal power consumption with subthreshold operation. Decoder power consumption is compared to coding gain and energy savings at the transmitter for each decoder implementation to determine at what distance use of that decoder becomes energy-efficient. Different environments and a range of frequencies are considered. Our initial work in

2

EURASIP Journal on Wireless Communications and Networking

[20, 21] is extended to a more realistic power consumption model, and transmitter efficiency is considered as well. Equations for the critical distance dCR , where energy expenditure per data bit is equivalent for the coded and uncoded system, are developed and presented for both high and low throughput channels. At distances greater than dCR , use of the coded system results in net energy savings for a WSN. Section 2 of this paper presents a framework for the factors that affect the minimum transmitter power, and a path loss model. Basic types of ECC are presented in Section 3. Section 4 explores the energy savings from ECC in terms of coding gain, presents models for the power consumption of a decoder at high and low throughput, and develops equations for the total energy savings, combining transmit energy savings with decoder energy cost, and for the critical distance dCR . The critical distances for actual decoder implementations are found in Section 5 for several different environments and frequencies. Conclusions based on these results are presented in Section 6. 2.

TRANSMITTED POWER AND PATH LOSS

2.1. Minimum transmitted power Minimizing transmitted RF power is the key to energyefficient wireless sensor networks [1–3]. To shed more light on RF transmission power, let us consider that the receiver has a required minimum signal-to-noise power S/N, below which it cannot operate reliably. Often, this requirement is expressed in terms of minimum Eb /N0 , where Eb is the required minimum energy per bit at the receiver, and N0 is the noise power spectral density. The S/N can be found as [22] S REb Eb = =η , N N0 B N0

(1)

where R is the information rate or throughput in bps, B is the signal bandwidth, and η, the ratio of the information rate to the bandwidth, is known as the spectral efficiency. The signal noise N may be expressed as proportional to thermal noise and the signal bandwidth B, as [23] N = mkTB,

(2)

where m is a noise proportionality constant, k is the Boltzmann constant, and T is the absolute temperature in K. The receiver noise figure RNF in dB is incorporated into the proportionality constant m such that m ≥ 1 and m = 10RNF /10 . An ideal receiver with RNF = 0 dB results in m = 1. Finally, the received signal power SRX = S at a distance d from the transmitting source can be expressed in free space using the Friis transmission formula [24], assuming an omnidirectional antenna and no interference or obstacles, 

SRX



1 λ2 = PTX , 2 4πd 4π

(3)

where λ is the transmitted wavelength corresponding to the

transmitting frequency f with λ = c/ f , and PTX is the transmitted power. Equations (1), (2), and (3) may be combined to express the minimum transmitted power PTX required to achieve S/N at a receiver a distance d away, in free space, without interference, as 

PTX =

S 4πd N N λ

2



PTX

,

4πd Eb = η mkTB N0 λ

(4)

2

.

Note that in (4) the minimum transmitted power is proportional to distance squared, d2 , between transmitter and receiver, and inversely proportional to λ2 , which means the power is proportional to frequency f . Operation at higher frequencies requires higher transmit power. Section 2.2 considers the effect of transmitting in an environment which is not free space. Many transmission environments include significant obstacles, and interference, and have reduced line-of-sight (LOS) components. Signal path loss or attenuation in these environments can be significantly greater than that in free space. We will not consider external sources of interference in these environments; only structural interference by obstacles such as walls, doors, furniture, and carpeted wall dividers is considered. 2.2.

Path loss modeling

The Friis transmission formula is rewritten below in a different form, as (7) is a well-known formula for RF transmission in a free space in a far-field region [24]. Since wireless sensors are likely to be deployed in a number of different, physically constrained environments, it is worthwhile exploring its limitations. The space surrounding a radiating antenna is typically subdivided into three different regions [24]: (i) reactive near field, (ii) radiating near field (Fresnel region), (iii) far field (Fraunhofer region). As the Friis formula applies to the far-field region, it is important to establish a minimum distance dff where the far field begins, and beyond which (3) and (7) are valid. The physical definition of the far-field is the region where the field of the antenna is essentially independent of the distance from the antenna. If the antenna has a maximum dimension D, the far-field region is commonly recognized to exist if the sensor separation d is larger than [24] d > dff =

2D2 . λ

(5)

While sensor nodes can use different kinds of antennas depending on cost, application, and frequency of operation, a first-order estimate of the antenna size D can be assumed as λ/L, where L is an integer whose value is dependent on antenna design. The above assumption expresses a common

Sheryl L. Howard et al.

3

relationship between antenna size and the corresponding radiating wavelength λ. Substituting D = λ/L into (5), the distance limitation can be expressed as d > dff =

2 λ. L2

(6)

Typical frequencies used in RF transmission vary from as low as 400 MHz (Medical Implant Communications Service— MICS) to 10 GHz (highest band of ultra-wideband technology) with many services offered around 2.4 GHz (Bluetooth, Wireless LAN—802.11, some cellular phones). The corresponding wavelengths change from 75 cm (at 400 MHz) down to 33 mm (at 10 GHz). As a result, the limitations imposed by (6) seem not too restrictive, as even at the lowest frequencies, with largest wavelength, dff will be below 1 m. Even if one does not assume proportionality between the antenna size D and wavelength λ, it would be straightforward to calculate the minimum distance dff directly from (5). For practical reasons due to size limitation, the antenna should not be much larger than the sensor node hardware itself, which in turn should not be larger than a few cubic centimeters. As a result, D should not be larger than 10 cm, resulting in dff of a fraction of a meter at most. In further deliberations, we will assume that the distance between sensors is at least 1 meter, which places both corresponding antennas between the receiver and transmitter in the far-field region. The results of Section 5.1 regarding the distance at which ECC becomes energy-efficient for various decoder implementations will justify this assumption. Equation (3) can be written as 

PL(d) =

SRX (d) 4πd = PTX λ

2

,

(7)

where PL is a path loss, which is the loss in signal power at a distance d due to attenuation of the field strength. In a log scale, (7) becomes [25] 

 

PL(d) = PL d0 + 10n log10



d , d0

(8)

where n = 2. Later this equation is generalized to include other values of n, which better fit the measured attenuation of environments which are more cluttered or confined than the free space assumption: (i) n = mean path loss exponent (n = 2 for free space), (ii) d0 = reference distance = 1 m, (iii) d = transmitter-receiver separation (m) and the reference path loss at d0 is given by  

PL d0 = 20 log10





4πd0 , λ

(9)

(iv) λ = the wavelength of the corresponding carrier frequency f . The second, more important, limitation of the Friis transmission formula results from the free space propagation assumption. In reality for practically deployed wireless sensor networks, it is unlikely that this assumption will remain

valid. Small antennas causing Fresnel zone losses, multiple objects blocking line of sight, or walls and ceilings in indoor environments will all cause deviations from the simple prediction of (7). Various models have been developed over the years to improve the accuracy of (7) under different conditions [26– 29]. Recently a path loss model based on the geometrical properties of a room was presented in [30]. The authors derived equations for the upper and lower bounds of the mean received power (MRP) of a transmission in the room, for random transmitter and receiver locations. Although mathematically complex, these equations fail to reproduce the experimental data of [30]. In fact, the simple equation (7) seems to provide better accuracy. However, the problem with (7) is that it does not take into account losses caused by transmission through walls, reflections from ceilings and Fresnel zone blockage effects. In order to account for some of these effects, one model [31] proposes to apply an additional correction factor in the form of a linear (on a log scale) attenuation factor, in addition to the value predicted by (7). The additional attenuation factor ranges from 0.3 to 0.6 dB/m depending on selected frequency. To retain generality but keep the path loss equation simple, we will follow many others [25, 26, 32, 33], in assuming the form of (8) with n being an empirically fitted parameter depending on the environment. For free space conditions, n = 2 as stated by the Friis transmission formula (7). In real deployment conditions, attenuation loss with distance d will increase more than the squared response implied by (7). To accommodate a wide variety of conditions, the path loss exponent in (3) can be changed from n = 2 up to n = 4, with n = 3 being a typical value when walls and floors are being considered. Under special conditions, the coefficient n might lie outside the 2–4 range; for example, for short distance line-ofsight paths, the path loss exponent can be below n = 2 [26]. This is especially true in hallways, as they provide a waveguiding effect. In other conditions, n > 4 has been suggested if multiple reflections from various objects are considered. In the following section, we will assume the validity of (8) with a value of n in the range from n = 2 to n = 4, with n = 3 being representative of most typical indoor environments and outdoor urban/suburban foliated areas [34]. Dense outdoor urban environments can have n ≥ 4 [35]. 3.

ERROR CONTROL CODING

Error control coding (ECC) introduces redundancy into an information sequence u of length k by the addition of extra parity bits, based on various combinations of bits of u, to form a codeword x of length nC > k. The redundancy provided by these extra nC − k parity bits allows the decoder to possibly decode noisy received bits of x correctly which, if uncoded, would be demodulated incorrectly. This ability to correct errors in the received sequence means that use of ECC over a noisy channel can provide better bit error rate (BER) performance for the same signal-to-noise ratio (SNR) compared to an uncoded system, or can provide the same BER at

EURASIP Journal on Wireless Communications and Networking

a lower SNR than uncoded. This difference in required SNR to achieve a certain BER for a particular code and decoding algorithm compared to uncoded is known as the coding gain for that code and decoding algorithm. Typically there is a tradeoff between coding gain and decoder complexity. Very long codes provide higher gain but require larger decoders with high power consumption, and similarly for more complex decoding algorithms. Several different types of ECC exist, but we may loosely categorize them into two divisions: (1) block codes, which are of a fixed length nC , with nC − k parity bits, and are decoded one block or codeword at a time; (2) convolutional codes, which, for a rate k/nC code, input k bits and output nC bits at each time interval, but are decoded in a continuous stream of length L  nC . Block codes include repetition codes, Hamming codes [36], Reed-Solomon codes [37], and BCH codes [38, 39]. The terminology (nC , k) or (nC , k, dmin ) indicates a code of length nC with information sequence of length k, and minimum distance (the minimum number of different bits between any of the codewords) dmin . Short block codes like Hamming codes can be decoded by syndrome decoding or maximum likelihood (ML) decoding by either decoding to the nearest codeword or decoding on a trellis with the Viterbi algorithm [40] or maximum a posteriori (MAP) decoding with the BCJR algorithm [41]. Algebraic codes such as Reed-Solomon and BCH codes are decoded with a complex polynomial solver to determine the error locations. Convolutional codes are decoded on a trellis using either Viterbi decoding, MAP decoding, or sequential decoding. Another categorization is based on the decoding algorithms: (1) noniterative decoding algorithms, such as syndrome decoding for block codes or maximum likelihood (ML) nearest-codeword decoding for short block codes, algebraic decoding for Reed-Solomon and BCH codes, and Viterbi decoding or sequential decoding for convolutional codes; (2) iterative decoding algorithms, such as turbo decoding with component MAP decoders for each component code, and the sum-product algorithm (SPA) [42] or its lower complexity approximation, min-sum decoding [43, 44], for low-density parity-check codes (LDPCs). The noniterative decoding category may be further divided into hard- and soft-decision decoders; hard-decision decoders output a final decision on the most likely codeword, while soft-decision decoders provide soft information in the form of probabilities or log-likelihood ratios (LLRs) on the individual codeword bits. Viterbi decoding can be either hard-decision or soft-decision, with a 2 dB gain in performance for soft-decision decoding. Category (2) are all softdecision algorithms by nature, as iterative decoding requires soft information as a priori input for each iteration. Iterative decoding algorithms provide significant coding gain, at the cost of greater decoding complexity and power consumption. Figure 1 shows BER performance versus SNR for several types of error-correcting codes, compared to uncoded BPSK (binary phase-shift keying) modulation. Transmission is over an additive white Gaussian noise (AWGN) channel, with variance N0 /2 and zero mean, using BPSK modulation

10−1

10−2

Bit error rate

4

10−3

10−4

10−5

10−6

1

2

3

4

5 6 7 8 SNR = Eb /N0 (dB)

Uncoded BPSK (255, 239) RS (8, 4) EHC: MAP (16, 11) EHC: MAP r 1/2 K = 7 CC: hard-dec

9

10

11

12

r 1/2 K = 7 CC: soft-dec r 1/3 N = 40 PCCC (16, 11)2 TPC: MAP Irr N = 1024 LDPC

Figure 1: BER performance versus SNR for several error-correcting codes.

for all encoded bits. Note that the SNR = Eb /N0 in dB is an energy ratio, rather than the power ratio S/N. The received energy per bit Eb is energy per symbol over code rate Es /R, with constant Es , and N0 is the noise power spectral density. The thick black line indicates a BER of 10−4 ; the coding gain for each code at this BER is easy to determine. Three block codes are shown: a (255, 239, 17) ReedSolomon code, an (8, 4, 4) extended Hamming code, and a (16, 11, 4) extended Hamming code. Note that the longer extended Hamming code provides better performance due to its longer length. The Reed-Solomon code does not provide better performance until a much lower BER, even though it is significantly longer and has a better minimum distance, due to its higher rate. Two convolutional codes, both rate 1/2 64-state constraint length 7, are compared [45]. One uses a hard-decision Viterbi decoder and the other uses a soft-decision Viterbi decoder. The soft-decision decoder performs about 2 dB better than the hard-decision decoder. Three iteratively decoded codes are displayed as well, and the power of iterative decoding is clearly shown. These three codes provide the best performance on the graph. The parallel concatenated convolutional code (PCCC) is a classic turbo code, and used in the 3 GPP standard, although it is short; it has an interleaver and information sequence size of 40 bits, with a codeword length of 132 bits [46]. The (16, 11)2 turbo product code is composed of component (16,11) extended Hamming codes, decoded with MAP decoding [47]. The rate 1/2 length 1024 irregular LDPC is similar to the code implemented in [48], with 64 decoding iterations used. The use of ECC can allow a system to operate at significantly lower SNR than an uncoded system, for the same BER.

Sheryl L. Howard et al.

5

Whether this coding gain ECCgain = SNRU − SNRECC provides sufficient energy savings due to the lowered minimum transmitted power requirement to outweigh the cost of extra power consumption due to the decoder will be examined in the next section. 4.

ENERGY SAVINGS FROM ECC

4.1. Minimum required transmit power For an uncoded system, the minimum required transmit power PTX,U at the signal-to-noise ratio (termed SNRU ) required to achieve a desired BER is found from (4) and (7) to be 

PTX,U [W] = ηU

Eb 4π N N0 λ

2

dn , 

4π PTX,U [W] = ηU 10(SNRU /10+RNF/10) (kTB) λ

WSN scenario, transmitting with as much power as possible, up to regulatory limits, is not desirable. Rather, transmitting with as little power as possible, so as to extend sensor battery life, while maintaining a minimum required SNR, is our goal. Similar to a deep-space satellite scenario, the lowpower WSN is far more power-constrained than bandwidthconstrained. In order to achieve power efficiency, we are willing to sacrifice spectral efficiency. An equation similar to (10), but for the minimum required transmit power PTX,ECC using ECC, can be found. Recall that the required SNRECC is less than SNRU by the coding gain ECCgain . Also note that ηC BC = R and ηU B = R. The minimum required transmit power when using ECC, PTX,ECC , is given by 

(10)

2

PTX,ECC [W] = ηC 10(SNRECC /10+RNF /10) kTBC

dn ,

where ηU is the uncoded system’s spectral efficiency. RNF is the receiver noise figure in dB and SNRU is the required SNR = Eb /N0 in dB to achieve the target BER with an uncoded system. The path loss exponent n depends on the environment. At the frequencies of interest, d > λ as stated in Section 2.2, so the far-field approximation of (8) is valid. The uncoded system has a transmission rate R and bandwidth B, so the uncoded spectral efficiency ηU = R/B. We consider BPSK-modulated transmission, which has a maximum possible spectral efficiency of ηmax = 1, and so we require that B = R and ηU = 1. For an equal comparison, we require that the coded system also have an information transmission rate R. Recall that the information bits are the uncoded bits before going into the encoder, and the coded bits are the bits output from the encoder. The number of coded bits is greater than the number of information bits, so it would be an unfair comparison to consider the coded system to have a coded transmission rate of R, as then the information transmission rate would decrease to R∗RC . The code rate RC is the number of information bits divided by the number of codeword bits. This means the uncoded system would be decoding R information bits per second, assuming BPSK modulation, while the coded system would decode only R∗RC information bits per second. This would give the coded system an unfair advantage. Thus we require that the coded system transmit at an information transmission rate of R, as for the uncoded system. The coded transmission rate or coded channel throughput R then increases to R = R/RC , for a code of rate RC . The bandwidth of the coded system, BC , is assumed to increase with the coded transmission rate, so that BC = R . Thus the coded system’s spectral efficiency decreases to ηC = R/BC = RC . Minimizing transmit power is considered herein to be the most critical parameter for a low-power WSN, whose battery lifetime is dependent on power consumption. Therefore all transmit power and energy calculations use the minimum required transmit power and energy. In a low-power

PTX,ECC [W] =

4π λ

2

dn ,

ηC BC PTX,U PTX,U = ECCgain /10 . ηU B 10ECCgain /10 10 (11)

The required transmit power PTX is converted to required transmit energy per transmitted information bit by dividing PTX by the information transmission rate R in bps to obtain EbTX = PTX /R in J/bit. Since the information transmission rate R is the same for both uncoded and coded systems, the ratio of uncoded to coded energy per transmitted bit remains the same as for power. The information rate R is also assumed constant over all transmission distances d. This allows for a straightforward comparison of the minimum required transmit energy and power of coded and uncoded systems at different distances. The transmit energy savings per information bit of the coded system is found as the difference between the minimum required transmit energy per information bit for uncoded and coded systems, as EbTX,U [J/bit] = EbTX,ECC [J/bit] =

PTX,U , R

PTX,ECC EbTX,U = ECCgain /10 , R 10 

(12) 

EbTX,U − EbTX,ECC = EbTX,U 1 − 10−ECCgain /10 . Use of ECC lowers the required minimum transmit power and energy per decoded bit as a result of the coding gain ECCgain . However, at the receiver, the coded system has the added power consumption of its decoder, which must be factored in as a cost of using ECC. We do not consider the additional power consumed by the encoder; typically the encoder is much smaller and consumes significantly less power than the decoder. Decoder implementation results usually present one or two power consumption measurements at specified throughputs. We can factor in the cost of the decoder power consumption by taking the power consumption value at an

EURASIP Journal on Wireless Communications and Networking

information throughput equal to the information transmission rate R, and dividing the power consumption by the throughput R to get energy per decoded bit Ebdec . However, the power consumption values available for the implementations are almost always for high throughput. A model is needed to estimate the decoder power consumed at throughput below that measured, based on the available power consumption data. 4.2. Decoder power consumption

(13)

The dynamic power consumption increases linearly with frequency, and becomes the dominant factor at higher frequencies. At low frequencies, static power consumption dominates and the total power consumption no longer increases linearly with frequency, but approaches the static value. This is seen from the total power consumption model as Ptotal ( f ) ≈ a f + b,

2 a = CVdd , b = Ileak Vdd .

Digital N = 1024 LDPC SPA decoder: throughput versus power

10−1

Power estimated as 3.75e − 10∗ throughput +3.9e − 3

10−2

The power consumption of a digital CMOS decoder consists of two types: dynamic and static. Dynamic power consumption is primarily due, in CMOS logic, to the switching capac2 itance, and is modeled as Pd ≈ CVdd f , where C is the total switched capacitance, Vdd is the power supply voltage, and f is the operating, or clock, frequency. The static power consumption is due to leakage current and DC biasing sources, and can be modeled as Ps = Ileak Vdd , where Ileak is the leakage current. The total power consumption is modeled as [49] 2 Ptotal = Pd + Ps ≈ CVdd f + Ileak Vdd .

100

Power (W)

6

(14)

The decoder throughput R is proportional to f over most of the range of f , so the total power Ptotal ∝ aR + b. At high frequencies, near the limit of the clocking frequency, the dynamic power will increase superlinearly with f , and the chip dissipates large amounts of power. We will not consider operation near the high-frequency limits of chip performance. Figure 2 shows actual power versus throughput measurements for a digital implementation of a length 1024 rate 1/2 LDPC decoder incorporating the sum-product algorithm (SPA) [48]. A linear approximation for the normalized power is compared to the actual measurement data. The linear approximation is quite accurate in the linear, dynamic-powerdominated region of the power versus throughput curve. From the decoder power consumption approximation, the energy cost per decoded information bit could be found as Ebdec = Ptotal /R. There is an additional factor to consider in power consumption, which is the implementation process. The decoder implementations presented in Table 1 span several different CMOS processes: from 0.5 μm to 0.16 μm. Larger processes have higher supply voltage and dissipate greater amounts of power. So as not to unfairly penalize decoders implemented

10−3

106

107 108 Throughput in bps

109

Measured power dissipation Approximated power dissipation

Figure 2: Power versus throughput: measured values and linear approximation for digital LDPC implementation.

in a larger process size, we scale the energy per decoded bit 2 by Vdd . This results in an energy per decoded information bit Ebdec , normalized to a supply voltage of 1 V, as Ebdec =

Ptotal 2 . RVdd

(15)

When operating anywhere in the dynamic power/high throughput region, the energy per decoded information bit is constant at Ebdec =

Pmax 2 . Rmax Vdd

(16)

This paper also considers analog decoder implementations, which use very small bias currents, so that the transistors operate in the subthreshold region. Hence, analog decoders inherently have very low power dissipation, and would seem a good choice for power-limited applications such as wireless sensor networks. 4.3.

Energy savings of ECC and critical distance

The total energy cost or gain of using ECC with a particular decoder implementation, at a given frequency, distance, throughput, and required BER, may then be found as the combination of its energy savings due to coding gain from (12), plus the energy cost due to decoder power consumption as (15). This energy savings ΔES with respect to an uncoded system is found as the difference in minimum transmitted energy per information bit between uncoded and coded, minus the additional energy cost at the decoder. Recall that

Sheryl L. Howard et al.

7

Table 1: Different decoder implementations: coding gain, maximum measured core power consumption and information throughput, and energy per decoded information bit, normalized to Vdd = 1, at maximum measured power and throughput. Decoder implementation

Coding gain in dB

(255,239) RS digital Digital rate 1/2 CC hard-dec Viterbi Digital rate 1/2 CC soft-dec Viterbi (8,4) EHC analog (16,11) EHC analog (16, 11)2 TPC analog Rate 1/3 turbo analog N = 1024 LDPC digital (32,8,10) LDPC analog

Pmax in mW

2 2.3 4.2 2 2.6 5.7 4.8 6.1 1.3

ΔES = 10(SNRU /10+RNF /10) kT −



4π λ

1.8 1.8 2.2 0.8 1.8 1.8 2 1.5 1.8

0.1193 0.2475 0.1138 0.0633 0.0062 0.0266 0.5125 0.56 0.0193

0.18 0.18 0.35 0.18 0.18 0.18 0.35 0.16 0.18

2

2



Pmax λ   = 2 10(SNRU /10+RNF/10) kTRmax Vdd 1 − 10−ECCgain /10 4π



dn 1 − 10−ECCgain /10



dn 1 − 10−ECCgain /10





Ptotal 2 . RVdd

dCR



Ptotal λ   2 10(SNRU /10+RNF/10) kTRVdd 1 − 10−ECCgain /10 4π

2 1/n

. (19)

The distance d at which ΔES = 0 is termed the critical distance dCR . This is the distance at which use of a particular decoder implementation becomes energy-efficient. For sensors greater than a distance dCR apart, use of that decoder implementation saves energy compared to an uncoded system. The critical distance dCR is found from (17) as



160 106 67 3.7 135 1000 2 500 80



(17)

=

Process size in μm

dCR

 PTX,U  = 1 − 10−ECCgain /10 − Ebdec R 

Ebdec in nJ/bit

given by

ΔES = EbTX,U − EbTX,ECC − Ebdec

10(SNRU /10+RNF /10) kTB 4π R λ Ptotal − 2 , RVdd

Vdd in V

58 85 83 0.15 2.7 86.1 4.1 630 5

B = R. The energy savings ΔES is given by

=

Rmax in Mbps

2 1/n

For a low throughput channel, we need to consider the type of network traffic across the channel. Bursty traffic, where long periods of silence are interspersed with brief bursts of data, is representative of many types of low throughput networks. Examples are weather sensors or patient temperature sensors reporting conditions at fixed intervals, or sensors receiving data from security cameras at an isolated facility that only transmit data when there is movement or pixel change. Bursty traffic channels, while on average low throughput, are better represented as a channel which has high throughput for a certain percentage of time, and no throughput the rest of the time. In the bursty traffic scenario, a low throughput channel of rate R is viewed as having high throughput or transmission rate R1 > R for 100h% of the time, where 0 ≤ h ≤ 1, and no throughput 100(1 − h)% of the time, such that hR1 = R. The decoder is assumed to be powered down during periods of no throughput. During the time when the decoder is operating, throughput is high and decoder power consumption follows the dynamic power consumption model. Averaged over time, the total decoder power consumption is found to be

. (18)

Ptotal is represented as a linear function of the throughput R, as Ptotal = Pmax ∗R/Rmax . Recall that Pmax and Rmax are the maximum measured power and throughput values, respectively, and they fall within the decoder’s dynamic power consumption region. The static power contribution is considered to be negligible in the dynamic region. The factor of (1/R)1/n in (18) will be canceled, in the dynamic region, by R in Ptotal . Thus dCR in the dynamic region is independent of throughput, and has constant value. The critical distance is

Ptotal =

hR1 Pmax RPmax = , Rmax Rmax

(20)

the same as for the dynamic power consumption case. In other words, bursty traffic effectively lowers the dynamic power region to lower throughputs, because the data itself is delivered at a transmission rate within the dynamic power region. Thus the critical distance dCR for low throughput with bursty traffic is the same as (19). We will not consider a constant low throughput channel, as it is not an energy-efficient method of operating the decoder.

8

EURASIP Journal on Wireless Communications and Networking

Another factor to consider is whether the minimum required uncoded transmit power, PTX,U , exceeds regulatory limits on maximum allowable transmitted power at a certain distance dPlim ≤ dCR . If so, then coding will be necessary simply to reduce the transmit power below regulatory limits. The critical distance dCR for the coded system would then drop to dPlim , provided that the minimum coded transmit power PTX,ECC did not also exceed the maximum power limitation. There are many different regulatory limits, depending on location, frequency, and application. Thus it is not within the scope of this paper to determine whether PTX,U exceeds all possible limits at each frequency, application, and critical distance. However, this is a factor which should be considered for actual usage. The next section considers both digital and analog decoder implementations and determines their critical distances at various frequencies and environments. Path loss exponents range from n = 2 for free space to n = 4 for office space with many obstacles and ranging over multiple floors. Both high and bursty traffic low throughput channels are considered. 5.

CRITICAL DISTANCE RESULTS FOR IMPLEMENTED DECODERS

5.1. Decoder implementations We now examine several different decoder implementations, both analog and digital, for a variety of code types. BPSK transmission over an AWGN channel is assumed for all decoders. Block codes considered include a high-rate digital (255, 239) Reed-Solomon decoder [50], an analog (8, 4, 4) extended Hamming decoder [51] and an analog (16, 11, 4) extended Hamming decoder [47]. Two digital convolutional decoders are included, a hard-decision Viterbi [52] and a soft-decision Viterbi decoder [53]. Both decoders use a rate 1/2, 64-state, constraint length K =7 convolutional code. Iterative decoders are examined as well. An analog rate 1/3 length 132 turbo decoder with interleaver size 40 [46] is considered, as well as an analog (16, 11)2 turbo product decoder [47, 54] using MAP decoding on each component (16, 11) extended Hamming codes. Two LDPC decoders are evaluated, a digital rate 1/2 length 1024 irregular LDPC sumproduct decoder [48] and an analog rate 1/4 (32,8,10) regular LDPC min-sum decoder [55]. Table 1 displays the pertinent data for each decoder, including coding gain in dB, maximum measured decoder core power consumption Pmax , corresponding maximum measured information (not coded) throughput Rmax , core supply voltage Vdd . The decoded energy per information bit, Ebdec , is found with (15), and assumes operation in either the dynamic power consumption region or a bursty traffic low throughput scenario, which is modeled equivalently to the dynamic region. The coding gain is compared to uncoded BPSK at a BER of 10−4 , and is the coding gain of the implemented decoder. The process size for each decoder is also presented. As shown, the analog decoders have the lowest Ebdec values.

Table 2: Parameters used in critical distance calculations. Path loss exponent Frequency range Required BER Uncoded SNR (Eb /N0 ) Receiver noise figure Temperature

5.2.

n = 2, 3, 4 450 MHz–10 GHz 10−4 8.3 dB 5 dB [56] 300 K

Critical distance values

From the energy per decoded data bit, Ebdec , the critical distance dCR for each decoder implementation may be found according to (19) for a variety of scenarios. If we consider either a high throughput channel or a bursty traffic low throughput channel, then dCR , found from (19), is independent of the throughput, with a single value regardless of throughput. First we consider the path loss exponent n, as representative of the transmission environment. We examine dCR for n = 2, as a free space, line-of-sight (LOS) model, either outdoors or in a hallway; n = 3 as an interior environment such as an office building, where the network is all located on the same floor, or an outdoor environment such as forest or foliated urban/suburban locations; and n = 4 as an interior environment with many obstructions and possibly multiple floors, or a dense urban environment. A frequency range from 450 MHz to 10 GHz is considered. Throughput is assumed to be either within the dynamic power region or low but bursty, and the critical distance dCR is calculated according to (19). The parameters used in (19) are displayed in Table 2. Figure 3 shows dCR versus frequency for n = 2, free space path loss, for all decoders in Table 1. The decoder curves are shown in the order in which they appear in the graph legend, that is, top first. At 10 GHz, the lowest critical distances belong to the analog (16,11) extended Hamming and (16, 11)2 turbo product decoders, at 30 and 48 m, respectively. These decoders would be practical in an indoor hallway scenario, where sensors placed at ends of the hallway would have LOS. At lower frequencies, the values of dCR in a free space environment, assuming no interference or extra background noise, are extremely large. Not until f = 3 GHz do any of the critical distances drop below 100 m. For an outdoor scenario where sensors are very widely spaced, with an LOS component, perhaps for either infrequently located security sensors around a large perimeter, along a highway or railroad track, monitoring outdoor weather data, or monitoring a fault line, the large distances even at lower frequencies might be practical. The distances are far too large for any indoor scenario. Figure 4 shows dCR versus frequency for n = 3, an office environment or foliated outdoor environment. The analog decoders could be practical, at the higher frequencies, for security scenarios where one might have security sensors spaced every few houses in an urban environment, or sensors placed in every few rooms of a hotel or office building. The analog (16,11) extended Hamming and

Sheryl L. Howard et al.

9

104 Path loss exponent n=3

103

Critical distance dCR (m)

Critical distance dCR (m)

Path loss exponent n=2

102

101

100

102

101

100 109

1010

1010 Frequency (Hz)

Frequency (Hz) Analog turbo Digital LDPC Digital hard-dec CC Digital Reed-Solomon Digital soft-dec CC

109 Analog turbo Digital LDPC Digital hard-dec CC Digital Reed-Solomon Digital soft-dec CC

Analog (8,4) EHC Analog LDPC Analog (16, 11)2 TPC Analog (16,11) EHC

Analog (8,4) EHC Analog LDPC Analog (16, 11)2 TPC Analog (16,11) EHC

Figure 3: Estimated critical distance dCR versus f for n = 2 free space path loss and high throughput or bursty low throughput channel.

Figure 4: Estimated critical distance dCR versus f for n = 3 path loss exponent and high throughput or bursty low throughput channel.

(16, 11)2 turbo product decoders again have the lowest critical distances, at 15 m and 21 m, respectively, for f = 5 GHz, and 10 and 13 m at 10 GHz. At the lowest frequency of 450 MHz, the lowest critical distance is 76 m for the (16,11) extended Hamming decoder, but all other decoders have critical distances above 100 m. Urban and suburban nodes which are not LOS, such as low buildings located more than a block apart, could be separated by distances greater than the critical distances even at the lowest frequencies, and well above the 2.4 GHz values. Outdoor sensor networks in forested regions monitoring nesting sites, or forest health and dryness, or avalanche-prone regions, could also be spaced further apart than the critical distances at low frequencies. Figure 5 shows dCR versus frequency for n = 4, either an office floor with many obstructions or between multiple floors, or a dense outdoor urban environment. Critical distances, even at the lowest frequencies, are practical for a dense outdoor urban environment without LOS, for all decoders, as long as the sensors are spaced a few buildings apart. For the office environment, the critical distance values are more practical for frequencies of 2 GHz and above. The analog decoders, with the exception of the analog turbo decoder, all have critical distances below 25 m at 2 GHz, and 10 m or less at 10 GHz. The analog (16,11) extended Hamming and (16, 11)2 turbo product decoders again perform the best, with respective dCR values at 10 GHz of 5.5 m and 7 m, at 5 GHz of 8 and 10 m, and at 2.4 GHz of 12 and 15.5 m. These distances could represent a sensor network monitoring different floors of a building, with a node in each office,

or a network monitoring separate enclosures in an animal park. These distances are just feasible, at the higher frequencies, to consider a sensor network for monitoring patients in a hospital. However, with additional interference and background noise, as would be likely in these environments, dCR would certainly decrease, increasing the energy efficiency of each decoder implementation and making ECC more practical for this scenario. The analog decoders, with their extremely low power consumption, provide the most energy-efficient decoding solution in these scenarios, except for the analog turbo decoder. The digital decoders all have higher dCR values, from 2 to 4 times greater than the other analog decoders. For some scenarios, particularly free space transmission at frequencies below 1 GHz, ECC is not energy-efficient, except at very large distances. ECC is not always the best solution to minimizing energy. Our results for dCR clearly show that energy-efficient use of ECC must consider the transmission environment and frequency, as well as decoder implementation. As the environment becomes more crowded, with more obstacles between sensor nodes, ECC becomes more energy-efficient at shorter distances. At the highest frequencies, ECC is practical for all the discussed scenarios when implemented with analog decoders. 5.3.

Correction for power amplifier efficiency

Calculations presented so far have assumed that the power savings in RF transmitted power PTX directly translate into savings of the DC chip power consumption PDC . In practice

10

EURASIP Journal on Wireless Communications and Networking 102

Critical distance dCR (m)

Path loss exponent n=4

101

100

109

1010 Frequency (Hz)

Analog turbo Digital LDPC Digital hard-dec CC Digital Reed-Solomon Digital soft-dec CC

Analog (8, 4) EHC Analog LDPC Analog (16, 11)2 TPC Analog (16, 11) EHC

Figure 5: Estimated critical distance dCR versus f for n = 4 path loss exponent and high throughput or bursty low throughput channel.

this assumption rarely holds true; in fact, both power factors are related through the power amplifier efficiency ε, defined as P (21) ε = TX . PDC Taking this into account, it is straightforward to show that (19), for high throughput or bursty traffic low throughput, needs to be modified as dCR





εPmax λ  = 2 10(SNRU /10+RNF/10) kTRmax Vdd 1−10−ECCgain /10 ) 4π

2 1/n

,

R > Rd . (22) In order to use the above equation, power efficiency numbers for typical CMOS implementations need to be evaluated. As we will show below, ε varies from 19% to 65%, depending on what class power amplifier is used. The reasons for this wide spread of achieved efficiencies can be explained as follows. Contemporary standards such as 802.11 use digital modulation to achieve high spectral efficiency. For example, at 54 Mbps, WLAN uses 64-QAM modulation on each OFDM subcarrier [57], resulting in a transmit waveform with high peak-to-average ratio (PAR). A linear power amplifier must be used, which often has low power added efficiency (PAE), resulting in high power consumption. One step towards more power efficient drivers is to use constant envelope modulation, as in the personal area network standard 802.15.4. Constant envelope transmitters can be driven closer to the compression point, resulting in a

higher PAE; this in turn means lower power consumption. In this case, nonlinear (or switched-mode) power amplifiers may also be used, usually providing much higher efficiencies as a tradeoff for linearity. Typically, switched-mode amplifiers are also simpler in terms of realization complexity, warranting a more effective use of silicon area. The highest efficiency of power amplification in silicon can be achieved using switched mode circuits [12]. Although theoretically, switched-mode PAs can transmit finite power with 100% efficiency, finite CMOS switching times and other effects result in lower efficiencies. As an example, a class E PA proposed in [58] has a PAE of 92.5% at an output power of −4.3 dBm in the 433 MHz ISM band using duty-cycle modulation (DCM). This efficiency figure, however, does not include the power consumption of the DCM circuit (which is effectively a preamplifier circuit). Taking this into account reduces the overall PAE to 65%, providing a better comparison towards other implementations. A somewhat comparable linear amplifier shown in [3] has a drain efficiency of 27.5% at an output power of −4.2 dBm at f = 1.9 GHz (however, a given drain efficiency will always be higher than the equivalent PAE). Efficiency values for several types of power amplifiers are presented in Table 3. Their efficiency ε varies from 0.19, or 19%, to 0.65, with many common amplifier types showing ε near 0.3. At lower power output, as would be typical in a wireless sensor network, ε may drop even lower. From (22), dCR will change by ε1/n , so assuming a power efficiency of 33% and free space path loss, dCR will be 0.58 times the value obtained assuming ideal power efficiency of 100%. For n = 3, dCR is 0.69 times the ideal power efficiency value of dCR , and for n = 4, dCR is 0.76 times the ideal power efficiency value. If we assume even lower power efficiency of 19%, dCR reduces further to 0.44, 0.57, and 0.66 times its value calculated assuming ideal power efficiency, for n = 2, 3, and 4, respectively. While these values do not drop dCR dramatically, they do bring the n = 4 values at 10 GHz into the range of 3.5 to 7 m, and at 450 MHz to a range of 17 to 32 m, for the 4 most energy-efficient analog decoders with a power efficiency of 19%. Figure 6 shows the changes in dCR obtained assuming ε = 0.33 and 0.19, compared with ideal power efficiency of ε = 1, for the most energy-efficient decoder, the analog (16,11) extended Hamming decoder. At f = 10 GHz, a power efficiency of 33% drops dCR in free space from 30 m to 17 m, and 19% efficiency drops it further to 13 m. This is easily within the distance of one building to another, or from a house to a garage, for an LOS security scenario. With n = 3 and a power efficiency of 33%, dCR falls from 9.5 m to 6.5 m, and to 5.5 m with a power efficiency of 19%. For n = 4 and power efficiency of 33%, dCR is lowered from 5.5 m to 4 m, and power efficiency of 19% lowers it slightly further to 3.5 m. This is less than the distance between rooms in most buildings, making applications where a sensor in one room transmits to a receiver in another room behind it, perhaps for medical applications, practical for ECC using analog decoders at high frequencies.

Sheryl L. Howard et al.

11 Table 3: Comparison of various power amplifier configurations.

Description

Output power

Efficiency

Carrier frequency

−6.0 dBm

19%

900 MHz

Class B

9.8 dBm

38%

433 MHz

Class A/B

2.7 dBm

33%

1.9 GHz

Class E

−4.3 dBm

65%

433 MHz

OOK cascode

−4.2 dBm

27.5%

1.9 GHz

Push-pull linear

Critical distance dCR (m)

104

103

Analog (16,11) EHC n=2

102

n=3 n=4

101

100

109

1010 Frequency (Hz)

n = 2, Eff = 100% n = 2, Eff = 33% n = 2, Eff = 19% n = 3, Eff = 100% n = 3, Eff = 33%

n = 3, Eff = 19% n = 4, Eff = 100% n = 4, Eff = 33% n = 4, Eff = 19%

Figure 6: Estimated critical distance dCR for analog (16,11) extended Hamming decoder assuming 19%, 33%, and 100% power efficiency, for n = 2, 3, and 4.

6.

CONCLUSIONS

In free space line-of-sight scenarios, ECC is not very energyefficient for frequencies below 2 GHz, except for widely spaced outdoor monitoring networks. In an urban outdoor setting, at higher frequencies, ECC can be practical for sensor networks placed between buildings, especially when implemented with analog decoders. For indoor environments, ECC is energy-efficient at high frequencies, for sensors placed at opposite ends of hallways or in adjacent rooms, or on multiple floors or in a dense urban environment at all frequencies. Analog decoders offer the most energy-efficient ECC solution, becoming energy-efficient at distances from 1/4 to 1/2 the critical distances of the digital decoders examined in this paper.

Notes Efficiency figure includes oscillator and frequency divider Includes 3 class A preamplifier stages N/A Uses duty-cycle modulation

Paper reference

N/A

[3]

[12] [14] [59] [58]

The effect of interference from other radiating sources has not been taken into account in this paper. This would reduce dCR values, as the uncoded system must increase power to overcome the interference. The ECC system will thus become more energy-efficient at shorter distances when interference is considered. The analog decoders in general, with their low power consumption, are better suited than digital decoders for the low-power requirements of wireless sensor networks. However, even the analog decoders require distances of 5–10 m (3.5–7 m for 19% power amplifier efficiency) at 10 GHz and n = 4 before they are energy-efficient in terms of the power the decoder consumes compared with the energy saved due to coding gain. Thus, analog decoders may not yet be practical for sensor network applications requiring close spacing of the sensors, such as monitoring patients in a crowded emergency room, babies in a nursery, or multiple sensors on one patient. Again, the effect of interference has not been considered, and in these scenarios where sensors are spaced closely together, interference could well be sufficient to require ECC for reliable operation. The analog decoder critical distances considered for 10 GHz and n = 4 without interference are practical for sensors at ends of a room, or located one per room, such as air quality and temperature/humidity sensors, or sensors transmitting experimental data between university labs, or transmitting patient data during a procedure to equipment in another room. Depending on the application and environment, analog decoders can be energy-efficient when used in a wireless sensor network. A combination of low power consumption and moderately high to high throughput makes analog decoders quite practical for WSN use. ECC is not always a practical solution for increasing link reliability, and as shown by the large critical distance values in free space at lower frequencies, an uncoded system may actually be more energy-efficient in certain environments, for specific applications. But in an office environment for communication between rooms, or a multiple-floor network, or security cameras in adjacent buildings, ECC, especially when implemented with analog decoders, can be a practical method of minimizing energy consumption in the wireless sensor network.

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EURASIP Journal on Wireless Communications and Networking

ACKNOWLEDGMENTS Many thanks to Vincent Gaudet and Chris Winstead, for their helpful comments and suggestions regarding analog decoders and throughput, and to the editor and reviewers for their recommendations to improve the quality of this paper. REFERENCES [1] S. Roundy, B. Otis, Y. H. Chee, J. Rabaey, and P. Wright, “A 1.9GHz RF transmit beacon using environmentally scavenged energy,” in Proceedings of IEEE International Symposium on Low Power Electronics and Devices (ISLPED ’03), Seoul, Korea, August 2003. [2] T.-H. Lin, W. J. Kaiser, and G. J. Pottie, “Integrated low-power communication system design for wireless sensor networks,” IEEE Communications Magazine, vol. 42, no. 12, pp. 142–150, 2004. [3] B. Otis, Y. H. Chee, and J. Rabaey, “A 400 μW-RX, 1.6mW-TX super-regenerative transceiver for wireless sensor networks,” in Proceedings of IEEE International Solid-State Circuits Conference (ISSCC ’05), vol. 1, pp. 396–397, San Francisco, Calif, USA, February 2005. [4] K. Iniewski, C. Siu, S. Kilambi, et al., “Ultra-low-power circuit and system design tradeoffs for smart sensor network applications,” in Proceedings of the International Conference on Information and Communication Technology (ICICT ’05), Cairo, Egypt, December 2005, invited paper. [5] V. Ekanayake, C. Kelly IV, and R. Manohar, “An ultra-lowpower processor for sensor networks,” in Proceedings of the 11th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-XI ’04), Boston, Mass, USA, October 2004. [6] G. K. Ottman, H. F. Hofmann, and G. A. Lesieutre, “Optimized piezoelectric energy harvesting circuit using step-down converter in discontinuous conduction mode,” IEEE Transactions on Power Electronics, vol. 18, no. 2, pp. 696–703, 2003. [7] S. Roundy, D. Steingart, L. Fr´echette, P. K. Wright, and J. Rabaey, “Power sources for wireless sensor networks,” in Proceedings of the 1st European Workshop on Wireless Sensor Networks (EWSN ’04), pp. 1–17, Berlin, Germany, January 2004. [8] W. Ye, J. Heidemann, and D. Estrin, “An energy-efficient MAC protocol for wireless sensor networks,” in Proceedings of 21st International Conference of IEEE Computer and Communications Societies (INFOCOM ’02), vol. 3, pp. 1567–1576, New York, NY, USA, June 2002. [9] K. Sohrabi and G. J. Pottie, “Performance of a novel selforganization protocol for wireless ad-hoc sensor networks,” in Proceedings of IEEE 50th Vehicular Technology Conference (VTC ’99), vol. 2, pp. 1222–1226, Amsterdam, The Netherlands, September 1999. [10] A. Woo and D. Culler, “A transmission control scheme for media access in sensor networks,” in Proceedings of ACM/IEEE International Conference on Mobile Computing and Networking (MOBICOM ’01), Rome, Italy, July 2001. [11] F. Bennett, D. Clarke, J. B. Evans, A. Hopper, A. Jones, and D. Leask, “Piconet: embedded mobile networking,” IEEE Personal Communications, vol. 4, no. 5, pp. 8–15, 1997. [12] A. Molnar, B. Lu, S. Lanzisera, B. W. Cook, and K. S. J. Pister, “An ultra-low power 900 MHz RF transceiver for wireless sensor networks,” in Proceedings of the IEEE on Custom Integrated Circuits Conference (CICC ’04), pp. 401–404, Orlando, Fla, USA, October 2004.

[13] A.-S. Porret, T. Melly, D. Python, C. C. Enz, and E. A. Vittoz, “An ultralow-power UHF transceiver integrated in a standard digital CMOS process: architecture and receiver,” IEEE Journal of Solid-State Circuits, vol. 36, no. 3, pp. 452–466, 2001. [14] T. Melly, A.-S. Porret, C. C. Enz, and E. A. Vittoz, “An ultralow-power UHF transceiver integrated in a standard digital CMOS process: transmitter,” IEEE Journal of Solid-State Circuits, vol. 36, no. 3, pp. 467–472, 2001. [15] P. Lettieri, C. Fragouli, and M. B. Srivastava, “Low power error control for wireless links,” in Proceedings of the 3rd Annual ACM/IEEE International Conference on Mobile Computing and Networking (MOBICOM ’97), pp. 139–150, Budapest, Hungary, September 1997. [16] S. Mukhopadhyay, D. Panigrahi, and S. Dey, “Data aware, low cost error correction for wireless sensor networks,” in Proceedings of IEEE Wireless Communications and Networking Conference (WCNC ’04), vol. 4, pp. 2492–2497, Atlanta, Ga, USA, March 2004. [17] E. Shih, S. Cho, F. S. Lee, B. H. Calhoun, and A. Chandrakasan, “Design considerations for energy-efficient radios in wireless microsensor networks,” Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, vol. 37, no. 1, pp. 77–94, 2004. [18] C. Berrou, A. Glavieux, and P. Thitimajshima, “Near Shannon limit error-correcting coding and decoding: turbo-codes,” in Proceedings of IEEE International Conference on Communications (ICC ’93), vol. 2, pp. 1064–1070, Geneva, Switzerland, May 1993. [19] R. G. Gallager, “Low-density parity-check codes,” IRE Transactions on Information Theory, vol. 8, no. 1, pp. 21–28, 1962. [20] S. Kasnavi, S. Kilambi, B. Crowley, K. Iniewski, and B. Kaminska, “Application of error control codes (ECC) in ultra-lowpower RF transceivers,” in Proceedings of IEEE Dallas Circuits and Systems Workshop (DCAS ’05), Dallas, Tex, USA, September 2005. [21] N. Sadeghi, S. L. Howard, S. Kasnavi, K. Iniewski, V. C. Gaudet, and C. Schlegel, “Analysis of error control code use in ultra-low-power wireless sensor networks,” in Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS ’06), Kos, Greece, May 2006, accepted. [22] C. Schlegel and L. Perez, Trellis and Turbo Coding, IEEE/Wiley, Piscataway, NJ, USA, 2004. [23] B. Sklar, Digital Communications: Fundamentals and Applications, Prentice Hall, Englewood Cliffs, NJ, USA, 1988. [24] W. L. Stutzman and G. A. Thiele, Antenna Theory and Design, John Wiley & Sons, New York, NY, USA, 2nd edition, 1998. [25] T. S. Rappaport, Wireless Communications: Principles and Practice, Prentice Hall, Englewood Cliffs, NJ, USA, 1996. [26] S. Y. Seidel and T. S. Rappaport, “Path loss prediction in multifloored buildings at 914 MHz,” IEE Electronics Letters, vol. 27, no. 15, pp. 1384–1387, 1991. [27] C. Perez-Vega and J. L. Garcia, “A simple approach to a statistical path loss model for indoor communications,” in Proceedings of the 27th European Microwave Conference and Exhibition, pp. 617–623, Jerusalem, Israel, September 1997. [28] G. D. Durgin, T. S. Rappaport, and H. Xu, “Partition-based path loss analysis for in-home and residential areas at 5.85 GHz,” in Proceedings of IEEE Global Telecommunications Conference (GLOBECOM ’98), vol. 2, pp. 904–909, Sydney, NSW, Australia, November 1998. [29] D. B. Green and A. S. Obaidat, “An accurate line of sight propagation performance model for ad-hoc 802.11 wireless LAN (WLAN) devices,” in Proceedings of IEEE International

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Conference on Communications (ICC ’02), vol. 5, pp. 3424– 3428, New York, NY, USA, April-May 2002. J. Hansen and P. E. Leuthold, “The mean received power in ad hoc networks and its dependence on geometrical quantities,” IEEE Transactions on Antennas and Propagation, vol. 51, no. 9, pp. 2413–2419, 2003. D. M. J. Devasirvatham, C. Banerjee, M. J. Krain, and D. A. Rappaport, “Multi-frequency radiowave propagation measurements in the portable radio environment,” in Proccedings of IEEE International Conference on Communications (ICC ’90), vol. 4, pp. 1334–1340, Atlanta, Ga, USA, April 1990. T. J. Harrold, A. R. Nix, and M. A. Beach, “Propagation studies for mobile-to-mobile communications,” in Proceedings of IEEE 54th Vehicular Technology Conference (VTC ’01), vol. 3, pp. 1251–1255, Atlantic City, NJ, USA, October 2001. H. Hashemi, “The indoor radio propagation channel,” Proceedings of the IEEE, vol. 81, no. 7, pp. 941–968, 1993. J. Sydor, “True broadband for the countryside,” IEE Communications Engineer, vol. 2, no. 2, pp. 32–36, 2004. A. Aguiar and J. Gross, “Wireless channel models,” Tech. Rep. TKN-03-007, Telecommunications Networks Group, Technische Universit¨at Berlin, Berlin, Germany, April 2003. R. W. Hamming, “Error detecting and error correcting codes,” The Bell System Technical Journal, vol. 29, no. 2, pp. 147–160, 1950. I. S. Reed and G. Solomon, “Polynomial codes over certain finite fields,” SIAM Journal on Applied Mathematics, vol. 8, pp. 300–304, 1960. R. C. Bose and D. K. Ray-Chaudhuri, “On a class of error correcting binary group codes,” Information and Control, vol. 3, pp. 68–79, 1960. A. Hocquenghem, “Codes correcteurs d’erreurs,” Chiffres, vol. 2, pp. 147–156, 1959. A. J. Viterbi, “Error bounds for convolutional codes and an asymptotically optimum decoding algorithm,” IEEE Transactions on Information Theory, vol. 13, no. 2, pp. 260–269, 1967. L. R. Bahl, J. Cocke, F. Jelinek, and J. Raviv, “Optimal decoding of linear codes for minimizing symbol error rate,” IEEE Transactions on Information Theory, vol. 20, no. 2, pp. 284– 287, 1974. J. Pearl, Probabilistic Reasoning in Intelligent Systems: Networks of Plausible Inference, Morgan Kaufmann, San Mateo, Calif, USA, 1988. N. Wiberg, “Codes and decoding on general graphs,” thesis of Doctor of Philosophy, Link¨oping University, Link¨oping, Sweden, 1996. M. P. C. Fossorier, M. Mihaljevi´c, and H. Imai, “Reduced complexity iterative decoding of low-density parity check codes based on belief propagation,” IEEE Transactions on Communications, vol. 47, no. 5, pp. 673–680, 1999. J. G. Proakis, Digital Communications, McGraw-Hill, New York, NY, USA, 4th edition, 2001. D. Vogrig, A. Gerosa, A. Neviani, A. Graell I Amat, G. Montorsi, and S. Benedetto, “A 0.35-μm CMOS analog turbo decoder for the 40-bit rate 1/3 UMTS channel code,” IEEE Journal of Solid-State Circuits, vol. 40, no. 3, pp. 753–761, 2005. C. Winstead, “Analog Iterative Error Control Decoders,” thesis of Doctor of Philosophy, Department of Electrical & Computer Engineering, University of Alberta, Alberta, Canada, 2004.

13 [48] A. J. Blanksby and C. J. Howland, “A 690-mW 1-Gb/s 1024-b, rate-1/2 low-density parity-check code decoder,” IEEE Journal of Solid-State Circuits, vol. 37, no. 3, pp. 404–412, 2002. [49] J. Rabaey, A. Chandrakasan, and B. Nikolic, Digital Integrated Circuits, Prentice Hall, Englewood Cliffs, NJ, USA, 2nd edition, 2003. [50] T. S. Fill and P. G. Gulak, “An assessment of VLSI and embedded software implementations for Reed-Solomon decoders,” in Proceedings of IEEE Workshop on Signal Processing Systems (SIPS ’02), pp. 99–102, San Diego, Calif, USA, October 2002. [51] C. Winstead, N. Nguyen, V. C. Gaudet, and C. Schlegel, “Lowvoltage CMOS circuits for analog iterative decoders,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 52, no. 4, 2005. [52] M. Kawokgy, C. Andre, and T. Salama, “Low-power asynchronous Viterbi decoder for wireless applications,” in Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED ’04), pp. 286–289, Newport, Calif, USA, August 2004. [53] C.-C. Lin, C.-C. Wu, and C.-Y. Lee, “A low power and high speed Viterbi decoder chip for WLAN applications,” in Proceedings of the 29th European Solid-State Circuits Conference (ESSCIRC ’03), pp. 723–726, Lissabon, Portugal, September 2003. [54] C. Winstead, C. Schlegel, and V. C. Gaudet, “CMOS analog decoder for (256,121) block turbo code,” submitted to EURASIP Journal on Wireless Communications and Networking, special issue: CMOS RF circuits for wireless applications. [55] S. Hemati, A. H. Banihashemi, and C. Plett, “An 80-Mb/s 0.18μm CMOS analog min-sum iterative decoder for a (32,8,10) LDPC code,” in Proceedings of the IEEE Custom Integrated Circuits Conference (CICC ’05), pp. 243–246, San Jose, Calif, USA, September 2005. [56] T. Lee, The Design of CMOS Radio-Frequency Integrated Circuits, Cambridge University Press, Cambridge, UK, 2nd edition, 2004. [57] “Wireless LAN medium access control (MAC) and physical layer (PHY) specification,” LAN MAN Standards Committee, IEEE Computer Society, IEEE, New York, NY, USA, IEEE Std 802.11 - 1997 edition, 1997. [58] D. Aksin, S. Gregori, and F. Maloberti, “High-efficiency power amplifier for wireless sensor networks,” in Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS ’05), vol. 6, pp. 5898–5901, Kobe, Japan, May 2005. [59] Y. H. Chee, J. Rabaey, and A. M. Niknejad, “A class A/B low power amplifier for wireless sensor networks,” in Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS ’04), vol. 4, pp. 409–412, Vancouver, BC, Canada, May 2004. Sheryl L. Howard received the B.S.E.E. degree in 1984 from the University of Utah, Salt Lake City, Utah, and the M.E.E.E. degree in 1988, also from the University of Utah. She is currently working towards the Ph.D. degree in electrical engineering at the University of Alberta, Edmonton, AB, Canada. Her research interests include iterative error control decoding and coding techniques.

14 Christian Schlegel received the Dipl. El. Ing. ETH degree from the Federal Institute of Technology, Zurich, in 1984, and the M.S. and Ph.D. degrees in electrical engineering from the University of Notre Dame, Notre Dame, Ind, in 1986 and 1989. He held academic positions at the University of South Australia, University of Texas, and University of Utah, Salt Lake City. In 2001 he was named iCORE Professor for High-Capacity Digital Communications at the University of Alberta, Canada, a 3million-dollar research program in leading-edge digital communications. His interests are in error control coding and applications, multiple access communications, digital communications, and analog and digital implementations of communications systems. He is the author of Trellis Coding and Trellis and Turbo Coding by IEEE/Wiley, and Coordinated Multiple User Communications, coauthored with Professor Alex Grant. He received a 1997 Career Award, and a Canada Research Chair in 2001. He is an Associate Editor for coding theory and techniques for IEEE Transactions on Communications, and a Guest Editor of the IEEE Proceedings on Turbo Coding. He served as Technical Program Cochair of ITW ’01 and ISIT ’05, and General Chair of CTW ’05, as well as on numerous technical conference program committees. Kris Iniewski is an Associate Professor at the Electrical and Computer Engineering Department of University of Alberta. He is also a President of CMOS Emerging Technologies, Inc., a consulting company in Vancouver. His research interests are in advanced CMOS devices and circuits for ultralow-power wireless systems, medical imaging, and optical networks. From 1995 to 2003, he was with PMC-Sierra and held various technical and management positions in research & development and strategic marketing. Prior to joining PMC-Sierra, from 1990 to 1994, he was an Assistant Professor at the University of Toronto’s Electrical and Computer Engineering Department. He has published over 80 research papers in international journals and conferences. He holds 18 international patents granted in USA, Canada, France, Germany, and Japan. He is a frequent invited speaker and consults for multiple organizations internationally. He received his Ph.D. degree in electronics (with honors) from the Warsaw University of Technology (Warsaw, Poland) in 1988. Together with Carl McCrosky and Dan Minoli he is an author of Data Networks-VLSI and Optical Fibre (Wiley, 2006) and editor of Emerging Wireless Technologies (CRC Press, 2006).

EURASIP Journal on Wireless Communications and Networking

Hindawi Publishing Corporation EURASIP Journal on Wireless Communications and Networking Volume 2006, Article ID 62905, Pages 1–14 DOI 10.1155/WCN/2006/62905

Charge-Domain Signal Processing of Direct RF Sampling Mixer with Discrete-Time Filters in Bluetooth and GSM Receivers Yo-Chuol Ho, Robert Bogdan Staszewski, Khurram Muhammad, Chih-Ming Hung, Dirk Leipold, and Kenneth Maggio Wireless Analog Technology Center, Texas Instruments Inc., Dallas, TX 75243, USA Received 15 October 2005; Revised 13 March 2006; Accepted 13 March 2006 RF circuits for multi-GHz frequencies have recently migrated to low-cost digital deep-submicron CMOS processes. Unfortunately, this process environment, which is optimized only for digital logic and SRAM memory, is extremely unfriendly for conventional analog and RF designs. We present fundamental techniques recently developed that transform the RF and analog circuit design complexity to digitally intensive domain for a wireless RF transceiver, so that it enjoys benefits of digital and switched-capacitor approaches. Direct RF sampling techniques allow great flexibility in reconfigurable radio design. Digital signal processing concepts are used to help relieve analog design complexity, allowing one to reduce cost and power consumption in a reconfigurable design environment. The ideas presented have been used in Texas Instruments to develop two generations of commercial digital RF processors: a single-chip Bluetooth radio and a single-chip GSM radio. We further present details of the RF receiver front end for a GSM radio realized in a 90-nm digital CMOS technology. The circuit consisting of low-noise amplifier, transconductance amplifier, and switching mixer offers 32.5 dB dynamic range with digitally configurable voltage gain of 40 dB down to 7.5 dB. A series of decimation and discrete-time filtering follows the mixer and performs a highly linear second-order lowpass filtering to reject close-in interferers. The front-end gains can be configured with an automatic gain control to select an optimal setting to form a trade-off between noise figure and linearity and to compensate the process and temperature variations. Even under the digital switching activity, noise figure at the 40 dB maximum gain is 1.8 dB and +50 dBm IIP2 at the 34 dB gain. The variation of the input matching versus multiple gains is less than 1 dB. The circuit in total occupies 3.1 mm2 . The LNA, TA, and mixer consume less than 15.3 mA at a supply voltage of 1.4 V. Copyright © 2006 Yo-Chuol Ho et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

1.

INTRODUCTION

The continuous technology innovation in CMOS forces to integrate more circuits resulting in lower solution price while offering more features [1]. Designing a radio for the wireless and cellular standards with large digital circuitry, such as digital baseband (DBB), application processor, and memory on the same chip becomes a challenging task due to the coupling of the digital spurious noise through silicon substrate, interconnect, and package [2]. While high level of integration impedes achieving a low noise figure, low supply voltage makes linearity hard to achieve. Recently, we have demonstrated a highly integrated system-on-chip (SoC) in the discrete-time Bluetooth receiver. The receiver architecture [3–6] uses direct RF sampling in the receiver front-end path. In the past, only subsampling mixer receiver architectures have been demonstrated: they operate at lower IF frequencies [7, 8] and suffer from noise folding and exhibit susceptibility to clock jitter. In this architecture,

discrete-time analog signal processing is used to sample the RF input signal as it is down-converted, down-sampled, filtered, and converted from analog to digital with a discretetime ΣΔ ADC. This method achieves great selectivity right at the mixer level. The selectivity is digitally controlled by the LO clock frequency and capacitance ratio, both of which are extremely precise in deep-submicron CMOS processes. The discrete-time filtering at each signal processing stage is followed by successive decimation. The main philosophy in architecting the receive path is to provide all the filtering required by the standard as early as possible using a structure that is quite amenable to migration to the more advanced deep-submicron processes. This approach significantly relaxes the design requirements for the following baseband amplifiers. In this paper, we also present a 90-nm CMOS realization of a GSM receiver [9–11] RF front end incorporating the discrete-time signal processing. The RF front end provides an embedded variable gain amplifier (VGA) function

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EURASIP Journal on Wireless Communications and Networking

gm

gm

gm iRF

iRF

iRF N

LO+

LO

LO

LO+

LO−

LOA

LO−

LOB

LOB Cs+

Cs (a)

LOA

Cs−

Cs

Cs

(b)

Figure 1: Temporal MA operation at RF rate: (a) single-ended, (b) pseudodifferential configurations.

Figure 2: Temporal MA operation at RF rate with cyclic charge readout.

that is digitally configurable and offers fine gain control. The switched capacitor filter (SCF) implements a highly-linear second-order lowpass filter. The input S11 is constant over the desired frequency range while achieving 1.8 dB noise figure (NF) in the highest gain setting of 40 dB where the RF front-end circuits consume only 15.3 mA. The gain can be configured with an automatic-gain-control algorithm in the receiver to select an optimal setting with a trade-off between noise figure and linearity and to compensate for process and temperature variations. The objective is to realize a receiver front-end circuit with adjustable lowpass filters that is small in size while enabling the software-defined radio (SDR) of the future. The organization of this paper is as follows. Section 2 presents discrete-time signal processing of the RF front-end mixer with an emphasis on Bluetooth examples. Section 3 describes a specific implementation of the described techniques and concepts in a GSM front-end radio. Silicon realization of the Bluetooth and GSM radios is presented in Section 4. Performance of the GSM front-end receiver is shown in Section 6.

and the accumulated charge on the sampling capacitor is

2. 2.1.

DISCRETE-TIME OPERATION Direct sampling mixer

The basic idea of the current-mode direct sampling mixer [3, 4] is illustrated in Figure 1(a). The low-noise transconductance amplifier (LNTA) converts the received RF voltage vRF into iRF in current domain through the transconductance gain gm . The current iRF gets switched by the half-cycle of the local oscillator (LO) and integrated into the sampling capacitor Cs . Since it is difficult to switch the current at RF rate, it could be merely redirected to an identical sampler that is operating on the opposite half-cycle of the LO clock, as shown in Figure 1(b) for a pseudodifferential configuration. If the LO oscillating at f0 frequency is synchronous and in phase with the sinusoidal RF waveform, the voltage gain of a single RF half-cycle is Gv,RF =

1 1 gm · · π f 0 Cs

(1)

Gq,RF =

1 1 · · gm . π f0

(2)

In the above equations, the 1/π factor is contributed by the half-cycle sinusoidal integration. As an example, if gm = 30 mS, Cs = 15.925 pF, and f0 = 2.4 GHz, then Gv,RF = 0.25. 2.2.

Temporal moving average

Continuously accumulating the charge as shown in Figure 1 is not very practical if it cannot be read out. In addition, a mechanism to prevent the charge overflow is needed. Both of these operations are accomplished by fixing the integration window length followed by charge readout phase that will also discharge the sampling capacitor such that the next period of integration would start from the same zero condition. The RF sampling and readout operations are cyclically rotated on both Cs capacitors as shown in Figure 2. When LOA rectifies N RF cycles that are being integrated on the first sampling capacitor, LOB is off and the second sampling capacitor charge is being read out. On the following N RF cycles the operation is reversed. This way, the charge integration and readout occur at the same time and no RF cycles are missed. The sampling capacitor integrates the half-rectified RF current over N cycles. The charge accumulated on the sampling capacitor and the resulting voltage (V = Q/Cs ) increases with the integration window, thus giving rise to a discrete signal processing gain of N. The temporal integration of N half-rectified RF samples performs a finite-impulse response (FIR) operation with N all-one coefficients, also known as moving-average (MA), according to the equation wi =

N −1

ui−l ,

(3)

l=0

where ui is the ith RF sample of the input charge sample, wi is the accumulated charge. Since the charge accumulation is done on the same capacitor, this formula could also be used

Yo-Chuol Ho et al.

3

Frequency response of the temporal MA filters

20

Voltage gain (dB)

10 0 −10 −20 −30 −40

0

200

400

600

800

1000

1200

Frequency (MHz) MA7 @RF MA8 @RF MA9 @RF

Figure 3: Transfer function of the temporal MA operation at RF rate.

in the voltage domain. Its frequency response is a sinc function and is shown in Figure 3 for N = 8 (solid line) and N = 7, 9 (dotted lines) with sampling rate f0 = 2.4 GHz. It should be noted that this filtering is done on the same capacitor in time domain resulting in a most faithful reproduction of the transfer function. Due to the fact that the MA output is being read out at the lower rate of N RF clock cycles, there is an additional aliasing with foldover frequency at f0 /2N and located halfway to the first notch. Consequently, the frequency response of MA = 7 with decimation of 7 exhibits less aliasing and features wider notches than MA = 8 or MA = 9 with decimation of 8 or 9, respectively. It should be emphasized that the voltage Gv and charge Gq signal processing gains of the temporal moving average (TMA) (followed by decimation) are merely due to the sampling time interval expansion of this discrete-time system (the sampling rate of the input is at the RF frequency): Gv,tma = Gq,tma = N. In the following analysis, the RF half-cycle integration voltage gain of gm /πCs f0 is tracked separately. Since this gain depends on the absolute physical parameters of usually low tolerance (gm value of the preceding LNTA stage and the total integrating capacitance of the sampling mixer), it is advantageous to keep it decoupled from the discrete signal processing gain of the MTDSM. 2.3. High-rate IIR filtering Figure 2 is now modified to include recursive operation that gives rise to the IIR filtering capability, which is generally considered stronger than that of FIR.

A “history” sampling capacitor CH is added in Figure 4. The integration operation is continually performed on the “history” capacitor CH = a1 Cs and one of the two rotating “charge-and-readout” capacitors CR = (1 − a1 )Cs such that the total RF integrating capacitance, as seen by the LNTA, is always CH + CR = Cs . When one of the CR capacitors is being used for readout, the other is being used for RF integration. The IIR filtering capability comes into play in the following way. The RF current is being integrated over N RF cycles, as described before. This time, the charge is being shared on both CH and CR capacitors proportionately to their capacitance values. At the end of the accumulation cycle, the active CR capacitor, that stores (1 − a1 ) of the total charge, stops further accumulating in preparation for charge readout. The other rotating capacitor joins the CH capacitor in the RF sampling process and, at the same time, obtains (1 − a1 )/(a1 + (1 − a1 )) = 1 − a1 of the total remaining charge in the “history” capacitor, provided it has no initial charge at the time of commutation. Thus the system retains a1 portion of the total system charge of the previous cycle. If the input charge accumulated over the most recent N RF samples is w j , then the charge s j stored in the system at sampling time j, where i = N · j (as stated earlier, i is the RF cycle index) could be described as a single-pole recursive IIR equation: s j = a1 s j −1 + w j , 



x j = 1 − a1 s j −1 , a1 =

CH . C H + CR

(4) (5) (6)

The output charge x j is (1 − a1 ) of the system charge in the most recent cycle. This discrete-time IIR filter operates at f0 /N sampling rate and introduces a single pole with the frequency attenuation of 20 dB/dec. The equivalent pole location in the continuous-time domain for fc1  f0 /N is fc1 =

 1 f0  1 f0 CR · 1 − a1 = · . 2π N 2π N CH + CR

(7)

Since there is no sampling time expansion for the IIR operation, the discrete signal processing charge gain is one. In other words, due to the charge conservation principle, the input charge per sample interval is on average the same as the output charge. For the voltage gain, however, there is an impedance transformation of Cinput = Cs and Coutput = (1 − a1 )Cs , thus resulting in a gain:

Gv,iir1

Gq,iir1 = 1, 1 C H + CR = = . 1 − a1 CR

(8)

As an example, the IIR filtering with a single coefficient of a1 = 0.9686, placing the pole at fc1 = 1.5 MHz (CR = 0.5 pF, CH = 15.425 pF) is performed at f0 /N = 2.4 GHz/8 = 300 MHz sampling rate and it follows the FIR MA = 8 filtering of the input at f0 RF sampling rate. The voltage gain of the high-rate IIR filter is 31.85 (30.06 dB).

4

EURASIP Journal on Wireless Communications and Networking iRF

gm

LO

N LO SA

SA

SAZ

SAZ

CH = a1 Cs

CR = CR = (1 − a1 )Cs (1 − a1 )Cs

Figure 4: IIR operation with cyclic charge readout.

2.4. Additional spatial MA filtering zeros

iRF

For practical reasons, it is difficult to read out the x j output charge of Figure 4 at f0 /N = 300 MHz rate. The output charge readout time is extended M = 4 times by adding redundancy of four to each of the two original CR capacitors as shown in Figure 5. The input charge is cyclically integrated within the group of four CR capacitors. Adding the redundant capacitors gives rise to an additional antialiasing filtering just before the second decimation of M. This could also be considered as equivalent to adding additional M − 1 zeros to the IIR transfer function in (4). After the first bank of four capacitors gets charged (SA1 − SA4 in Figure 5), the second bank (SB1 − SB4 ) is in the process of being charged and the charge on first bank of capacitors are summed and read out (RA ). Physically connecting together the four capacitors performs an FIR filtering described as the spatial moving average of M = 4: yk =

M −1 

xk−l ,

(9)

gm

LO SA1

SA2

SA3

SA4

CR

CR

CR

SB1 CR CH

SB2 CR

SB3 CR

SB4 CR

CR

S0 SA1 SA2 SA3 SA4 RA SB1 SB2 SB3 SB4 RB

Figure 5: IIR operation with additional FIR filtering. The readout and reset circuitry is not shown.

l=0

where yk is the output charge and sampling time index j = M · k. RA and RB in Figure 5 are the readout/reset cycles during which the output charge on the four nonsampling capacitors is transferred out and the remnant charge is reset before the capacitors are put back into the sampling operation. It should be noted that after the reset phase, but before the sampling phase, the capacitors are unobtrusively precharged [5] in order to implement a dc-offset cancellation or to accomplish a feedback summation for the ΣΔ loop operation. Since the charge of four capacitors is added, there is a charge gain of M = 4 and a voltage gain of 1. Again, as explained before, the charge gain is due to the sampling interval expansion: Gq,sma = M and Gv,sma = 1. Figure 6 shows frequency response of the temporal moving average with a decimation of 8 (Gv = 18.06 dB), the IIR filter operating at RF/8 rate (Gv = 30.06 dB), and the spatial moving average filter operating at RF/32 rate (Gv = 0 dB) with a decimation of 4. The solid line is the composite transfer function with the dc gain of Gv = 48.12 dB. The first decimation of N = 8 reveals itself as aliasing. It should be noted

that it is possible to avoid aliasing of a very strong interferer into the critical IF band by simply changing the decimation ratio N. This brings out advantages of integrating RF/analog with digital circuitry by opening new avenues of novel signal processing solutions not possible before. 2.5.

Lower-rate IIR filtering

The voltage stored on the rotating capacitors cannot be readily presented to the MTDSM block output without an active buffer that would isolate the high impedance of the mixer from the required low driving impedance of the output. Figure 7 shows the mechanism to realize the second, lowerrate, IIR filtering through passive charge sharing. The active element, the operational amplifier, does not actually take part in the IIR filtering process. It is merely used to sense voltage of the buffer feedback capacitor CB and present it to the output with a low driving impedance. Figure 7 additionally suggests possibility of differentially combining, through the

Yo-Chuol Ho et al.

5 The charge “lost” or reflected back into the M · CR capacitor for subsequent reset is (1 − a2 )(zk−1 + yk ). Due to charge conservation principle, the time-averaged values of charge input, yk , and charge leaked out, (1 − a2 )(zk−1 + yk ), should be equal. As stated before, the leak-out charge is not the output from the signal processing standpoint. It should be noted that the amplifier does not contribute to the net charge change of the system and, consequently, the only path of the charge loss is through the same M · CR capacitors being reset after the dumping phase. The output charge zk stops at the IIR-2 stage and does not further propagate, therefore it is of less importance for signal processing analysis. The charge discrete signal processing gain of the second IIR stage is

Frequency response of the temporal MA8, IIR−1, and spatial MA4 filters

50 40

Voltage gain (dB)

30 20 10 0 −10 −20 −30 −40

0

200

400

600

800

1000

1200

Frequency (MHz) MA8 @RF IIR @RF/8: a1 = −0.9686 Composite after MA4 @RF/32

Gv,iir2 = 1.

Figure 6: Transfer functions of the temporal MA filter and the IIR filter operating at RF/8 rate. The solid line is the composite transfer at the output of the spatial MA filter.

operational amplifier, the opposite (180 degree apart) processing path. The charge yk accumulated on the M = 4 rotating capacitors is being shared during the dumping phase with the buffer capacitor CB . At the end of the dumping phase, the M · CR capacitors get disconnected from the second IIR filter and their charge reset before they could be reengaged in the MTDSM operation of Figure 5. This charge loss mechanism gives rise to IIR filtering. If the input charge is yk , then the charge zk stored in the buffer capacitor CB at sampling time k is 



zk = a2 zk−1 + yk = a2 zk−1 + a2 yk , CB . a2 = CB + MCR

(10) (11)

Equation (10) describes a single-pole IIR filter with coefficient a2 and input yk scaled by a2 , where a2 corresponds to the storage-to-total capacitance ratio CB /(CB + MCR ). Conversely, due to the linearity property, it could also be thought of as an IIR filter with input yk and output scaled by a2 . This discrete-time IIR filter operates at f0 /NM sampling rate and introduces a single pole with the frequency transfer function attenuation of 20 dB/dec. The equivalent pole location in the continuous-time domain for fc2  f0 /(NM) is fc2 =

 1 f0  1 f0 MCR · 1 − a2 = · . 2π NM 2π NM CB + MCR

a2 CB = . (13) 1 − a2 MCR The input/output impedance transformation is MCR /CB . Consequently, the voltage gain of IIR-2 is unity: Gq,iir2 =

(12)

The actual MTDSM output is the voltage sensed on the buffer feedback capacitor zk /CB . The previously used charge stream model cannot be directly applied here because the “output” charge zk is not the one that leaves the system.

2.6.

(14)

Cascaded MTDSM filtering

The cascaded discrete signal processing gain equations of the MTDSM mixer are Gq,dsp = Gq,tma · Gq,iir1 · Gq,sma · Gq,iir2 CB =N ·1·M· MCR NCB = , CR (15) Gv,dsp = Gv,tma · Gv,iir1 · Gv,sma · Gv,iir2 C H + CR =N· ·1·1 CR   N C H + CR = . CR Including the RF half-cycle integration (1) and (2), the total single-ended gain is Gq,tot = Gq,RF · Gq,dsp 1 1 = · · gm , π f0 /N Gv,tot = Gv,RF · Gv,dsp gm 1 1 = · · . π f0 /N CR

(16)

(17)

Note the similarity between (17) and (1). In both cases, the term Rsc = 1/ fs Cs is an equivalent resistance of a switched capacitor Cs sampling at rate fs . For example, if fs = 300 MHz and CR = 0.5 pF, then the equivalent resistance is Rsc = 6.7 kΩ. Since the MTDSM output is differential, the gain values in the above equations are actually doubled. The dc-frequency gain Gv,tot in (17) requires further elaboration. The gain depends only on the gm of the LNTA stage, rotating capacitor value, and the rotation frequency. Amazingly, it does not depend on the other capacitor values, which contribute only to the filtering transfer function at higher frequencies.

6

EURASIP Journal on Wireless Communications and Networking

−

D

MTDSM output

Qoutput +

Qinput M∗C

CB

R

Figure 7: Second IIR filter. 2.4 GHz

300 MHz FIR

ui

MA = 8

From LNTA (Temporal) Gq = N = 8 Gv = N = 8

wj 8

IIR-1 1/(1 − a1 )

75 MHz xj

FIR MA = 4

yk 4

IIR-2 1/(1 − a2 )

(Spatial) Gq = 1 Gv = 1/(1 − a1 )

Gq = M = 4 Gv = 1

zk To buffer

Gq = a2 /(1 − a2 ) Gv = 1

Figure 8: Discrete signal processing in the MTDSM.

2.7. Near-frequency interferer attenuation Most of the lower-frequency filtering could be realistically done only with the first and second IIR filters. The two FIR filters do not have appreciable filtering capability at low frequencies and are mainly used for antialiasing. It should be noted that the best filtering could be accomplished by making 3-dB corner frequencies of both IIR filters the same and placing them as close to the higher end of signal band as possible: fc1 = fc2 .

(18)

This gives the following constraint: CB = CH − (M − 1)CR .

are a1 = 0.9686 and a2 = 0.8744. The dc-frequency gains are Gv,iir1 = 31.85 and Gv,iir2 = 1. The transfer function of these IIR filters is shown in Figure 9. The spatial MA = 4, which follows IIR-1, does not appreciably contribute to filtering at lower frequencies but serves as an antialiasing filter for the lower-rate IIR-2. Since the 3-dB point of IIR-2 is slightly corrupted by the discrete-time approximation, the composite attenuation at the cut-off frequencies fc1 = fc2 = 1.5 MHz is about 5.5 dB. The attenuation drops to 13 dB at 3 MHz. Within the 1 MHz band of interest, there is a 3- dB signal attenuation. For the most optimal detector operation, this in-band filtering should be taken into consideration in the matched-filter design. Figure 10 shows the phase response of the above structure versus the ideal constant group delay.

(19) 2.9.

2.8. Signal processing example Figure 8 shows the block diagram from the signal processing standpoint for our specific implementation of f0 = 2.4 GHz, N = 8, M = 4. The following equations describe the timedomain signal processing: (3) for wi , (4) and (5) for x j , (9) for yk , and (10) for zk . The first aliasing frequency (at f0 /N = 300 MHz) is partially protected by the first notch of the temporal MA = 8 filter. However, for higher-order aliasing and overall system robustness, it has to be protected with a truly continuous-time filter, such as an antenna filter. A typical low-cost Bluetoothband duplexer can attenuate up to 40 dB at 300 MHz offset. For the above system with an aggressive cut-off frequency of fc1 = fc2 = 1.5 MHz, using CR = 0.5 pF will result in a dc-frequency voltage gain of 63.66 or 36 dB (17) and the required capacitance is CH = 15.425 pF (7) and CB = 13.925 pF (12). The z-domain coefficients of the IIR filters

MTDSM feedback path

The MTDSM feedback correction could be unobtrusively injected into either group of the four rotating capacitors of Figure 5 when they are not in the active sampling state. This way, the main signal path is not perturbed. The feedback correction is accomplished through charge injection/equalization between the “feedback capacitor” CF and the rotating capacitors CR in the MTDSM structure by shorting all of them together after the CR group of capacitors gets reset, but before they are put back to the sampling system. The feedback charge accumulation structure is shown in Figure 11. Each feedback capacitor CF is associated with one of the two rotating capacitors of group “A” and “B.” The two groups commutate the charging process. Voltage on the feedback capacitor can be calculated as follows. Charging the feedback capacitor CF with the current ifbck for the duration of T will result in incremental accumulation of ΔQin = ifbck · T charge. This charge gets

Yo-Chuol Ho et al.

7 Frequency response of the IIR filters

40

30

30

25 Voltage gain (dB)

Voltage gain (dB)

20 10 0 −10

20 15 10 5

−20

0

−30

−5

−40

Frequency response of the IIR filters

35

0

1

2

3

4

5

6

7

Frequency (Hz) IIR1 @RF/8, a1 = 0.9686 MA4 @RF/8

−10

×107

IIR2 @RF/32, a2 = 0.8744 Cascaded

0

0.5

1

1.5 2 Frequency (Hz)

IIR1 @RF/8, a1 = 0.9686 MA4 @RF/8

(a)

2.5

3 ×106

IIR2 @RF/32, a2 = 0.8744 Cascaded

(b)

Figure 9: Transfer functions of the IIR filters with two poles at 1.5 MHz (bottom zoomed).

Frequency response of the IIR filters

ifbck

0 −0.5

FA

FB

Phase (rad)

−1

SAZ

−1.5

(A)

M ∗ CR

−2

R (reset)

SBZ

PA

PB

(B)

M ∗ CR

(A)

CF

(B)

CF

−2.5

Figure 11: Feedback into the rotating capacitors.

−3

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

Frequency (Hz)

5 ×106

Figure 10: Phase response of the IIR filters with two poles at 1.5 MHz.

added to the total charge QF (k) of the feedback capacitor at the kth time instance: QF (k) = QF (k − 1) + ΔQin = QF (k − 1) + ifbck · T.

(20)

During the charge distribution moment, the feedback capacitor gets connected with the previously reset group of rotating capacitors M · CR . The charge depleted from CF is dependent on the relative capacitor values: ΔQout (k) =

MCR QF (k). CF + MCR

The charge transferred to the rotating capacitors is proportional to the total accumulated charge QF or voltage on the feedback capacitor VF = QF /CF . At first, the accumulated charge is small, so the outgoing charge is small. Since the incoming charge is constant, the QF charge will continue accumulating until the net charge intake becomes zero. Equilibrium is reached when ΔQin (k) = ΔQout (k):

(21)

ifbck · T =

MCR QF (k). CF + MCR

(22)

Transformation of the above gives the equilibrium voltage: VF,eq = ifbck · T ·

CF + MCR . CF · MCR

(23)

8

EURASIP Journal on Wireless Communications and Networking Out P

I-channel LPF

SCF

Rtank

SOUT I

Ctune

Ltank

TA

VDD

LNA

LO-I DCO LO-Q

EN1

ADPLL DCU

LPF

SCF

TA

EN1B

EN2

EN2B

SOUT Q IN P

MN1P

MN2P

Q-channel LS

Figure 12: Receiver front-end diagram.

VSS

Figure 13: LNA core schematic.

The ΔQout,eq charge transfer into the rotating capacitors at equilibrium will create voltage on the bank of rotating capacitors: i ·T VR = fbck . MCR

(24)

As shown in Section 2.5, the voltage transfer function from the rotating capacitors to the history capacitor is unity. Therefore, the bias voltage developed on CH is i ·T . VH = fbck MCR 3.

5

(25)

A GSM RECEIVER FRONT-END ARCHITECTURE

The receiver front end is shown in Figure 12 and consists of an LNA followed by two transconductance amplifiers (TAs) and two passive mixers. The RF input signal is amplified by the LNA and splits into I/Q paths where it is further amplified in the TA. It is then down-converted to a low intermediate frequency (IF) that is fully programmable (but defaults to 100 kHz) by the following mixers driven by an integrated local oscillator (LO). The IF signal is sampled and lowpass-filtered by passing through the switched-capacitor filter (SCF). The LO signals are generated using an all-digital PLL (ADPLL) [12] that incorporates a digitally controlled oscillator (DCO). The digital control unit (DCU) provides all the clocks for the SCF operation. Although the front-end circuit requires two TAs, two mixers, and quadrature LO signals, the receiver has an excellent sensitivity and good linearity at a low supply voltage (VDD ) of 1.4 V thus offering excellent performance that satisfies the GSM requirements. The power is supplied by an integrated low-drop-out (LDO) regulator. 3.1. Low-noise amplifier A differential LNA is implemented to improve noise figure which could be degraded by substrate coupling originating from DBB since the impact of the switching noise of more than a million digital gates on the same silicon die could not have been known precisely. Figure 13 shows a simplified schematic diagram of the LNA. A variable gain feature with seven digitally configurable steps is implemented. In the

4 3 Q 2 1 0 0E + 00

5E + 08

1E + 09

1.5E + 09

2E + 09

2.5E + 09

Frequency (Hz)

Figure 14: Inductor Q-factor.

high-gain mode, four voltage gains are realized with a 2- dB step between 21 dB and 29 dB. In the low-gain mode, there are three gain steps with a 2- dB step between 3 dB and 9 dB. As shown in Figure 13, the multiple cascode stages are connected in parallel with one source degeneration inductor and one inductive load. Each stage has digital configurability. The top transistors of the cascode stage used for bypassing gain contribution are shunted to VDD . Since the bottom transistors of the cascode stage operate in all gain settings, the input impedance is constant to the first order over gain selections, which is critical for constant input power and noise matching. Inductive source degeneration using package bond wires is implemented to improve linearity. The LNA load is an on-chip spiral inductor using multiple metal layers with metal width = 5.9 μm, metal space = 2 μm, inner diameter = 81.9 μm, and 10 turns. This inductor is drawn as a center-tap configuration for better matching between the differential branches and achieving a higher quality factor (Q). As shown in Figure 14, the inductance is 8.9 nH and Q is > 4 at 900 MHz, where Q is defined as |imag(y11)/real(y11)|. To reduce the substrate effect, all doping under the inductor is blocked to preserve a higher resistivity.

Yo-Chuol Ho et al.

9 Transconductance amplifier VDD VFB

Mixer LO+

VFB

CH Rload

IF+ LO−

VCM IF− CH

Vgs

Vgs VSS

RF+

LO+

RF−

Figure 15: TA and mixer core schematic.

The inductor is tuned with the capacitance at the LNA load which comprises tuning capacitors together with parasitics. The tuning capacitor is realized using metal-insulatormetal (MIM) capacitors and switches. Two capacitors are connected differentially with a switch and two pull-down transistors to keep both source/drain voltages of the switch low and Q of the capacitor bank high. The achieved effective Q is 100 at 900 MHz. When the switch is turned off to be in a low capacitance value, the parasitic capacitance of the MIM capacitors and transistors still has an effective Q of about 100. Compared to MOS capacitor, MIM capacitor provides a much better trade-off between Q and CON /COFF ratio. In this design, a CON /COFF ratio of larger than 4 was achieved while Q is still greater than 100. The selectable capacitance ranges 2.5 pF in total because in this process, MIM capacitance can vary up to +/ − 20% from its nominal value. With this design, all GSM bands can be fully covered. The differential LNA draws 7.3 mA. The LNA input is protected against ESD by one reverse-biased diode to VDD and three forward-biased diodes in series to VSS . ESD structures at LNA input are aimed to protect larger than 2 kV human body model (HBM). The LNA bond pad is shielded with lower metal-1 layer to eliminate the substrate coupling while minimizing parasitic capacitance which is about 100 fF. 3.2. TA and mixer Figure 15 shows a simplified TA and mixer schematic diagram. A highly efficient push-pull amplifier is chosen for the TA because of its low noise and good linearity characteristics. The variable gain feature is implemented in the TA with a 3-bit control. A feedback amplifier is used to set the dc bias voltage of the TA output node to VREF which is set to half of VDD so as to provide maximum signal swing. Resistors in Figure 15 are large enough to prevent significant RF signal loading. The differential TA draws 4 mA in the maximum gain mode. A double-balanced switching mixer is connected to the TA output via ac-coupling capacitors so that the dc voltage at the TA output is isolated from the mixer. This topology has an excellent feature of reduced 1/f noise because there is

no dc current flowing through making it suitable for directconversion or near-zero IF receivers. By adding a capacitive load (CH , history capacitor) to the mixer output, lowpass filtering can be obtained to reduce large interferers. In this mixer, two switches are toggled by one of the complementary LO signals (LO+, LO−) from a digitally controlled oscillator (DCO). Since the mixer is connected to the switched capacitor filter (SCF), its loading effect can be represented as Rload which is about 4.5 kΩ. 3.3.

SCF

The schematic diagram of the switched capacitor filter block (SCF) is shown in Figure 16. The switches are controlled by the digital control unit (DCU) that generates the timing waveforms shown in Figure 17. For one LO cycle, the RF signal of the mixer output is integrated into a history capacitor (CH ) and a rotating capacitor (CR1 ). Since the four rotating capacitors sequentially connect to CH in a fixed order, the charge transfer via CR1 is a direct sampling of IF signal. It is also clear that a charge loss on CH through CR1 creates the loading (Rload ) to the mixer output. For two LO cycles, two rotating capacitors in the first bank sample the IF signal on CH while the rotating capacitors in the second bank and CB1 share charge. Because of the half sampling rate from the mixer output to CB1 , the decimation operation creates a sinc function that has notches at the foldover frequencies, NLO/2, where N is a positive integer. Transconductance (gm ) of TA, CH and the loading (Rload ) of SCF create the first IIR filtering response of gm -C antialiasing lowpass filtering prior to the main sinc filter. However, the TA sees a periodic constant load at its output. After the two CR1 capacitors in one bank are disconnected from CH , these carry the charge of past 2 IF samples created by the charge sharing between two CR1 and CH . Next, the two CR1 capacitors share charge with the buffer capacitor CB1 and a second rotating capacitor, CR2 . The overall effect is to create a second IIR filtering stage in which 2CR1 delivers input, CB1 holds the memory, and CR2 captures a glimpse of the output of the second IIR filter stage. This charge is subsequently shared with a second buffer capacitor, CB2 , resulting

10

EURASIP Journal on Wireless Communications and Networking SB

SA SA

IF+ S[0]

D

S[2]

S[3] IF−

RA

CR2 CB1

RB

CR2

PB

SB FP

FB-DAC

CR2

RB

PB

SDM FM CR2

SB D

CB2

SA

VREF

SA SB CR1 SB SB CR1

CR2

SOUT+

SA

CR1

SB

CR2

PA

SB

CR1 SA SA

S[1]

CR2

D

SB SA

RA

PA

CR2

SA

SA SB

CB2 D

SOUT−

Figure 16: SCF core schematic.

1Ts LO+ LO− S[0] S[1] S[2] S[3] SA

(FB-DAC) provided by a sigma-delta modulator that connects the output of a low-noise feedback voltage reference to CR2 . Zero DAC code produces approximately 50% duty cycle at FM and FP clocks which brings the common mode voltage of the SCF exactly at half of VREF . In the presence of a dc offset, the duty cycle is changed with sigma-delta noise shaping to cancel the offset voltage. 3.4.

SB D RA RB PA PB FM FP

Figure 17: DCU clock diagram.

in the third IIR filter stage. While charge samples are passed on from the CH to CB2 through a series of charge combination, splitting and recombination operations, the IF information at mixer output are always kept on CH together with two CR1 capacitors from one bank. The three IIR filters have corner frequencies that are given by respective ratios of rotating capacitors (CR1 , CR2 ) to fixed capacitors (CH , CB1 , CB2 ) and may be readjusted by changing the size of the capacitors. The capacitor ratios in the SCF are programmable which allows the filter corner frequency to be adjustable over a wide range, thereby allowing its use in a multistandard environment. After the charge sharing of CR2 with CB2 , CR2 is reset (RA, RB) and precharged (PA, PB) by the 1-bit feedback circuit

DCO

A DCO circuit schematic is shown in Figure 18 [12]. L1A and L1B are two halves of a center-tap inductor. Because of the shortcoming of this 90-nm digital CMOS Cu process which has thin metal interconnects, it is difficult to design an inductor with even a moderate Q. To enhance the Q of the inductor, an Al layer is patterned and connected in parallel with the Cu windings. M3-5 plus the Al layer were used to form L1 while only M3-5 layers were used for L0. The total Cu and Al thickness are only 0.75 μm and 1.0 μm, respectively. The simulated single-ended Q using an imag(y11)/real(y11) definition is 3.6 and 6.7 at 0.9 and 3.6 GHz, respectively. The differential phase stability Q is 3.6 and 10.2 at 0.9 and 3.6 GHz, respectively [13]. The varactor is implemented using an npoly-nwell MOSCAP structure. Extrapolating from measurement data, the Cmax/Cmin ratio is > 3 within the ranges of desired gate length Lg and gate width Wg per finger. The resulting total tolerable fixed parasitic capacitance is 720 fF. MOSCAP was chosen because the gate oxide thickness (tox) is one of the best controlled parameters in this CMOS process, whose corner variation is within +/ − 2.5%. The four different phases of LO driving the I- and Q-mixers in Figure 15 are generated from the DCO frequency which oscillates at 4ω0 , where ω0 is in the GSM band frequencies. A fully digital circuit (ADPLL) is built around the DCO to adjust its phase and frequency deviations in a negative feedback manner.

Yo-Chuol Ho et al.

11 VDD L1A

Vtune high

L1B SRAM

Varactors

OSCM

OSCP

ROM

MT2

ARM7

dx

dx

Digital baseband

MT1

SRAM M1

M2 ADPLL + TX Mod

BE LDO

Vtune low High Z

L0

ADO

C0

M0

MTDSM

BGAP

Ib Bias

DCO

DAC Logic

LNA +DPA

CGND (a)

The presented techniques have been realized in silicon. Figure 19 shows two chip micrographs representing the first and second generation of digital RF processor (DRP), respectively: (1) commercial 10 mm2 single-chip Bluetooth radio in 130 nm CMOS, and (2) a fully functional preproduction version of the single-chip GSM radio in 90- nm CMOS. The GSM chip consists of two independent pairs of transmitters and receivers to study various on-die coupling mechanisms, which are especially important in full-duplex WCDMA operations with RX and TX diversity. The 90- nm process features the following parameters that characterize the process: 0.27 μm minimum metal pitch, five levels of copper metal, 1.2 V nominal transistor voltage, 2.6 nm gate oxide thickness, logic gate density of 250 kgates/mm2 , SRAM cell density of 1.0 Mb/mm2 . The measured RX sensitivity of −82 dBm for Bluetooth and −110 dBm for GSM, versus the respective specifications of −70 dBm and −102 dBm, is quite competitive with conventional solutions. The overall GSM RX noise figure is only 2 dB. 5.

GSM RX FRONT-END PERFORMANCE

The LNA input is matched using an external inductor and a capacitor with a balun for impedance ratio of 50 to 100 Ω. The measured LNA input matching with S11 is < −10 dB over the whole GSM band. When the curves of S11 versus multiple LNA gains are compared, largest variation is less than 1 dB. Figure 20 displays the front-end voltage gains versus different LNA and TA gain settings. The front-end gains can be configured with an automatic-gain-control (AGC) function to select an optimal gain setting trading off noise figure for linearity. This circuit adds 32.5 dB dynamic range to the receiver.

DCXO

ADC

RX

RX

ADPLL TX DCO

MTDSM LNA

TX

ARM7 +SPRAM

SILICON REALIZATION

DPA

4.

ARM7 + SRAM

Figure 18: DCO core schematic.

DCXO

LDOs

(b)

Figure 19: Die micrographs of radios employing two generations of DRP: (a) the commercial single-chip Bluetooth radio; (b) the preproduction version of the single-chip GSM radio.

The measured noise figure in the maximum gain mode is 1.8 dB which is excellent, when considering the fact that several hundred thousand digital logic gates are switching on the same die. With LO frequency set to 869.1 MHz, +50 dBm of IIP2 is measured with a front-end gain of 34 dB where the LNA gain is set to 2 dB below the maximum gain (6 LNA) and TA to its middle gain setting (3 TA). To mimic the EDGE environment, two tones of 875.2 MHz and 875.3 MHz are injected into the LNA for the IIP2 test (power of −36 dBm). The LNA, two TAs, and mixers consume 15.3 mA from an internal LDO voltage of 1.4 V. Since this work has digitally configurable gain with a fine resolution, it is different from a conventional front-end approach that is typically built for two large steps. A major advantage of our approach is that

12

EURASIP Journal on Wireless Communications and Networking 5

40 35 30 25 20 15 10 5 0

0 Transfer characteristic (dB)

Gain (dB)

45

(1 TA)

(7 (6 (5 (4

LNA) LNA) LNA) LNA)

(2 TA)

(3 TA) TA gain

(4 TA)

(5 TA)

−5 −10 −15 −20 −25 −30 −35 −40

(3 LNA) (2 LNA) (1 LNA)

10

100 1000 Frequency (kHz) I−270 kHz Q−270 kHz

Figure 20: Measured voltage gain.

10 000

I−150 kHz Q−150 kHz

Figure 21: Measured filtering characteristics.

Table 1: Measured performance. Measured data Noise figure (1 kHz—100 kHz) NF with −25 dBm blocker at 3-MHz offset S11 IIP2 IIP3 P1 dB Gain Front-end current consumption

2.0 dB 5.0 dB < −10 dB +50 dBm −15 dBm −25 dBm +34 dB 15.3 mA

and Q channels with switched capacitor filter (SCF). While providing 35 digitally configurable gain steps ranging from 40 dB down to 7.5 dB, this fully integrated front-end circuit demonstrates a good noise figure of 1.8 dB at 40 dB maximum gain and +50 dBm IIP2 at 34 dB of gain, while a million of digital logic gates are simultaneously running on the same die. This paper demonstrates feasibility and attractiveness of employing the charge-domain RF signal processing within a larger system-on-chip (SoC) designs. REFERENCES

the circuit performance can be finely optimized by selecting the appropriate gain settings. Table 1 summarizes the measured performance when the front-end gain of 34 dB is selected with LNA gain setting number 6 (max −2 dB) and TA gain setting number 3. Since the SCF is a highly-linear filter, little degradation in linearity has been measured. In Figure 21, two pairs of measured plots at SCF output show the lowpass filtering where the 3- dB frequencies are set to 150 kHz and 270 kHz. 6.

CONCLUSION

We have presented an RF direct sampling technique that achieves great selectivity right at the mixer level. The dynamic range requirements of the following ADC are thus significantly relaxed. The selectivity is digitally controlled by the LO clock frequency and the capacitance ratio, both of which are extremely precise in digital deep-submicron CMOS processes. In order to validate the proposed technique, the multitap direct sampling mixer (MTDSM)-based front-end RX has been fabricated as part of commercial Bluetooth and GSM radios in digital deep-submicron CMOS processes. We have also presented implementation details of the GSM receiver front end realized in a 90-nm digital CMOS technology. It includes LNA, transconductance amplifier (TA), mixer for I

[1] A. A. Abidi, “RF CMOS comes of age,” IEEE Journal of SolidState Circuits, vol. 39, no. 4, pp. 549–561, 2004. [2] W. Krenik, D. Buss, and P. Rickert, “Cellular handset integration—SIP vs. SOC,” in Proceedings of IEEE Custom Integrated Circuits Conference (CICC ’04), pp. 63–70, Orlando, Fla, USA, October 2004. [3] K. Muhammad, D. Leipold, R. B. Staszewski, et al., “A discretetime Bluetooth receiver in a 0.13/spl μ/m digital CMOS process,” in Proceedings of IEEE International Conference on SolidState Circuits (ISSCC ’04), vol. 1, pp. 268–269, 527, San Francisco, Calif, USA, February 2004. [4] K. Muhammad and R. B. Staszewski, “Direct RF sampling mixer with recursive filtering in charge domain,” in Proceedings of the International Symposium on Circuits and Systems (ISCAS ’04), vol. 1, pp. I-577–I-580, Vancouver, BC, Canada, May 2004, sec. ASP-L29.5. [5] K. Muhammad, R. B. Staszewski, and C.-M. Hung, “Joint common mode voltage and differential offset voltage control scheme in a low-IF receiver,” in Proceedings of IEEE Radio Frequency Integrated Circuits Symposium (RFIC ’04), pp. 405–408, Fort Worth, Tex, USA, June 2004, sec. TU3C-2. [6] R. B. Staszewski, K. Muhammad, D. Leipold, et al., “All-digital TX frequency synthesizer and discrete-time receiver for Bluetooth radio in 130-nm CMOS,” IEEE Journal of Solid-State Circuits, vol. 39, no. 12, pp. 2278–2291, 2004. [7] S. Karvonen, T. Riley, and J. Kostamovaara, “A low noise quadrature subsampling mixer,” in Proceedings of IEEE

Yo-Chuol Ho et al.

[8]

[9]

[10]

[11]

[12]

[13]

International Symposium on Circuits and Systems (ISCAS ’01), vol. 4, pp. 790–793, Sydney, NSW, Australia, May 2001. S. Lindfors, A. Parssinen, and K. A. Halonen, “A 3-V 230-MHz CMOS decimation subsampler,” IEEE Transactions on Circuits and Systems II, vol. 50, no. 3, pp. 105–117, 2003. K. Muhammad, Y.-C. Ho, T. Mayhugh, et al., “A discrete time quad-band GSM/GPRS receiver in a 90nm digital CMOS process,” in Proceedings of IEEE Custom Integrated Circuits Conference (CICC ’05), pp. 809–812, San Jose, Calif, USA, September 2005, sec. 28-5. Y.-C. Ho, K. Muhammad, M.-C. Lee, et al., “A GSM/GPRS receiver front-end with discrete-time filters in a 90nm digital CMOS,” in Proceedings of IEEE Dallas/CAS Workshop: Architectures, Circuits and Implementation of SoC (DCAS ’05), pp. 199–202, Dallas, Tex, USA, October 2005. Y.-C. Ho, C.-M. Hung, K. Muhammad, et al., “A 1.8dB NF receiver front-end for GSM/GPRS in a 90nm digital CMOS,” in Proceedings of International SoC Design Conference (ISOCC ’05), pp. 211–214, Seoul, Korea, October 2005, ses. 12. R. B. Staszewski, J. Wallberg, S. Rezeq, et al., “All-digital PLL and GSM/EDGE transmitter in 90nm CMOS,” in Proceedings of IEEE International Solid-State Circuits Conference (ISSCC ’05), vol. 1, pp. 316–317, 600, San Francisco, Calif, USA, February 2005, sec. 17.5. K. O, “Estimation methods for quality factors of inductors fabricated in silicon integrated circuit process technologies,” IEEE Journal of Solid-State Circuits, vol. 33, no. 8, pp. 1249–1252, 1998.

Yo-Chuol Ho received the B.S. degree in EE from Seoul National University, Seoul, Korea, in 1987, the M.S. degree in EE from KAIST, Seoul, Korea, in 1989, and the Ph.D. degree from the SiMICS Group of the ECE Department, University of Florida, in 2000. From March 1989 to June 1994, he worked as a PC Development/Product Engineer at Daewoo Telecommunication, Seoul, Korea. During summer 1998, he worked at Harris Semiconductor, Melbourne, Fla. From May 1999 to August 1999, he was with Conexant Systems, Newport Beach, Calif, where he did research on substrate isolation in high-frequency CMOS circuits. Since 2000, he has joined Texas Instruments Inc., Dallas, Tex, as a Design Engineer, and has been involved in Bluetooth SOC IC development in CMOS. His research interests includes radio frequency transceiver circuits and systems. Robert Bogdan Staszewski received the B.S.E.E. (summa cum laude), M.S.E.E., and Ph.D. degrees from the University of Texas at Dallas in 1991, 1992, and 2002, respectively. From 1991 to 1995, he was with Alcatel Network Systems in Richardson, Tex, working on Sonnet cross-connect systems for fiber optics communications. He joined Texas Instruments in Dallas, Tex, in 1995, where he is currently a Distinguished Member of Technical Staff. Between 1995 and 1999, he has been engaged in advanced CMOS read channel development for hard disk

13 drives. In 1999, he costarted a Digital Radio Frequency Processor (DRP) Group within Texas Instruments with a mission to invent new digitally intensive approaches to traditional RF functions for integrated radios in deep-submicron CMOS processes. Dr. Staszewski currently leads the DRP system and design development for transmitters and frequency synthesizers. He has authored and coauthored 40 journal and conference publications and holds 25 issued US patents. His research interests include deep-submicron CMOS architectures and circuits for frequency synthesizers, transmitters, and receivers. Khurram Muhammad received the B.S. degree from the University of Engineering and Technology, Lahore, Pakistan, in 1990, the M. Eng. Sc. degree from the University of Melbourne, Parkville, Victoria, Australia, in 1993, and the Ph.D. degree from Purdue University, West Lafayette, Ind, in 1999, all in electrical engineering. Since 1999, he has worked at Texas Instruments Inc., Dallas, Tex, on read-channel, power-line modem, A/D and D/A converters. Currently he leads the RX system development of the Digital RF Processor (DRP) Group in addition to leading the receiver design. His research interests include softwaredefined radio, SoC integration, low-power and low-complexity design. Chih-Ming Hung received his B.S. degree in electrical engineering from the National Central University, Chung-Li, Taiwan, in 1993, and his M.S. and Ph.D. degrees in electrical and computer engineering from the University of Florida, Gainesville, in 1997 and 2000, respectively. In July 2000, he joined Texas Instruments, Dallas, Tex. He has focused on R&D of advanced CMOS RF IC for wireless cellular applications. Since 2002, he has been a Group Member of Technical Staff and a Design Manager responsible for RF front end for digital RF processor (DRP). He has authored and coauthored 33 journal and conference publications. He has one granted patent and 12 patents pending. Dr. Hung also serves as a reviewer for various technical journals and conferences. His interests include CMOS RF IC design, integrated passive components, and SoC integration. Dirk Leipold received his Diploma in physics from the University of Konstanz in 1991. From 1991 to 1995, he worked in the Paul Scherrer Institute, Zurich, on smart pixel optoelectronics. He received his Ph.D. degree in physics from the University of Konstanz in 1995. He joined Texas Instruments, Germany, in 1995, where he worked on RF process integration, device characterization and modeling, particularly the development of RF-CMOS technologies on high resistivity substrates. From 1998 to 1999, he represented Texas Instruments in ETSI Hiperlan2 Committee, where he was an Editor for the PHY layer technical specification. In 1999, he moved to Texas Instruments in Dallas, Tex, where he is currently a Design Manager of the Digital RF Processor (DRP) Group. His research interests include advanced RF architectures, nanometer scale CMOS processes, and quantum electronics.

14 Kenneth Maggio graduated from Oklahoma State University and joined Texas Instruments, Inc., Dallas, in 1989, in the Defense and Electronics Group, particularly IC development for a wide range of applications including phase array radar, and radar jammers. He later moved to the Hard Disk Drive Products Group where he was a Key Instigator and Design Manager of a new design group for read/write preamplifiers which captured a majority market share. In 1999, he moved to the Wireless Terminals Group where he is currently the Chief Technical Officer of the Digital RF Processor (DRP) Group, Texas Instruments, Inc. His research interests are mixed signal and RF design.

EURASIP Journal on Wireless Communications and Networking

Hindawi Publishing Corporation EURASIP Journal on Wireless Communications and Networking Volume 2006, Article ID 71249, Pages 1–8 DOI 10.1155/WCN/2006/71249

A Sigma-Delta ADC with Decimation and Gain Control Function for a Bluetooth Receiver in 130 nm Digital CMOS Jinseok Koh, Gabriel Gomez, Khurram Muhammad, R. Bogdan Staszewski, and Baher Haroun Wireless Analog Technology Center, Texas Instruments Inc., Dallas, TX 75243, USA Received 25 October 2005; Revised 15 April 2006; Accepted 18 April 2006 We present a discrete-time second-order multibit sigma-delta ADC that filters and decimates by two the input data samples. At the same time it provides gain control function in its input sampling stage. A 4-tap FIR switched capacitor (SC) architecture was chosen for antialiasing filtering. The decimation-by-two function is realized using divided-by-two clock signals in the antialiasing filter. Antialiasing, gain control, and sampling functions are merged in the sampling network using SC techniques. This compact architecture allows operating the preceding blocks at twice the ADC’s clock frequency, thus improving the noise performance of the wireless receiver channel and relaxing settling requirements of the analog building blocks. The presented approach has been validated and incorporated in a commercial single-chip Bluetooth radio realized in a 1.5 V 130 nm digital CMOS process. The measured antialiasing filtering shows better than 75 dB suppression at the folding frequency band edge. A 67 dB dynamic range was measured with a sampling frequency of 37.5 MHz. Copyright © 2006 Jinseok Koh et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

1.

INTRODUCTION

Discrete-time analog signal processing approaches for Bluetooth wireless receivers have been proposed and successfully implemented [1, 2]. These receivers employ a discrete-time architecture in which the RF signal is directly sampled and filtered using analog and digital signal processing techniques. Although sampling close to the front-end may render the receiver architecture more susceptible to noise folding and clock jitter effects, it also provides significant advantages that make this technique very attractive. From the RF wireless system point of view, integrating analog building blocks and digital baseband circuits on the same chip helps to reduce area and power consumption, thus driving down the total system cost. Advanced digital CMOS technology provides very high-speed switching devices, thus allowing discrete-time circuits to be clocked at very high rates. Additionally, it is well known that these digital CMOS processes show component matching as good as or even better than traditional analog processes, even though absolute component value may present big spread over process corners. The approach shown in Figure 1 [1, 2] takes advantage of this system and CMOS process characteristics by directly sampling the RF signal after the LNA and subsequent processing that exploits the precise capacitance ratios that set

the filtering coefficients. Total noise due to folding can be minimized by sampling at a very high rate compared to the input signal bandwidth. This is achieved in the direct sampling mixer (DSM) which samples the RF signal at RF carrier rate, while down-converting and integrating it in a sampling capacitor. In order to realize the direct sampling, the DSM clocking frequency must be kept high at RF, while, at the same time, the ADC data rate should be kept low in order to reduce power dissipation and to allow for sufficient settling time to the input signal. Thus, an ADC that provides data rate conversion and signal amplification in the input sampling stage becomes very advantageous. Figure 2 represents a basic idea for this approach. In this paper, we present such an approach, which has been implemented and verified in a 130 nm digital CMOS process. The organization of this paper is as follows. Section 2 presents the receiver architecture. The sigma-delta ADC design and the proposed built-in antialiasing filter merged into sampling network are described in Section 3. Measurements and implementation are presented in Section 4. Performance summary and conclusions are covered in Section 5. 2.

RECEIVER ARCHITECTURE

The amount of interferer filtering performed in the frontend establishes the ADC dynamic range (DR) specification

2

EURASIP Journal on Wireless Communications and Networking 2400 MS/s MTDSM

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Figure 1: A discrete-time RF wireless receiver [1, 2].

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Figure 2: Typical building blocks for what would be required for decimation and gain control.

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Figure 3: Proposed sigma-delta ADC architecture.

amplifier (IFA), thus relaxing the IFA specification and optimizing power consumption. A hypothetical conventional solution, as shown in Figure 2 would require an isolation buffer between the FIR filter and the ADC input sampling stage in order to avoid charge sharing between the two switched capacitor blocks. This buffer would also provide the required AGC functionality. However, this amplifying stage would have very demanding settling time requirements to reduce the error at the sampling instant in the ADC input stage. In addition, it would increase area and power consumption. The FIR filtering, decimation-by-two, and gain control functions are all implemented in the sampling network at the input of the ADC. As shown in Figure 3, combining these functions in a single sampling structure optimizes area, power, and complexity. 3. 3.1.

to a minimum of 60 dB. In [3, 4], it was shown that a 5level second-order sigma-delta ADC can achieve this DR at a Fs = 37.5 MHz sampling frequency while maintaining a low power dissipation. The block diagram in Figure 3 shows the 3-bit sigma-delta architecture with the built-in antialiasing filter. This multibit architecture relaxes the first integrator’s amplifier requirements, thanks to the reduced signal changes at the amplifier’s output when compared to a singlebit sigma-delta ADC. Also, the required full signal swing at this node is reduced, resulting in a relaxed settling time and slew rate specifications. This also results in area and power savings, since a single-stage low-voltage and low-power amplifier can be used for the implementation. Two issues need to be carefully considered for the ADC system design. First, since decimation causes noise folding, an antialiasing filter is required. This filter is implemented using an FIR switched capacitor structure. Second, from the Bluetooth system requirements, there is a need for an automatic gain control (AGC) function. Providing some gain control at the input of the ADC helps distributing the AGC function between the ADC and the intermediate frequency

SIGMA-DELTA ADC DESIGN FIR antialiasing filter and decimation

The diagram in Figure 4 shows a switched capacitor implementation of the sampling network, but, for the sake of clarity at this point, it does not include the gain control function. Since the supply voltage is 1.58 V, that is, above 1.4 V of the nominal supply to ensure good transconductance, all switches are realized as regular NMOS devices with nominal VT = 600 mV. The key role of the FIR filter is to provide enough noise suppression around Fs /2. The signal at the input of the ADC is naturally band-limited to 75 MHz by the preceding circuits. The ADC works at half that frequency. A 4-tap charge-domain FIR filter is implemented to attenuate the input signal noise around 37.5 MHz. The FIR order was determined by system level simulations. The FIR filter difference equation is given by CM · y[n] = C0 · x[n] + C1 · x[n − 1] + C2 · x[n − 2] + C3 · x[n − 3],

(1)

where coefficients C0 , C1 , C2 , and C3 are 1, 3, 3, and 1, respectively, which can be easily implemented as capacitor ratios.

Jinseok Koh et al.

3 Input

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Figure 4: Four-tap FIR filter implementation.

FIR filter frequency response

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Figure 5: Output power spectrum density for FIR filter with white noise input.

The plot in Figure 5 shows the FIR output power spectral density with white noise applied as input. Matlab simulations indicate that more than 80 dB attenuations can be achieved at the folding frequency band edge (36.5 MHz, since 1 MHz is the signal bandwidth). Capacitor mismatches in the FIR filter can possibly cause distortion and unwanted modulation. In order to reduce this effect, dynamic element matching techniques can be employed with additional switched capacitor circuits. However, these extra circuits increase area. Another way to minimize this effect is to use bigger unit capacitance which has generally better matching. Thanks to the good matching property of the CMOS process, 10 bit matching can be easily achieved

without dramatically increasing unit capacitance. Based on behavioral-level simulations, the minimum allowable capacitance value was chosen. Six-phase clock signals are utilized to realize both the FIR filter and the decimation functions. On P1 phase, the input signal is sampled in C p2 and 3C p1 , on P2 phase, it is sampled in C p2 , and 3C p2 , and on Pi phase, the input is sampled into C pi and 3C pi , with i = 1, . . . , 6. After P6, the process is repeated back from P1 phase. On I1 integrating phase, charge in capacitors C p2 , 3C p3 , 3C p4 , and C p5 is dumped into the integrating capacitor CM . As shown in the timing diagram in Figure 6, integration occurs in P1, P3, and P5 phases only (with corresponding signal names I1, I2, and I3). Since there could be no integration for P2, P4, or P6 phases, decimation-by-2 operation is achieved. To increase the time available for integrator settling, integrating control signals’ I1, I2, and I3 duty cycle is extended as shown in Figure 6.

4

EURASIP Journal on Wireless Communications and Networking High gain mode

Csh

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Figure 9: Folded cascode amplifier.

400 300 200 100 0 564 noise tot

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Figure 8: Noise analysis.

3.2. Gain control Figure 7 shows how the two-step (0 dB and 14 dB, derived from the Bluetooth RX system specifications) gain control function is implemented using switched capacitor circuits. When the switch HG turns on, the 14 dB gain mode is activated. When the 0 dB mode is activated, switch LG turns on instead of switch HG. The total gain is simply defined by the ratio between the sampling and the integrating capacitors. This function is implemented in the FIR sampling block by adding the high-gain-mode switched capacitor in parallel with each of the capacitors in Figure 4. An alternative of adding the capacitance in the amplifier feedback is not the best choice since it would change the amplifier gainbandwidth (GBW) product. The load capacitance at the IFA output is an important design parameter, since it affects the GBW product as well as the slew rate of the amplifier. Therefore, both gain modes should provide the same load condition to the IFA output. As shown in Figure 7, the capacitance seen at the input port is kept constant for both gain modes. In order to minimize the sampling error due to charge injection and clock feed-through from the switches, transistor sizes are optimized for speed and area. Figure 8 shows the

noise analysis for the proposed ADC. Quantization noise is a dominant noise contributor for this application due to the low oversampling ratio (OSR), making kT/C noise less of an issue. Therefore, the unit capacitance element in the FIR filter is selected based mainly on the effect of mismatch on the ADC performance. 3.3.

Amplifier, comparator, and DAC

A folded cascode fully differential amplifier with a switched capacitor common mode feedback is used [5]. Amplifier noise is optimized on the basis of power consumption and area. However, as in the case of kT/C noise, noise from the amplifier is not very critical due to the high in-band quantization noise. Therefore slew rate, GBW, and output dynamic range became the most critical design parameters. Since the sigma-delta ADC has to work in the same substrate as the digital core, digital circuit noise coupling through the substrate and supply rails was carefully considered as an important design and layout parameter. Layout considerations are also very critical, since any component mismatch could result in degradation of common-mode noise rejection and cancellation. Also, great care was taken to provide enough guard ringing and supply decoupling. The final amplifier configuration is shown in Figure 9, which does not include the common mode feedback or the bias circuits. A five-level quantizer is implemented using four comparators to build a flash ADC. The flash ADC utilizes switched capacitor subtraction in order to generate four different threshold voltages. The simplified comparator circuits for one of the flash’s four stages, including subtraction circuits, are depicted in Figure 10. The 5-level (+2, +1, 0, −1, −2) DAC is implemented using four switched capacitor elements that keep constant the capacitor loading at the input of the amplifier, independently

Jinseok Koh et al.

5 VINP

Ci

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+ COMP +

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Figure 10: Switched capacitor comparator.

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of the quantizer output. Two DAC elements could have been used for a 5-level DAC realization, but the load capacitance would be different for the case when quantizer output is +1 or −1 versus the case when it is +2, 0, and −2. In order to suppress nonlinearities generated in the 5-level switched capacitor DAC, the individual level averaging (ILA) algorithm is used [3, 6]. Any possible distortion from the capacitor mismatch in the 5-level DAC is translated into gain error by the ILA algorithm. This phenomenon is depicted in Figure 11. Two worst-case mismatch conditions were chosen and verified in behavioral and SPICE simulations. Figure 11(a) shows the 5-level DAC transfer function by using two worst-case mismatch conditions. Figure 11(b) shows a DAC transfer function when ILA is used to liberalize the DAC transfer function. In order to visualize the effect from capacitor mismatch clearly, unrealistic matching numbers were used to generate the plot in Figure 11.

4.

EXPERIMENTAL RESULTS

The 3-bit sigma-delta ADC output was captured using a high-frequency DSP-based data acquisition system. The dynamic performance was obtained by post-processing the captured data through an FFT and computing various performance numbers. Figure 12 is the measured FIR filter response with a −6 dBFS input sinusoidal signal applied to the ADC at frequency steps of 1 MHz from 1 MHz to 30 MHz. The measurement results are well matched to the theoretical curve of the FIR antialiasing filter, as can be seen in the plot. The gain of the filter response is slightly less than the theoretical number due to the gain error induced from nonidealities in the integrator, reference buffer, and SC DAC. The power spectral density plot in Figure 13 shows the system performance when two signals (0 dB at 37 MHz and −6 dB at 275 kHz) are applied together. By sampling theory,

6

EURASIP Journal on Wireless Communications and Networking Antialiasing FIR filter response

0

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Figure 13: Spectrum of the captured output.

this should cause a folding signal at 500 kHz (37.5 MHz (Fs ) −37 MHz), but as the figure shows, it is filtered and attenuated below the quantization noise floor. The interferers in communication systems need to be carefully taken into account especially in cases where system nonlinearities may create intermodulation. Due to ADC nonlinearities, an interferer can be folded into the Bluetooth signal bandwidth by means of intermodulation. Figure 14 shows the measured FFT plot for an intermodulation test. Two −8 dBFS sinusoidal signals at 1 MHz (F1 ) and 2.2 MHz (F2 ) are applied. A −80 dBc IM3 signal appears at 200 kHz. The measured IM3 satisfies and exceeds the system requirements. Figure 15 shows the measured SNDR versus input amplitude for 0 dB and 14 dB gain modes. The measured

peak SNDR is 60 dB for an input 4 dB from full scale with a 1 MHz bandwidth, where the full scale is defined as twice the reference voltage. Table 1 shows the performance summary of the implemented ADC. Die photo for the dual channel implementation is shown in Figure 16. 5.

CONCLUSION

A discrete-time second-order 5-level sigma-delta ADC has been successfully implemented and characterized in a 1.5 V 130 nm digital CMOS technology. The built-in antialiasing filter and a two-step gain control are merged into the sampling network. The decimation-by-two function relaxes the settling requirements of the amplifier. The two-step gain control increases the overall dynamic range and also relaxes the automatic gain control burden in the Bluetooth system

Jinseok Koh et al.

7

Table 1: Performance summary. Technology Sampling frequency Signal bandwidth Peak SNDR (0 dB gain option) Peak SNDR (14 dB gain option) Dynamic range Overall dynamic range Input range Supply voltage Power consumption Core area

130 nm digital CMOS 37.5 MHz 1 MHz 60 dB 57 dB 67 dB 77 dB 1.4 V pp (diff) 1.58 V 1.6 mW 0.2 mm2

[2]

[3]

[4]

[5]

DAC

[6] ADC

MTDSM

Figure 16: Micrograph of the dual channel ADC.

implementation. Since the quantization noise is the dominant factor due to the low oversampling ratio and the kT/C noise and amplifier noise are not critical, the power consumption in the ADC system was optimized, which resulted in saving area and current consumption. The total area including the switched capacitor sampling network is 0.2 mm2 per ADC channel. The consumed power is 1.6 mW per channel at a 1.58 V supply. The achieved dynamic performance fully satisfies the system requirements for a Bluetooth receiver. The presented architecture can be easily extended to higher decimation ratios and better gain control resolution, while the FIR filter can be easily adjusted for different modes or system requirements. ACKNOWLEDGMENTS The authors would like to thank B. Bakkaloglu for discussion and comments and to W. E. Kim and H. S. Kim for support in device testing and characterization. REFERENCES [1] K. Muhammad, D. Leipold, B. Staszewski, et al., “A discretetime Bluetooth receiver in a 0.13μm digital CMOS process,” in Proceedings of IEEE International Solid-State Circuits Conference

(ISSCC ’04), vol. 1, pp. 267–269, 527, San Francisco, Calif, USA, February 2004. R. B. Staszewski, K. Muhammad, D. Leipold, et al., “All-digital TX frequency synthesizer and discrete-time receiver for Bluetooth radio in 130-nm CMOS,” IEEE Journal of Solid-State Circuits, vol. 39, no. 12, pp. 2278–2291, 2004. G. Gomez and B. Haroun, “A 1.5 V 2.4/2.9 mW 79/50 dB DR ΣΔ modulator for GSM/WCDMA in a 0.13 μm digital process,” in Proceedings of IEEE International Solid-State Circuits Conference (ISSCC ’02), pp. 242–243, 490, San Francisco, Calif, USA, February 2002. J. Koh, K. Muhammad, B. Staszewski, G. Gomez, and B. Horoun, “A sigma-delta ADC with a built-in anti-aliasing filter for Bluetooth receiver in 130nm digital process,” in Proceedings of IEEE Custom Integrated Circuits Conference (CICC ’04), pp. 535–538, Orlando, Fla, USA, October 2004, sec. 25-6. H. C. Yang, M. A. Abu-Dayeh, and D. J. Allstot, “Analysis and design of a fast-settling folded-cascode CMOS operational amplifier for switched-capacitor applications,” in Proceedings of the 32nd Midwest Symposium on Circuits and Systems, vol. 1, pp. 442–445, Champaign, Ill, USA, August 1989. B. H. Leung and S. Sutarja, “Multibit Σ-Δ A/D converter incorporating a novel class of dynamic element matching techniques,” IEEE Transactions on Circuits and Systems II, vol. 39, no. 1, pp. 35–51, 1992.

Jinseok Koh was born in Seoul, Korea, in 1968. He received his Ph.D. degree in electrical engineering from Texas A&M University in 2000. From 1993 to 1996, he was with Samsung Electronics as a Design Engineer working on the high-speed BiCMOS SRAM. When he was at Texas A&M University, he was with Analog Mixed Signal Center working on the sensor-based circuit implementations and modeling of nonidealities in data converters. He has developed an LMS-based sigma-delta ADC. He joined Texas Instruments in 2000, where he is working on transceiver designs for wireless applications. His interest is on the sigma-delta ADCs, high-speed DACs, and transceiver architectures. Gabriel Gomez received the Master’s degree electronic engineering from the Philips International Institute, Eindhoven, Netherlands, in 1987 and the M.S.E.E. degree from Wright State University, Dayton, Ohio in 1991. During 1992, he worked as an Assistant Professor at the Universidad del Valle, Cali, Colombia. From 1993 to 1995 he was a Ph.D. student while working as a Research Assistant at Texas A&M University, College Station, Tex. Since 1995 he has been with Texas Instruments, Inc., Dallas, Tex, as an IC Design Engineer in the Mixed Signal Design Department. He worked for four years in the Audio/Multimedia Group, designing data converters for audio and multimedia applications. Currently he works for the Nano-Meter Analog Integration Branch, as a Design Manager of the Advanced Analog Cells Section, in charge of the design of data converters for personal communication systems. His current main interest is the design of low-power low-voltage sigma-delta converters on deep submicron digital processes. He was elected as a Distinguished Member of the Technical Staff (DMTS) in 2005, in recognition for his contributions to the Semiconductor Group at Texas Instruments.

8 Khurram Muhammad received the B.S. degree from the University of Engineering and Technology, Lahore, Pakistan, in 1990, the M.Eng. degree from the University of Melbourne, Parkville, Victoria, Australia, in 1993, and the Ph.D. degree from Purdue University, West Lafayette, Ind in 1999, all in electrical engineering. Since 1999, he has worked at Texas Instruments Inc., Dallas, Tex, on read-channel, power-line modem, as well as A/D and D/A converters. Currently he leads system development of the Digital RF Processor (DRP) Group in addition to leading the receiver design. His research interests include softwaredefined radio, SoC integration, as well as low-power and lowcomplexity design. R. Bogdan Staszewski received the BSEE (summa cum laude), MSEE, and Ph.D. degrees from the University of Texas at Dallas in 1991, 1992, and 2002, respectively. From 1991 to 1995 he was with Alcatel Network Systems in Richardson, Tex, working on Sonnet cross-connect systems for fiber optics communications. He joined Texas Instruments in Dallas, Tex, in 1995 where he is currently a Distinguished Member of Technical Staff. Between 1995 and 1999, he has been engaged in advanced CMOS read channel development for hard disk drives. In 1999 he costarted a Digital Radio Frequency Processor (DRP) Group within Texas Instruments with a mission to invent new digitally intensive approaches to traditional RF functions for integrated radios in deep-submicron CMOS processes. Dr. Staszewski currently leads the DRP system and design development for transmitters and frequency synthesizers. He has authored and coauthored 40 journal and conference publications and holds 25 issued US patents. His research interests include deep-submicron CMOS architectures and circuits for frequency synthesizers, transmitters, and receivers. Baher Haroun received the B.S. degree (1981), the M.S. degree (1984) in electrical engineering from Ain Shams University, Egypt, and the Ph.D. degree (1989) from Electrical and Computer Engineering Department, University of Waterloo, Waterloo, Ontario, Canada. From 1989 to 1995, he was an Assistant, then Associate Professor in the Department of Electrical and Computer Engineering at Concordia University, Montreal, Canada. He joined Texas Instruments in 1995. He is now a Texas Instruments Fellow and a Design Manager of the Nanometer Analog Integration Branch in the Wireless Terminal Business Unit of Texas Instruments. He has several papers and patents to his credit and his research interests include low-power and low-voltage mixed signal wireless integrated circuits, GHz serial interfaces and high-performance and low-power digital signal processing architectures.

EURASIP Journal on Wireless Communications and Networking

Hindawi Publishing Corporation EURASIP Journal on Wireless Communications and Networking Volume 2006, Article ID 48489, Pages 1–11 DOI 10.1155/WCN/2006/48489

Design and Characterization of a 5.2 GHz/2.4 GHz ΣΔ Fractional-N Frequency Synthesizer for Low-Phase Noise Performance John W. M. Rogers,1 Foster F. Dai,2 Calvin Plett,1 and Mark S. Cavin3 1 Carleton

University, 1125 Colonel Drive Ottawa, ON, Canada K1S 5B6 and Computer Engineering Department, Auburn University, Auburn, AL 36849-5201, USA 3 Alereon, Inc., 7600 North Capital of Texas Highway, Building C, Suite 200 Austin, TX 78731, USA 2 Electrical

Received 8 August 2005; Revised 8 January 2006; Accepted 13 January 2006 This paper presents a complete noise analysis of a ΣΔ-based fractional-N phase-locked loop (PLL) based frequency synthesizer. Rigorous analytical and empirical formulas have been given to model various phase noise sources and spurious components and to predict their impact on the overall synthesizer noise performance. These formulas have been applied to an integrated multiband WLAN frequency synthesizer RFIC to demonstrate noise minimization through judicious choice of loop parameters. Finally, predicted and measured phase jitter showed good agreement. For an LO frequency of 4.3 GHz, predicted and measured phase noise was 0.50◦ rms and 0.535◦ rms, respectively. Copyright © 2006 John W. M. Rogers et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

1.

INTRODUCTION

High-speed frequency synthesis is one of the most challenging areas in radio frequency integrated circuit (RFIC) design. It requires diverse knowledge of both high-speed analog and digital circuits as well as deep knowledge of system level issues. The performance requirements on circuits used for frequency synthesis are often extremely demanding making the design of these blocks even more challenging. However, a high-performance frequency synthesizer is a key component in many wired (fiber or cable) and wireless communication systems. For modern multistandard applications, it is often difficult to cover multiple frequency bands using classical integerN frequency synthesizers whose step size is limited by the reference frequency. In order to achieve fine step size to cover the multiband channel frequencies, one has to lower the reference frequency in an integer-N synthesizer design, which results in high division ratio of the PLL and thus high inband phase noise. In contrast, a fractional-N synthesizer allows the PLL to operate with a high reference frequency while achieving fine step size by constantly swapping the loop division ratio between integer numbers, thus the average division ratio is a fractional number [1–4]. However, fine step size and low in-band phase noise is achieved with the penalty

of fractional spurious tones, which come from the periodical division ratio variation. To remove the fractional spurious components for a synthesizer with fine step size, the best solution is to employ a ΣΔ noise shaper to control a programmable divider. A ΣΔ noise shaper will help to move large spurs to higher frequencies where they can be easily filtered. While spurs are often one of the most important design considerations for a frequency synthesizer, they will not be treated in detail in this paper. Since these techniques are becoming more and more common in modern synthesizer design, noise in this style of synthesizer will be the focus of this paper. Here, a theoretical analysis of phase noise in modern frequency synthesizers will be presented. Phase noise is often the most challenging and crucial performance specification that must be met by a synthesizer. It is also the specification that often proves the most difficult to model and simulate. In this paper, a review of basic phase noise concepts will be presented, followed by a model that will allow the designer to take noise data from individual circuit simulations and predict the overall phase noise performance of an entire PLL frequency synthesizer. The proposed analytical model will then be used to predict and optimize the phase noise performance of a ΣΔ fractional-N frequency synthesizer designed for multiband

2

EURASIP Journal on Wireless Communications and Networking

Ref samp log 10 dB/

−18 dBm

ΔMkr1 2.82 MHz −73.961 dB

Atten 10 dB Carrier signal

1R

Pc

LSSB [dBc/Hz] = Pc [dBm/Hz]−Pn [dBm/Hz]

Discrete spurs LgAv 100 W1 S2 S3 FC

Pn

£( f ) : f > 50 k Swp

Random phase noise

Center 1.056 01 GHz Res BW 91 kHz

BW = 1 Hz Span 10 MHz Sweep 4.64 ms (601 pts)

VBW 91 kHz

Figure 1: An example of phase noise and spurs at the synthesizer output observed using a spectrum analyzer.

WLAN applications. The comparison between the simulated and the measured phase noise demonstrates that the analytical model can accurately predict the performance of the complete synthesizer, and provide the designer with a quick and reliable means to predict the phase noise performance of a synthesizer RFIC prior to its fabrication.

where ϕ p is the peak phase fluctuation and ωm is the offset frequency from the carrier. Substituting (2) into (1) gives

2.

For a small phase fluctuation, the above equation can be simplified as

BASIC PHASE NOISE CONCEPTS

Noise in synthesizers is contributed from all the building block circuits and components that make up the PLL. Synthesizer noise performance is usually expressed as phase noise, which is a measure of how much the output differs from an ideal impulse function in the frequency domain. We are primarily concerned with noise that causes fluctuations in the phase of the output rather than noise that causes fluctuations in the amplitude, since the output typically has a fixed and limited amplitude. The output of a synthesizer can be described as 



vout (t) = Vo sin ωLO t + ϕn (t) ,

(1)

where ωLO t is the desired phase of the output and ϕn (t) is the time-variant random phase fluctuation of the output signal due to any noise sources in the PLL. Phase noise is often quoted in units of dBc/Hz or rad2 /Hz. The phase fluctuation term ϕn (t) in (1) may be random phase noise or discrete spurious tones, also called spurs, as shown in Figure 1. The discrete spurs at a synthesizer output are most likely due to the fractional-N mechanism, while the phase noise in an oscillator is mainly due to thermal, flicker, or 1/ f noise and the finite Q of the oscillator tank. Assume the phase fluctuation is of a sinusoidal form as 



ϕ(t) = ϕ p sin ωm t ,

(2)





vout (t) = V0 cos ωc t + ϕ p sin ωm t



      = V0 cos ωc t cos ϕ p sin ωm t      − sin ωc t sin ϕ p sin ωm t .













(3)



v0 (t) = V0 cos ωc t − ϕ p sin ωm t sin ωc t     ϕp      cos ωc +ωm t − cos ωc − ωm t . = V0 cos ωc t − 2 (4) It is now evident that the phase-modulated signal includes the carrier signal tone and two symmetric sidebands at any offset frequency, as shown in Figure 1. A spectrum analyzer measures the phase noise power in dBm/Hz, but often phase noise is reported relative to the carrier power as 



Noise ωLO + Δω   , PN(Δω) = Pcarrier ωLO

(5)

where Noise is the noise power in a 1 Hz bandwidth and Pcarrier is the power of the carrier or local oscillator (LO) tone at the frequency at which the synthesizer is operating. In this form, phase noise has the units of [rad2 /Hz]. Often this is quoted as so many dB down from the carrier in units of [dBc/Hz]. To further complicate this, both singlesideband and double-sideband phase noise can be defined. Single-sideband (SSB) phase noise is defined as the ratio of power in one phase modulation sideband per Hertz bandwidth, at an offset Δω away from the carrier, to the total signal power. The SSB phase noise power spectral density (PSD)

John W. M. Rogers et al.

3

to carrier ratio, in units of [dBc/Hz], is defined as 

PNSSB (Δω) = 10 log

3.





N ωLO + Δω   Pcarrier ωLO

.

(6)

Combining (4) into (6) this equation can be rewritten as 

2



(1/2) V0 ϕ p /2 PNSSB (Δω) = 10 log (1/2)V02 = 10 log

 ϕ2  p

4





ϕ2rms , = 10 log 2

(7)

where ϕ2rms is the rms phase noise power density in units of [rad2 /Hz]. Note that single-sideband phase noise is by far the most common type reported and often it is not specified as SSB, but rather simply reported as phase noise. However, alternatively double-sideband phase noise can be expressed by 







N ωLO + Δω + N ωLO − Δω   PNDSB (Δω) = 10 log Pcarrier ωLO = 10 log



ϕ2rms

. (8)

From either the single-sideband or double-sideband phase noise, the rms phase noise can be obtained in the linear domain as 180 PNDSB (Δω)/10 10 π √ √  180 2 PNSSB (Δω)/10  = 10 deg/ Hz . π

ϕrms (Δω) =

(9)

It is also quite common to quote integrated phase noise over a certain bandwidth. The rms-integrated phase noise of a synthesizer is given by IntPNrms =

Δω1

ϕ2rms (ω)dω.

(10)

The limits of integration are usually the offsets corresponding to the lower and upper frequencies of the bandwidth of the information being transmitted. In addition, it should be noted that dividing or multiplying a signal in the time domain also divides or multiplies the phase noise. Similarly, if a signal is translated in frequency by a factor of N, then the phase noise power is increased by a factor of N 2 as 





ϕ2rms





3.1.

VCO noise

The phase noise from a VCO can be described as [5, 6] 

ϕ2VCO (Δω) =

ωo (2QΔω)



ϕ2 ωLO + Δω ωLO . + Δω = rms N N2

3.2.

Note this assumes that the circuit that did the frequency translation is noiseless. Otherwise, additional phase noise will be added. Also, note that the phase noise is scaled by N 2 rather than N because we are dealing with noise in units of power rather than units of voltage.

GkT 2PS





1+

ωc , Δω

(12)

Crystal reference noise

Crystal resonators are widely used in frequency control applications because of their unequaled combination of high Q, stability, and small size. The resonators are classified according to “cut,” which is the orientation of the crystal wafer (usually made from quartz) with respect to the crystallographic axes of the material. The total noise power spectral density of a crystal oscillator can also be found from Leeson’s formula and making use of a typical empirical multiplier [7]: 

(11)

2 

where PS is the signal power of the carrier, T is the temperature, Q is the quality factor of the oscillator’s resonator, k is Boltzmann’s constant, ωo is the frequency of oscillation, ωc is the flicker noise corner frequency, and G is a constant of proportionality which takes into account excess noise from the VCO transistors, and nonlinearity. Note that many additional refinements have been made to this formula, however as given here it is sufficient to capture the shape of most integrated VCO’s phase noise. Thus, at most frequencies of interest, the phase noise produced by the VCO will decrease at 20 dB/decade for an increasing offset frequency away from the carrier. This will not continue indefinitely, as thermal noise will put a lower limit on this phase noise which for most integrated VCOs is somewhere between −120 and −150 dBc/Hz. VCO phase noise is usually dominant outside the loop bandwidth and of less importance at low offset frequencies.



ϕ2rms NωLO + Δω = N 2 · ϕ2rms ωLO + Δω , 

Next, we will present the phase noise models for all PLL synthesizer building blocks such as the crystal oscillator, divider, phase-frequency detector (PFD), charge pump (CP), loop lowpass filter (LPF), and voltage-controlled oscillator (VCO). While the circuit-or block-level simulation of a typical synthesizer design will not be discussed in detail in this paper, some basic theory will be presented to show how the noise in each block can affect the loop performance. In Section 4, the effect of these noise sources on a complete synthesizer will be examined.





 Δω2

BUILDING BLOCK PHASE NOISE MODELS FOR PLL SYNTHESIZER

ϕ2XTAL (Δω)

−16±1

= 10



ω0 · 1+ 2Δω · QL

 2 

1+



ωc , Δω (13)

where ω0 is the oscillator output frequency, ωc is the corner frequency between 1/ f and thermal noise regions, which is normally in the range 1–10 kHz, QL is the loaded quality factor of the resonator. Since QL for crystal resonator is very large (normally in the order of 104 to 106 ), the reference noise

4

EURASIP Journal on Wireless Communications and Networking in LPF

contributes only to the very close-in noise and it quickly reaches thermal noise floor at offset frequency around ωc .

R

3.3. Frequency divider noise Frequency dividers consist of switching logic circuits, which are sensitive to the clock timing jitter. The jitter in the time domain can be converted to phase noise in the frequency domain. Time jitter or phase noise occurs when rising and falling edges of digital dividers are superimposed with spurious signals such as Johnson and flicker noise in semiconductor materials. Ambient effects result in variation of the triggering level due to temperature and humidity. Frequency dividers generate spurious noise especially for high-frequency operation. Dividers do not generate signals, but rather simply change their frequency. Kroupa provided an empirical formula, which estimates the amount of phase noise that frequency dividers add to a signal [8, 9]: ϕ2Div Added (Δω) ≈

2 10−14±1 + 10−27±1 ωdo 10−22±1 ωdo + 10−16±1 + , 2π · Δω 2π (14)

where ωdo is the divider output frequency and Δω is the offset frequency. Notice that the first term in (14) represents the flicker noise and the second term gives the white thermal noise floor. The third term is caused by timing jitter due to coupling, ambient, and supply variations. 3.4. Phase detector noise Phase detectors experience both flicker and thermal noise. At large offsets, phase detectors generate a white phase noise floor typically about −160 dBc/Hz, which is thermal noisedominant. The noise power spectral density of phase detectors is estimated empirically by [9] ϕ2PD (Δω) ≈

2π · 10−14±1 + 10−16±1 . Δω

(15)

C2

√

vn = 4kTR C1

Figure 2: Loop filter with thermal noise added.

that will turn on the source and sink currents for about the same amount of time. The closer reality matches the ideal case, the less noise will be produced. Also, note that as the offset frequency is decreased, 1/ f noise will become more important, causing the noise to increase. This noise can often be the dominant noise source at low-frequency offsets. Charge pump noise can be simulated with proper tools such as Cadence pss pnoise analysis. The results depend on the design in question so no simple general analytical formula will be given here, however, an example will be given later. 3.6.

Loop filter noise

Loop filters can be analyzed for noise in the frequency domain in a linear manner. The most common loop filter that will be examined in this paper will now be analyzed. It consists of two capacitors and one resistor. For offchip filters, the loss experienced by capacitors is negligible. Thus, the loop filter contains only one noise source, the thermal noise associated with the resistor R. The loop filter with its associated noise source can be drawn as shown in Figure 2. Now the noise voltage develops a current flowing through the series combination of C1 , C2 , and R (assuming that the CP and VCO are both open circuits), which is given by in LPF =

1 vn s 1 vn s   · ≈ · . R s + C1 + C2 /C1 C2 R R s + 1/C2 R (16)

3.5. Charge pump noise The noise of the charge pump can be characterized as an out√ put noise current and is usually given in pA/ Hz. Note that at this point in the loop, current represents the phase. The charge pump output current noise can be a strong function of the reference frequency and width of the current pulses. Therefore, for low-noise operation it is desirable to keep the charge pump sink and source currents matched as well as possible. This is because current sources only produce noise when they are on. When an ideal loop is locked, the sink and source current sources in a charge pump are turned off, resulting in zero net current charge or discharge of the holding capacitor. However, nonidealities result in finite pulses

Thus, this noise current will have a highpass characteristic, and therefore the loop will not produce any noise at DC and this noise will increase until the highpass corner is reached, after which it will be flat. Other filters can be analyzed in a similar manner. 3.7.

Phase noise due to ΣΔ converters

Fractional-N synthesizers often include ΣΔ modulators to shift the spurious components to a higher-frequency band, where the loop filter can filter randomized spurs. In a ΣΔ fractional-N synthesizer, the average loop divisor value corresponds to the desired output frequency and the instantaneous divisor value is dithered around the correct value by

John W. M. Rogers et al.

5

−Eq2 (z) +

+

n −

1 1 − z−1

n bit z−1

+ A3

C3 (z) +

+

N3 (z)

(1 − z−1 )2

1 bit Eq3 (z)

Integer divisor I(z)

(n + 1) bit + −Eq1 (z) +

n +

−

n bit

1 1 − z−1 z−1

+ A2

−

C2 (z) +

Total divisor N(z)

+

+

1 − z−1

N2 (z) + + +

1 bit Eq2 (z)

+

+

+ +

Fractional divisor F(z) + (1 − z−1 )3 Eq3

(n + 1) bit + F(z)

+

n bit

n +

−

1 1 − z−1 z−1

+ A1

+

+

−

N1 (z) = C1 (z)

+

1 bit Eq1 (z)

Figure 3: A three-loop MASH 1-1-1 ΣΔ modulator for fractional-N synthesis.

the ΣΔ modulator. The ΣΔ noise shaping can be modeled as a linear gain stage with an additive quantization noise source, which is shaped by a highpass transfer function. Hence, the quantization error component at the synthesizer output is composed of mostly high-frequency noise that can be filtered by the PLL. A block diagram of a typical ΣΔ modulator that is widely used in synthesizer applications is shown in Figure 3 [3]. This three-loop sigma-delta topology is called a MASH 1-1-1 structure, because it is a cascaded ΣΔ structure with three first-order loops. Each of the three loops is identical. The input of the second loop is taken from the quantized error Eq1 of the first loop, while the input of the third loop is taken from the quantized error Eq2 of the second loop. Thus, only the first loop has a constant input, which is the fractional portion of the desired rational divide number F(z), that is, the fine tune word. The integer part of the frequency word I(z), the coarse tune word, is added at the output of the three-loop ΣΔ modulator. Thus, Ndiv (z) = I(z) + F(z) is the time sequence used to control the integerrestricted divider ratios. The modulator is clocked at the divider output frequency, reflecting the sampled nature of the circuit. The first loop generates the fractional divisor value F(z) with the byproduct of quantization error Eq1 , which is further fed to the input of the second loop for further processing. The second loop cancels the previous loop’s quantization error Eq1 by the additional filter block (1 − z−1 ) in its output path. The only quantization noise term left after summing the first and second loop outputs is the quantization error Eq2 , which is second-order noise-shaped. When this noise term is further fed to the input of the third loop, the loop generates a negative noise term to cancel the previous loop’s quantization error Eq2 by the additional filter block (1 − z−1 )2

in its output path. Summing the outputs of the three loops, we obtain the modulated divisor value as N(z) = I(z) + N1 (z) + N2 (z) + N3 (z)

 3 = I(z) + F(z) + 1 − z−1 Eq3 (z),

(17)

where I(z) and F(z) are the integer portion and the fractional portion of the division ratio, respectively. As desired, the fractional divisor value F(z) is not affected by the modulator, while the quantization error generated in the last loop Eq3 is noise-shaped by a third-order highpass function of (1 − z−1 )3 . The quantization error generated in the first and second loops are totally canceled, and as a result the total quantization noise is equal to that of a single loop, although three loops are used. Therefore, the multiloop sigma-delta architecture provides high-order noise shaping without additional quantization noise. Discrete fractional spurs are generated by this circuit at multiples of the reference frequency, but these spurs become more like random noise after sigma-delta noise shaping. The single-sideband phase noise of the noise-shaped fractional spurs can be analyzed as follows. The 1-bit quantization error power is Δ2 /12 where Δ is the quantization step size. For Δ = 1, which is the case for a truncated binary word, the quantization error power is 1/12. This error power is spread over the sampling bandwidth, or equivalently the reference bandwidth of fr = 1/Ts . Thus, the error power spectral density (PSD) becomes 1/(12 fr ). Considering the noise shaping with an mth-order MASH ΣΔ modulator as expressed in (17), the frequency noise PSD is obtained as SΩ (z) =

    1 − z−1 m fr 2

12 fr

=

2m 1 1 − z−1 fr , 12

(18)

6

EURASIP Journal on Wireless Communications and Networking Charge pump ϕnoiseI (s) + Crystal reference

ICP

PFD

+

UP

VCO

Loop filter

−

DN

R

Kphase

ICP

C1

C2

KVCO + s

ϕnoise out (s)

F(s) ÷N

+

ΣΔ

ϕΣΔ (s)

ϕnoiseII (s)

Figure 4: A synthesizer showing places where noise is injected.

where the subscript Ω denotes the frequency fluctuations referred to the input of the divider. In order to obtain the phase fluctuations, consider the following relationship between frequency and phase: 

ω(t) =

dφ(t) φ(t) − φ t − Ts ≈ dt Ts

domain is given by 



(19)







ϕ2ΣΔ ( f ) rad2 /Hz πf (2π)2 = · 2 sin 2 24 fr fr 





2(m−1)

πf (2π)2 PN( f )[dBc/Hz] = 10 log · 2 sin 24 fr fr

, 2(m−1) 

. (24)

and its z-domain representation of 



Φ(z) 1 − z−1 , 2π · Ω(z) = TS

(20)

where Ts = 1/ fr is the sample period and where multiplication by z−1 represents a delay of Ts . Rearranging this expression yields Φ(z) =

2π · Ω(z)  . fr 1 − z−1

(21)

Noting that SΩ (z) is given in terms of power, the doublesideband phase noise PSD is obtained as (2π)2 SΦ (z) = SΩ (z)   1 − z−1 2 f 2 r 2m (2π)2 1 =  · 1 − z−1 fr 2 1 − z−1  f 2 12 r =

(22)

2m−2 (2π)2  · 1 − z−1 , 12 fr

where the subscript Φ denotes phase fluctuations. Noting that 







1 − z−1 = 1 − e− jωT  = 2 sin



ωT 2



 = 2 sin



πf , fr (23)

the single-sideband phase noise PSD in the frequency

4.

IN-BAND AND OUT-OF-BAND PHASE NOISE IN PLL SYNTHESIS

A typical PLL-based synthesizer system level diagram that will be analyzed in this paper is shown in Figure 4. It consists of a phase-frequency detector, a charge pump, a loop filter, a VCO, a programmable divider, a reference oscillator (typically a crystal reference source), and a fractional accumulator with ΣΔ modulation circuit to achieve the fine synthesizer step size without impacting the phase noise performance. The noise transfer functions for the various noise sources in the loop can be derived using conventional control theory [9, 10]. There are three additive noise transfer functions: one for the VCO noise, that is, the contributor of the synthesizer out-of-band noise, one for the ΣΔ modulator noise that could contribute to both in-band and out-of-band noise, and one for all other noise sources such as the PFD, CP, divider, and loop filter that are the contributors of the in-band noise. All in-band noise sources are referred back to the input of the PLL and shown as ϕnoiseI in Figure 4. The noise from the VCO is referred to the output and represented by ϕnoiseII in Figure 4, while the noise from the ΣΔ modulator is shown as ϕΣΔ . The noise transfer function (NTF) for in-band noise ϕnoiseI (s) is given by 





ϕnoise out (s) IKVCO /2π · C1 1 + RC1 s  = 2  . ϕnoiseI (s) s + IKVCO /2π · N Rs + IKVCO /2π · NC1 (25)

John W. M. Rogers et al.

7

As shown, the in-band noise transfer function has a lowpass characteristic. Note that for low-frequencies inside the loop bandwidth, the loop will track the input phase including the input phase noise. Therefore, this noise will be transferred to the PLL output. At higher offset frequencies, this noise is suppressed by the loop’s lowpass filter. Thus, the noise coming from the PFD, CP, divider, and loop filter contributes to the in-band noise at the PLL output. Also, note that the division ratio plays a very important role in this transfer function. Within the loop bandwidth, the in-band phase noise is magnified N times by the loop. Therefore, choosing smaller divisor value N will benefit the in-band noise reduction. The VCO noise transfer function is slightly different. In this case, setting the input reference and input noise source to zero, the VCO noise transfer function is given by ϕnoise out (s) s2  (s) = 2  . ϕnoiseII s + IKVCO /2π · N Rs + IKVCO /2π · NC1 (26) As shown, the VCO noise transfer function has a highpass characteristic. Thus, at low offsets inside the loop bandwidth the VCO noise is suppressed by the feedback loop, yet outside the loop bandwidth the VCO is essentially free running without noise attenuation. Thus, the out-of-band PLL noise approaches the VCO noise. The noise transfer function of the ΣΔ modulator is very similar to the in-band noise transfer function except an extra 1/N term in the numerator as the ΣΔ is not input-referred. Note that due to the highpass nature of the ΣΔ NTF, the order of the loop roll-off is very important. The noise shaping slope of an mth-order MASH ΣΔ modulation is 20(m − 1) dB/decade according to (24), while an nth-order lowpass loop filter has a roll-off slope of 20n dB/decade. Therefore, the order of loop filter must be higher than or equal to the order of the ΣΔ modulator in order to attenuate the out-ofband noise due to ΣΔ modulation. Thus, for instance, when calculating the effect of the ΣΔ modulator on out-of-band noise on the typical loop, it is necessary to include additional capacitor C2 in the loop filter as this will provide extra attenuation out of band. In this case, the ΣΔ noise transfer function to the output would be ϕnoise out (s) ϕΣΔ (s)





KVCO Kphase 1 + sC1 R    , = 2  s N C1 + C2 1 + sCs R + KVCO Kphase 1 + sC1 R (27) where Cs = C1 C2 /(C1 + C2 ). 5.

CIRCUIT-LEVEL PHASE NOISE COMPONENTS

The methods for dealing with phase noise will now be considered with application to an actual synthesizer RFIC design

case. The results of the analysis can then be verified against measurement data. The synthesizer to be considered was designed using a 47 GHz 0.5 μm BiCMOS process using primarily the CMOS part of the technology. The only exceptions were some high-speed bipolar CML in the divider and the output buffer circuits. The rest of the synthesizer including the VCO cores was all CMOS. It was designed for multiband WLAN applications, and had a reference frequency of 40 MHz, a fairly standard charge pump and PFD configuration with gain Kphase of 750 μA/2π, a multimodulus divider programmable between 64 and 127, and an LC-based VCO with a KVCO of approximately 120 MHz/V. The synthesizer was designed to generate carrier frequencies in the range from 3.2 to 3.3 GHz and from 4.1 to 4.3 GHz. The MMD gives a total division ratio of 86–88 and 102–108 under normal operating conditions and was controlled by a third-order ΣΔ modulator to provide the needed step size and noise shaping. The crystal oscillator used as a reference for this design had a QL of 8 × 104 and a noise floor of −150 dBc/Hz. The details of the actual circuit implementation will not be discussed in this paper, but are similar to those given in [11]. The raw VCO phase noise can be either predicted from a calculation [6] or else simulated with the aid of spectre or some other simulator. Output current noise from the charge pump/PFD combination can also be simulated or predicted from transistor level noise calculations. This simulation must be done using driving signals in the locked state to simulate accurately the amount of time the CP spends in the on state. This simulation can be used to predict how much noise current is on average produced by the circuit. Likewise simulations on the divider can be performed. The crystal oscillator is normally a commercially available part and data on its phase noise performance is often available from the manufacturer. The ΣΔ phase noise can be estimated from (24). Note that the maximum fractionality used in this design was 1/32. While this had an impact on the spurs of the system in different channels, the third-order ΣΔ has kept all the spurs below −50 dBc level such that the fractional spurs did not affect the phase noise of the system. Such simulations and calculations were performed for the sample design. The results of all raw phase noise due to circuit components are plotted in Figure 5. All phase noise is referred to the VCO output frequency for easy comparison of the relative importance of the phase noise sources. Next the optimal loop bandwidth for best phase noise performance must be determined. To do this the following must be implemented. (1) Plot all phase noise components. (2) Determine the intercept point of ΣΔ and VCO noise. (3) Compare it to the intercept between VCO noise and in-band noise (normally dominated by charge pump noise). (4) If the ΣΔ intercepts the VCO noise at a lower frequency than the in-band noise does, a higher-order ΣΔ is needed to prevent in-band noise degradation. Then make sure the higher-order ΣΔ noise intercepts the VCO noise at a higher frequency than the in-band noise does.

8

EURASIP Journal on Wireless Communications and Networking −80

Table 1: Loop filter components. (3) Crystal/CP intercept

CP no Cryst ise al no ise

(2) CP/VCO intercept

−110

1

10 100 Frequency (kHz)

1000

10 000

Figure 5: A plot of all raw phase noise components for the design referred to the VCO output frequency.

(5) Choose the intercept between the out-of-band noise (VCO noise) and the in-band noise (CP noise, reference noise, divider noise, etc.) as the loop optimal bandwidth. As an example, consider the plot of Figure 5. First the ΣΔ modulator used in the design must be considered. Since this noise increases with offset frequency, the loop bandwidth must be set low enough to properly attenuate this noise and prevent it from growing to dominate the phase noise of the design. Thus the loop bandwidth must be set lower than the intercept of the VCO noise and the ΣΔ noise (see point No.1 in Figure 5 at 600 kHz offset). For this design at frequencies between 300 Hz and 200 kHz, the in-band noise is dominated by CP, which is a fairly typical occurrence. This noise must also be weighed against the VCO noise and the intercept of these two noise sources (see point No.2 in Figure 5 at 200 kHz offset). Note that this point is lower than the ΣΔ intercept with the VCO noise and therefore it is the crucial point in this case that sets the loop bandwidth. Thus the loop bandwidth should be set at the point where these two noise sources are equal. Setting the loop bandwidth wider would result in the loop phase noise being dominated by the CP when it could be dominated by the lower VCO noise, and setting the loop bandwidth lower than this will result in the loop phase noise being dominated by the VCO, when it could be dominated by the lower CP/PFD noise. Thus, in this design the optimum loop bandwidth can be determined from the plot as the cross-over point between these two curves at an offset frequency of 200 kHz. Therefore the best possible out-of-band phase noise is the raw phase noise of the VCO and the inband phase noise will be dominated by the CP above a frequency of 300 Hz. Below this frequency the crystal oscillator noise will dominate the in-band noise (see point No.3 in Figure 5 at 300 Hz offset). 6.

3 nF 600 pF 600 Ω

COMPLETE PHASE NOISE ANALYSIS AND COMPARISON WITH MEASUREMENTS

Having determined the optimum loop bandwidth for best phase noise performance, the overall loop phase noise

−90 −100

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Figure 6: A plot of all phase noise including the effect of the loop.

performance can be predicted with the aid of the theory developed in Section 4. The loop filter components were chosen as shown in Table 1. A ratio of only 5 : 1 was chosen for C1 and C2 to help attenuate high-frequency ΣΔ phase noise and also to provide additional spur rejection. This can cause slight additional peaking in the phase noise at the loop corner frequency, but had a negligible impact on the integrated phase noise. Note that additional poles in the loop filter could lead to improved out-of-band performance, but since the loop filter was external in this experiment, this would have required additional package pins. The overall phase noise as well as all noise components are plotted in Figure 6 for a divider ratio of 87. The phase noise for this design integrated from 100 Hz to 10 MHz was predicted to be 0.44◦ rms. The synthesizer was fabricated and embedded with the rest of the circuitry that formed the WLAN transceiver. The back end of the process featured thick aluminum metallization designed to provide high-quality inductors. A die photo of the synthesizer is shown in Figure 7. This particular design implemented three VCO cores, however only two were required to cover all required WLAN frequencies. Each VCO had a tuning range of approximately 600 MHz. The synthesizer occupies an area of 2.3 mm by 1.4 mm. The synthesizer drew a current of 36 mA from a 2.75 V supply. The measured and simulated phase noise is compared in Figure 8 for a division ratio of 87 and in Figure 9 for a division ratio of 105. The comparison demonstrates that the overall PLL noise performance is predicted very closely by simulation and calculation. Thus, the proposed analytic model provides a rigorous model for analyzing PLL

John W. M. Rogers et al.

9 −60 −70 1R

PFD/CP

VCO2

VCO3

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ΣΔ

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Figure 7: Die photograph of the synthesizer. Figure 9: Comparison of measured and simulated phase noise for the 4.1–4.3 GHz band. The square dots are the simulated data. −60

Table 2: Comparison of measured and simulated phase noise.

Phase noise (dBc/Hz)

−70 −80 1R

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Measured phase noise

◦

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0.44 rms 0.50◦ rms

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1

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Table 3: Summary of synthesizer performance. Parameter

1

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1000

10000

Figure 8: Comparison of measured and simulated phase noise for the 3.2-3.3 GHz band. The square dots are the simulated data.

synthesizer phase noise performance. The model can serve as a design guide for synthesizer designers to optimize their circuits and meet their design goals prior to the expensive fabrication. The measured integrated phase noise of the WLAN synthesizer was 0.5◦ rms for the lower band and 0.535◦ rms for the upper band and that is close to the predicted phase noise. These results are summarized in Table 2. Owing to the accuracy of the proposed phase noise model, we were able to optimize the synthesizer circuits for improved noise performance prior to fabrication. The overall measured and simulated phase noise performance of the synthesizer RFIC is summarized in Table 3. Note that in this work the synthesizer was integrated with a superheterodyne front-end with an IF of approximately 1 GHz, and thus the LO frequencies are offset from the WLAN frequency bands. Translating the frequency of the LO up or down will improve or degrade the phase noise by the ratio the center frequency is scaled. The achieved phase noise is also compared to the most recently published WLAN synthesizer designs in Table 4. As shown, this design achieved one of the best phase noise performances for integrated WLAN transceiver RFICs. Note that in this table the phase noise quoted was for the

Technology VCO phase noise In-band phase noise Loop corner frequency Reference frequency Number of accumulator/MMD bits Order of ΔΣ accumulator Synthesizer step size Spurious Power supply Current consumption Synthesizer die area

Performance 0.5μ m BiCMOS −120 dBc/Hz @ 1 MHz −100 dBc/Hz @ 10 kHz 200 kHz 40 MHz 6 3rd 468.75 kHz < −50 dBc 2.75 V 36 mA 3.22 mm2

transceiver system and not simply of the synthesizers themselves. 7.

CONCLUSIONS

In this paper, a rigorous analytical model for determining the phase noise performance of PLL-based fractional-N ΣΔ synthesizers has been presented. Noise due to voltagecontrolled oscillators, charge pumps, crystal oscillators, phase-frequency detectors, charge pumps, loop filters, and ΣΔ modulator has been analyzed. Analyzing an example synthesizer RFIC designed for multiband MIMO WLAN applications has validated the theory. The analytical model achieved good agreements with measured synthesizer phase noise performance. The predicted phase noise of 0.44◦ rms and 0.50◦ rms at 3 GHz and 4 GHz bands, respectively,

10

EURASIP Journal on Wireless Communications and Networking Table 4: Comparison of synthesizer performance.

References

Frequency band (GHz)

Technology

Phase noise dBc/Hz @1 MHz

Phase noise dBc/Hz @10 kHz

Integrated phase noise of the system 0.7◦ rms, 5.3 GHz 1 kHz–10 MHz

[12]

2.4, 5.1–5.8

0.25 μm CMOS

−115

−105

[13]

5.1–5.8

0.18 μm CMOS

−115

−92

0.8◦ rms 1 kHz–10 MHz

[14]

5.1–5.3

0.18 μm CMOS

−110

−92

1.5 ∼ 2◦ rms 10 kHz–10 MHz

2.4, 5.1–5.3

0.5 μm BiCMOS

−120

−98

0.4◦ rms, 2.4 GHz 0.7◦ rms, 5.3 GHz 100 Hz–10 MHz

This work

agreed closely with the measured results of 0.5◦ rms and 0.535◦ rms. ACKNOWLEDGMENTS The authors are deeply indebted to their colleagues at Cognio for invaluable advice and support during this work. Thanks go especially to R. Griffith for CAD support and F. Qing and Z. Zhou for layout support. This work would also not have been possible without the support of Dave Rahn. REFERENCES [1] T. A. Riley, M. Copeland, and T. Kwasniewski, “Delta-sigma modulation in fractional-N frequency synthesis,” IEEE Journal of Solid-State Circuits, vol. 28, no. 5, pp. 553–559, 1993. [2] J. N. Wells, “Frequency Synthesizers,” United States Patent, no. 4609881, September, 1986. [3] B. Miller and B. Conley, “A multiple modulator fractional divider,” in Proceedings of the 44th Annual Symposium on Frequency Control, pp. 559–568, Baltimore, Md, USA, May 1990. [4] B. Muer and M. S. J. Steyaert, “A CMOS monolithic ΔΣ controlled fractional-N frequency synthesizer for DCS-1800,” IEEE Journal of Solid-State Circuits, vol. 37, no. 7, pp. 835–844, 2002. [5] D. B. Leeson, “A simple model of feedback oscillator noise spectrum,” Proceedings of IEEE, vol. 54, no. 2, pp. 329–330, 1966. [6] J. W. M. Rogers and C. Plett, Radio Frequency Integrated Circuit Design, Artech House, Norwood, Mass, USA, 2003. [7] Y. Watanabe, T. Okabayashi, S. Goka, and H. Sekimoto, “Phase noise measurements in dual-mode SC-cut crystal oscillators,” IEEE Transactions on Ultrasonics, Ferroelectrics and Frequency Control, vol. 47, no. 2, pp. 374–378, 2000. [8] V. F. Kroupa, “Jitter and phase noise in frequency dividers,” IEEE Transactions on Instrumentation and Measurement, vol. 50, no. 5, pp. 1241–1243, 2001. [9] V. F. Kroupa, “Noise properties of PLL systems,” IEEE Transactions on Communications, vol. 30, no. 10, pp. 2244–2252, 1982. [10] W. F. Egan, Frequency Synthesis by Phase Lock, John Wiley & Sons, New York, NY, USA, 2000. [11] J. W. M. Rogers, F. F. Dai, M. S. Cavin, and D. G. Rahn, “A multiband ΔΣ fractional-N frequency synthesizer for a MIMO WLAN transceiver RFIC,” IEEE Journal of Solid-State Circuits, vol. 40, no. 3, pp. 678–689, 2005.

[12] M. Zargari, S. Jen, B. Kaczynski, et al., “A single-chip dual-band tri-mode CMOS transceiver for IEEE 802.11a/b/g WLAN,” in Proceedings of IEEE International Solid-State Circuits Conference (ISSCC ’04), vol. 1, pp. 96–515, San Francisco, Calif, USA, February 2004. [13] J. Bouras, S. Bouras, T. Georgantas, et al., “A digitally calibrated 5.15-5.825GHz transceiver for 802.11a wireless LANs in 0.18μm CMOS,” in Proceedings of IEEE International SolidState Circuits Conference (ISSCC ’03), vol. 1, pp. 352–498, San Francisco, Calif, USA, February 2003. [14] P. Zhang, T. Nguyen, C. Lam, et al., “A direct conversion CMOS transceiver for IEEE 802.11a WLANs,” in Proceedings of IEEE International Solid-State Circuits Conference (ISSCC ’03), vol. 1, pp. 354–498, San Francisco, Calif, USA, February 2003. John W. M. Rogers received the Ph.D. degree in 2002 in electrical engineering from Carleton University, Ottawa, Canada. Concurrent with his Ph.D. research, he worked as part of a design team that developed a cable modem IC for the DOCSIS standard. From 2002 to 2004 he collaborated with Cognio Canada Ltd. doing research on MIMO RFICs for WLAN applications. He is currently an Assistant Professor at Carleton University. He is the coauthor of Radio Frequency Integrated Circuit Design and Integrated Circuit Design for High Speed Frequency Synthesis. His research interests are in the areas of RFIC and mixedsignal design for wireless and broadband applications. Dr. Rogers has been the recipient of an IBM faculty partnership award in 2004, an IEEE Solid-State Circuits Predoctoral Fellowship in 2002, and received the BCTM Best Student Paper Award in 1999. He holds five US patents and is a Member of the Professional Engineers of Ontario and the IEEE. He is currently serving as a Member of the Technical Program Committee for the Custom Integrated Circuits Conference. Foster F. Dai received the B.S. degree in physics from the University of Electronic Science and Technology of China (UESTC) in 1983. He received a Ph.D. degree in electrical engineering from The Pennsylvania State University in 1998. From 1997 to 2000, he was with Hughes Network Systems of Hughes Electronics, Germantown, Maryland, where he was a Member of Technical Staff in VLSI engineering,

John W. M. Rogers et al. designing analog and digital ASICs for wireless and satellite communications. From 2000 to 2001, he was with YAFO Networks, Hanover, Maryland, where he was a Technical Manager and a Principal Engineer in VLSI designs, leading high-speed SiGe IC designs for fiber communications. From 2001 to 2002, he was with Cognio Inc., Gaithersburg, Maryland, designing RFICs for integrated multiband wireless transceivers. In August 2002, he joined the faculty of Auburn University, where he is currently an Associate Professor in electrical and computer engineering. His research interests include VLSI circuits for digital, analog, and mixed-signal applications, RFIC designs for wireless and broadband communications, ultra-high frequency synthesis and analog and mixed signal built-in self-test (BIST). He is the coauthor of the book Integrated Circuit Design for High-Speed Frequency Synthesis (Artech House Publishers, February, 2006). Calvin Plett has been with Carleton University, Ottawa, Canada since 1986 and is now an Associate Professor. Prior to 1982, he worked for a number of companies including nearly four years with Atomic Energy of Canada, and shorter periods with Xerox, Valcom, Central Dynamics, and Philips. From 1982 to 1984, he worked with BellNorthern Research doing analog circuit design. For some years he did consulting work for Nortel Networks in RFIC design. For the last number of years he has been involved in collaborative research, which involved numerous graduate and undergraduate students and various companies including Nortel Networks, SiGe Semiconductor, Philsar, Conexant, Skyworks, IBM, and Gennum. He has authored or coauthored more than 60 technical papers which have appeared in international journals and conferences. He is a coauthor of Radio Frequency Integrated Circuit Design and a coauthor for Integrated Circuit Design for High-Speed Frequency Synthesis. His research interests include the design of analog and radio-frequency integrated circuits, including filter design, and communications applications. He is a Member of AES, the PEO, and a Senior Member of the IEEE. He was the coauthor of papers that won the Best Student Paper Awards at BCTM 1999 and at RFIC 2002. Mark S. Cavin received a BSEE from Virginia Tech in 1988 and MSEE in 1991 from the University of Central Florida. Following completion of BSEE he worked at David Taylor Research Center in the area of ship electromagnetic signature analysis. From 1990 to 1991, he worked on his MSEE at the University of Central Florida under a Motorola Research Grant on SAW device package electrical characterization and oscillator design. From 1991 to 1995, he was a Staff and Lead Oscillator Design Engineer in the Oscillator and Subsystems group at Sawtek. His design and research involved high performance commercial and military surface acoustic and surface transverse wave frequency sources. From 1996 to 2001, he was with RFMD. There he was involved in the development of transceivers for ISM band applications. In 2001 he joined Tality and was involved in CMOS PLL designs for Bluetooth and cable set top applications. From 2002 to 2004 he was at Cognio where he was involved in the design of a MIMO WLAN transceiver. Currently he is with Alereon Inc. in Austin Texas. His technical interests include low power transceivers, frequency synthesizer design, power amplifier design.

11

Hindawi Publishing Corporation EURASIP Journal on Wireless Communications and Networking Volume 2006, Article ID 24853, Pages 1–26 DOI 10.1155/WCN/2006/24853

Noise and Spurious Tones Management Techniques for Multi-GHz RF-CMOS Frequency Synthesizers Operating in Large Mixed Analog-Digital SOCs Adrian Maxim Maxim Inc., Austin, TX 78735, USA Received 17 October 2005; Revised 4 May 2006; Accepted 4 May 2006 This paper presents circuit techniques and power supply partitioning, filtering, and regulation methods aimed at reducing the phase noise and spurious tones in frequency synthesizers operating in large mixed analog-digital system-on-chip (SOC). The different noise and spur coupling mechanisms are presented together with solutions to minimize their impact on the overall PLL phase noise performance. Challenges specific to deep-submicron CMOS integration of multi-GHz PLLs are revealed, while new architectures that address these issues are presented. Layout techniques that help reducing the parasitic noise and spur coupling between digital and analog blocks are described. Combining system-level and circuit-level low noise design methods, low phase noise frequency synthesizers were achieved which are compatible with the demanding nowadays wireless communication standards. Copyright © 2006 Adrian Maxim. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

1.

INTRODUCTION

The major trend in nowadays wireless transceivers is towards single-chip CMOS integration. Designing low phase noise and low spurious tones frequency synthesizers that operate on the same die with a large and noisy digital core faces numerous system- and circuit-level challenges. There exist two main mechanisms of parasitic noise and spurious tones coupling to the PLL building blocks: magnetic coupling and electric coupling. The magnetic coupling can appear between two bondwires, between a bondwire and the VCO or the VCO buffer on-chip spiral inductors, or between a bondwire and a metal interconnect line that creates a large magnetic loop. Electric coupling may appear either through the supply lines or via the substrate. Achieving a low phase noise PLL requires a good understanding of all these coupling mechanisms and adopting appropriate circuit- and system-level techniques that result in coupling minimization. A large mixed analog-digital SOC often has several digital supply bondwires that carry large current spikes which may couple to the bondwires providing the supply or signal to the sensitive PLL analog blocks. Increasing the distance between the aggressor bondwire and the receiving one, while ensuring a 90◦ orientation between them, is the most effective way to reduce the magnetic coupling. One example of

critical magnetic coupling is between the bias bondwire of the voltage controlled oscillator (VCO) and any other aggressor bondwire, which may bring a significant variation of the local VCO supply. The nonlinear capacitance connected in parallel with the oscillator’s LC tank determines a finite supply pushing gain. Thus the supply noise and spurs are upconverted around the carrier, degrading the VCO phase noise performance. To solve this issue, it has become a standard solution to bias the oscillator from a dedicated high PSRR regulator [1–4]. Another often encountered example is the coupling to the VCO control line in the applications that use an off-chip loop filter [5, 6]. Bringing the sensitive VCO control node off-chip is very dangerous since any magnetic coupling to the corresponding bondwire directly modulates the VCO frequency and thus results in spur and phase noise degradation. This is the main reason that on-chip PLL loop filters are always preferred. Present design proposes a multiregulator PLL architecture for 802.11 a/b/g SOC applications, in which every single block from the PLL top level is biased from a dedicated series or shunt regulator. These regulators reduce both the impact of bondwire coupling and the parasitic noise and spur coupling between different PLL building blocks. If all analog and digital blocks are built in the same silicon substrate, a substantial noise coupling appears between them. To solve this

EURASIP Journal on Wireless Communications and Networking

Series reg.

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Figure 1: PLL top-level diagram including supply voltage partition and regulation.

troublesome issue, both the sensitive analog blocks and the noisy digital blocks were built in isolated substrates that are separated from the global chip substrate with deep N-well layers. Modern deep-submicron CMOS processes often offer dual gate oxide thicknesses: thin gate oxide FETs that have a high operating frequency and a relatively low breakdown voltage and thick gate oxide FETs that have a medium operating frequency but a much larger breakdown voltage. Present design takes advantage of both device types to optimize the overall PLL phase noise performance. The signal slew rate assumes very different values in the PLL building blocks (e.g., sinusoidal signal in XTAL oscillator and multi-GHz VCO and square-wave in the clock squaring buffers and the digital dividers). Therefore the impact that a given amount of supply noise has on these blocks can drastically differ. This paper presents a systematic design methodology to select the regulator type and architecture for each PLL building block. The oscillator is the most sensitive analog block inside the PLL frequency synthesizer. Its tuning gain plays a crucial role in the PLL phase noise performance. The tuning gain needs to be high enough to cover the entire frequency range allocated to the given communication standard and also compensate for the process, temperature, and supply (PTV) frequency variations. The continuous shrinking of the supply voltage in modern deep-submicron CMOS processes, together with the progressive increase towards multiGHz range of the operation frequency, has resulted in an ever high VCO tuning gain. A large VCO gain results in a degraded PLL phase noise due to a larger contribution of the PLL front-end stages noise and coupled spurious tones. A standard way to reduce the VCO gain is to break the frequency range into several subranges and use for each of them the entire tuning voltage range [3, 4, 7]. This paper proposes a high-resolution frequency calibration network to compensate for process variation, while a virtually constant varactor tuning gain is achieved by using several accumulation MOS varactors connected in parallel and having their C(V ) characteristics shifted one from the other, such that the individual gain peaks are distributed over the entire tuning range.

Power supply partitioning and filtering plays a key role in a low phase noise frequency synthesizer. Several low-voltage drop active RC filters are proposed to improve the PSRR of the headroom constrained PLL building blocks. For the cases when using only a filter or a regulator is not enough to provide the required PSRR, a cascade filter-regulator or a dualregulator architecture was proposed. Most existing PLLs use one [5, 6, 8] or two [3, 9, 10] series regulators to bias the PLL building blocks. This paper presents a multiregulator PLL architecture together with a rigorous methodology to select the optimum regulator architecture for each PLL building block that minimizes the noise and spurious tones coupling when operating in a large mixed signal SOC. 2.

PLL TOP LEVEL AND POWER SUPPLY PARTITIONING

Figure 1 presents the top-level diagram of the proposed low noise charge-pump PLL, including a crystal oscillator (XTAL) that provides a low phase noise sinusoidal reference clock to the PLL, a reference clock squaring buffer (REFBUF) that converts the reference sine-wave into a squarewave, the phase-frequency detector (PFD) that compares the phase of the reference and feedback clocks and generates the up/down control signals for the charge-pump (CP), a loop filter (LF) that provides the loop stabilizing zero and reduces the ripple at the voltage controlled oscillator (VCO) control line, the VCO-BUF buffer that increases the edge speed of the multi-GHz output clock, the feedback divider (Div.N) that sets the reference frequency multiplication factor ( fout = N ∗ fref ), and the divider buffer (Div.N-BUF) that drives the second input of the PFD. In addition to these main loop circuits, the PLL also has a quadrature clock generator (I/Q gen.) that performs a divide by two of the VCO output clock frequency and provides two clocks that are precisely at 90◦ phase difference, and a test circuit that brings at a test pin the signals at different analog and digital nodes from the PLL signal path for debugging purposes. Investigating the PLL top-level diagram, one may identify two types of building blocks: digital circuits (PFD, Div.N, REF-BUF, VCO-BUF) and sensitive analog circuits (XTAL,

Adrian Maxim CP, LF, and VCO). Many large mixed analog-digital SOCs are pad-limited, allowing only a single supply (VDD, GND) for the entire PLL. When both the analog and digital PLL building blocks are biased from the same supply line, a particular care needs to be taken in order to avoid the noise and spur contamination of the global supply, which may result in noise coupling between the digital and analog circuits. In low phase noise PLLs it is sometimes critical to avoid also the coupling between two digital blocks. One such example is the noise coupling between the feedback divider (Div.N) that may generate tones that are not harmonically related to the reference frequency and the reference clock squaring buffer (REF-BUF) that can downconvert these tones into the PLL bandwidth, leading to high-level spurs. Another situation encountered in many applications (presented in Figure 1) is when two supply lines are available to the PLL: one that biases the analog blocks and the second one that biases the noisy digital circuitry. In this case the designer needs to select the optimum boundary between the analog and digital power domains. The best choice for the analog-digital supply domain interface is at a high impedance node where the driving is done in current mode, as is the case for the charge-pump output node. Although the analog charge-pump is placed on the digital supply, using a current mode drive at the boundary between the two power domains, the noise between the analog and digital supplies is prevented from coupling into the signal path, as may be the case when the partition is done at a voltage-driven node (e.g., the up/down PFD output control signals). The key target of the proposed low noise PLL power supply partitioning is to prevent parasitic noise and spur coupling between the analog and digital blocks. To achieve this, the sensitive analog circuits were biased from high forward PSRR series regulators, while the global supply contamination with digital switching noise was prevented by biasing the digital circuits with shunt regulators that provide a high value reverse PSRR. Starting from the PLL front end, the crystal oscillator does not generate significant supply current spikes. Its bias current is in fact held constant by the automatic amplitude control loop (AAC). Therefore the XTAL oscillator can be biased with a series regulator which does not provide any reverse PSRR rejection. The only reverse PSRR achieved by a series regulator is ensured by its load filtering capacitance. However, the noise and spurious tones reaching the XTAL oscillator and its output buffer (REF-BUF) can seriously degrade the PLL phase noise performance. Therefore a very low noise and high PSRR regulator is required. This paper proposes a novel dual-regulator architecture to bias both the XTAL oscillator and the VCO. The reference and Div.N buffers dominate the in-band PLL phase noise. Their noise and spurs are directly magnified by the PLL gain (= N). It is therefore crucial to use a very low noise and high forward PSRR regulator for REF-BUF as well. Furthermore, the supply current spikes of the fast switching buffers do not need to be closed directly onto the global supply, since this may cause reference spur degradation through parasitic coupling to other sensitive PLL blocks (e.g., chargepump and loop filter). A shunt regulator was used to ensure

3 both a high forward and reverse PSRR rejection. Bandgap referenced regulators usually have a relatively large in-band noise, potentially degrading the REF-BUF phase noise performance through a modulation of its trip point. This design uses a very low noise VT /R reference to generate the required PLL low noise reference currents and voltages. The PFD has a much lower phase noise contribution due to the fact that its clock edges are very fast both at its input and also at its internal nodes. A high edge slope reduces linearly both the impact of the device internal noise and the supply injected noise. Therefore the usage of a regulator is not needed for the PFD from the forward PSRR point of view. However, due to the fact that the required supply voltage for the thin oxide gates (1.3 V) is smaller than the available system supply (2.5 V) and that it is preferable not to close the large current spikes of the fast switching digital gates onto the global supply, a second shunt regulator was used to bias the PFD. For the charge-pump two contradicting requirements need to be satisfied. On one side, the voltage swing at the CP output needs to be as large as possible in order to reduce the VCO gain and thus decrease the noise and spur coupling from the PLL front end. This requires a high value supply voltage to the charge-pump. On the other side, minimizing the CP spurs downconversion mechanism due to its chopping action requires the usage of a well filtered or regulated local supply that reduces the effective supply voltage available to the CP. A regulator usually takes a much larger headroom in comparison with a simple RC filter (2Von + VT for NFET output and Von for PFET output). Therefore in this design an active RC filter was selected to improve the CP supply noise rejection. The active loop filters are taking an almost constant supply current in lock conditions, allowing the usage of a series regulator to bias them [4, 11]. However, the presence of a supply line always comes with an elevated supply noise sensitivity. In the case of passive loop filters, there is no need for a regulator as they do not have a supply line. This paper presents a passive feedforward loop filter that significantly reduces the size of the on-chip loop filter capacitance, while requiring no supply line [12]. The VCO is the most sensitive analog block from the entire PLL design. Any supply noise or spur injection that reaches its local supply line is upconverted around the carrier by the supply voltage frequency pushing mechanism [13, 14]. It is now standard to bias the VCO from a dedicated high forward PSRR series regulator [1–4]. The VCO output buffer (VCO-BUF) which squares up the sine-wave looking clock generated by the oscillator leads to high amplitude supply current spikes due to the fast charging and discharging of the load capacitance. However, these current spikes are perfectly synchronous with the oscillator frequency and therefore cannot degrade VCO’s phase noise. Hence it is not necessary to isolate the VCO-BUF from the clean analog supply with the help of a shunt regulator, as was done for the other digital blocks. However, the voltage level required by the VCO-BUF and the following I/Q generator that use thin gate oxide FETs is lower than the one used by the VCO (1.3 V

4

EURASIP Journal on Wireless Communications and Networking

versus 1.5 V), requiring the usage of a separate series regulator. The VCO needs to operate at the maximum amplitude allowed by the device breakdown in order to minimize its phase noise. The device mismatches in the VCO-BUF may result in a significant pulse-width distortion of the resulting square-wave multi-GHz clock. This leads to a large secondorder harmonic in the buffer supply current. If this secondorder harmonic of the VCO frequency leaks to the I/Q generator, a large I/Q phase mismatch may result. A passive Rb , Cb filter was placed in series with the VCO-BUF supply line in order to close locally to ground its second-order harmonic current. Finally, the feedback divider (Div.N) that generates most of the internal PLL switching noise is biased from a shunt regulator having a large reverse PSRR, which prevents the contamination of the global PLL supply with tones created by the divider switching. Analyzing the PLL top-level diagram presented in Figure 1, one may conclude that every single building block of the PLL signal path that needs a supply line uses an appropriate filter or regulator. The digital blocks are using shunt regulators that close locally their large supply current spikes, while the sensitive analog blocks use series regulators with large forward PSRR values to minimize the supply and spur injection. Two supply voltages are available to the present SOC: 1.8 V used by the noisy digital core and 2.5 V used by the analog blocks in the signal path (LNA, mixers, VCOs). The frequency synthesizer uses two dedicated supply lines (see Figure 1). The PLL front end consisting of the digital building blocks (dividers, clock buffers, phase-frequency detector, and switched-current charge-pump) uses the 1.8 digital supply, since the clock edges are enough fast to be insensitive to the residual supply noise obtained after the high PSRR regulators. These digital blocks are built with thin gate oxide FETs that require a no larger than 1.3 V supply. Using a 1.8 V supply and high reverse PSRR shunt regulators results in a power efficiency level around 50%, but offers in return a good rejection of the supply noise and spurious tones. It is important that the crystal oscillator and the reference clock squaring buffer are connected at the same ground line and there is no potential difference between their local grounds. Any noise voltage between the XTAL oscillator and its REF-BUF buffer may significantly degrade the reference clock phase noise since the slew rate of the input buffer signal (sine-wave) is rather low. A star connection of the two local grounds and a wide metal line (low series resistance) ensures that they are precisely at the same potential. However, biasing the sensitive XTAL oscillator from the noisy digital supply requires a very high PSRR dual-regulator architecture to avoid the supply spur degradation. Separating the supply of the noisy digital building blocks from the sensitive oscillator prevents the contamination of the supply with reference frequency tones that may degrade the reference spur level. The front-end PLL regulators do not need a large bandwidth, since the noise and spurs coupled at the PLL input are strongly attenuated by the synthesizer lowpass-filter transfer function. This results in lower current levels in regulator’s amplifier, improving its power efficiency.

The shunt regulators used to bias the PFD and the PLL feedback divider have intrinsically a significantly lower power efficiency when compared to the series regulators. This is because their DC current needs to be larger than the average digital current in the worst-case process, temperature, and supply voltage corner. A digital calibration of the shunt regulator DC current based on the specific process corner and average die temperature lead to a power efficiency close to 50% even for the shunt regulators. The overall power efficiency of the PLL is around 45%. The low phase noise reference XTAL oscillator and the output multi-GHz oscillator with their clock buffers need a more complex regulation scheme (two cascaded regulators or one regulator and a cascaded RC filter) to achieve the targeted noise and spur specifications. The XTAL oscillator amplitude is around 0.8 V, allowing the use of a dual regulator within a 1.8 V supply headroom. In contrast the output oscillator amplitude needs to be much larger (3 V peak-to-peak) to achieve a low phase noise, and therefore requires the use of the 2.5 V supply if a dual-regulator architecture is to be implemented. This lowers the power efficiency of the oscillator series regulator below the 50% level. In an RF frequency synthesizer a lower power efficiency is always traded for better spur and phase noise performance. This gives one of the fundamental performance limitations for the portable application (battery operated) synthesizers. In wired applications the power efficiency is not that strongly constrained, and it is generally sacrificed to achieve a better synthesizer performance. The CMOS process scaling to 90 nm or 65 nm is accompanied by a supply voltage reduction (e.g., to 1 V), reducing the PLL power dissipation. The higher device fT leads to faster clock edges and therefore a lower sensitivity to supply noise and spurious tones. This relaxes somewhat the specifications for the biasing regulators, further improving their power efficiency. However, the increase of the operating frequency in emerging wireless application up to 5 GHz, or in some cases beyond 10 GHz diminishes the power saving offered by the CMOS process scaling. 3.

SUPPLY FILTERS

One solution to reduce the supply noise and spurious tones injection into the sensitive PLL blocks is to use a supply filter. Their advantages over a regulator are simplicity, smaller voltage drop, and lower die area. Figure 2(a) presents a standard passive RC filter. A first-order RC filter is shown, but higher-order filters can be also used for achieving a sharper frequency roll-off characteristic. In order to achieve an effective supply noise attenuation, it is required that the corner frequency of the filter is with at least one decade lower than the major supply noise frequency spectrum. Often the supply noise can have frequencies as low as few MHz, or even hundreds of KHz, forcing the RC filter corner frequency down to tens of KHz. The main drawback of the passive RC filter is that the DC current of the supplied block passes through the series resistor R f . To prevent a severe reduction of the local supply voltage going to the PLL block, due to the supply current variation, a relatively low R f value is needed. Usually the

Adrian Maxim

5 VDD

VDD

VDD

Rf

Rf

Ibias

Mfol Cf

Mfol

Rf

Cf

Cf

Ishift PLL block

PLL block (a)

(b)

PLL block (c)

Figure 2: (a) Passive RC filter; (b) and (c) active RC filters.

tolerated voltage drop on R f is only few hundred mV, resulting in a large C f capacitance that can take a significant die area. Active RC filters can be used to solve this problem [3, 4]. They consist as shown in Figure 2(b) of a low corner frequency R f , C f filter and an Mfol source follower. In this case the DC current of the PLL block does not go through the R f resistor and therefore a large R f value can be assumed. The supply current of the PLL block is provided by the Mfol active device that follows the filtered gate voltage as the local supply to the load block. The gate leakage of the Mfol follower is negligible, allowing for R f a multi-MΩ value. The upper limit for R f is set by the required noise level at the generated local supply. In circuits with high supply noise sensitivity this may be a stringent limiting factor (e.g., reference clock squaring buffer). The main drawback of the standard active RC filter is the large DC voltage drop equal to VT + Von of the Mfol follower. The Von component can be reduced by using a large W/L aspect ratio for Mfol . However, this increases its Cgd parasitic capacitance that in turn limits the high-frequency PSRR (PSRRHF = Cgd /(Cgd + C f )). A more attractive implementation of the active RC filter can be achieved by using native (zero-VT ) NFETs [11]. In this case the voltage drop on the filter is only a Von voltage that can be restricted to few hundred mV. Depending on the selected CMOS process, the threshold voltage of the native devices can be either slightly positive or slightly negative. If VT is always higher than zero for all process and temperature corners, then the Mfol device is guaranteed to be in saturation region when diode-connected by the R f resistor. However, if the threshold voltage can assume a negative value, then Mfol will be in triode region, preventing the supply noise filtering (Mfol is in fact a low value resistance that transfers the noise from the global supply line to the local PLL supply). To avoid the crashing of Mfol , a small Ishift current can be drawn out of the R f , C f filter, such that the VGD voltage assumes an enough high negative value to prevent the triode mode operation of the Mfol follower. In many situations the large body effect on Mfol (their body is the global p-substrate of the die, which is connected to ground) may be enough to guarantee an always positive VT for the native NFETs. Using such an active RC filter built with a native NFET results in a very low-voltage drop (100–200 mV), while providing a PSRR in excess of 40 dB at medium and high

frequencies. However, this circuit does not have any rejection at DC and frequencies lower than the R f , C f corner frequency. This may be an issue in the cases when DC-DC converters having significant spurs at tens of KHz are used to bias the SOC. Figure 2(c) presents an alternative architecture for the active RC filter that has a large supply rejection starting from DC. In this case the gate of Mfol is biased from a voltage achieved by injecting a bias current Ibias into an R f , C f filter. Its main drawback is that the output voltage is set by Ibias ∗ R f − VGS (Mfol ) and does not track the global PLL supply. In some applications it is beneficial that the additional headroom available at higher supply voltages is provided as extra voltage range to the headroom constrained PLL blocks. However, this last active RC filter architecture is very useful in filtering the local supply to circuits that are sensitive to low-frequency supply noise (e.g., the oscillators). 4.

BANDGAP AND VT REFERENCE GENERATORS

Reducing the supply noise injection in a frequency synthesizer operating in a large mixed signal IC mandates the usage of a dedicated regulator for every single PLL building block. An isolation regulator can successfully reject the supply noise and spur injection, but it has noise of its own that may impact the VCO phase noise performance. Achieving a low noise regulator needs a low noise reference voltage generator. The most common way to generate a reference voltage is using a bandgap circuit [1–11]. Figure 3(a) shows a local bandgap voltage replica circuit that uses an Ibg = Vbg /R current provided by the V -to-I converter of the master bandgap block that is injected into an Rbg resistor that closely matches the R resistor (in terms of unit resistor cells) used in the master bandgap circuit. Bandgap references have a good process and temperature stability, but come with a large output noise. The wideband noise can be filtered out with an RC filter, at the price of a large required die area due to the high value capacitance necessary to limit the total integrated white (thermal) noise to a low KT/C term. Rejecting the 1/ f noise requires a very low corner frequency, which may not be feasible to implement on-chip. This design proposes an alternative way of achieving a low noise reference voltage using a VT referenced circuit, as shown in Figure 3(b). The Mref device provides the reference VT voltage, which creates an Iref = VT /Rref current through the Rref resistor. The Mcasc

6

EURASIP Journal on Wireless Communications and Networking Iref

Ibg Rn

Rbg

Vref

Mcasc

Rdeg Rbias

Mp

Rdeg Mp Mp

Rdeg Mp

Mp

Cn

Mp

Cn Mref

Rref

Cc Rcal (a)

(b)

v

Rn Vref Md Md

(c)

Figure 3: Reference circuits: (a) bandgap reference, (b) V T/R reference, and (c) improved PSRR V T/R reference.

cascode device boosts the output impedance of the current generator, helping to improve its PSRR. If enough loop gain is provided to the local feedback loop (Mref and Mcasc ), the noise of the output current is dominated by the thermal noise of the Rref resistor. Using a large degeneration resistor value reduces the reference current noise at the expense of a low current value. A reference voltage was generated by injecting the Iref = VT /Rref current into a low impedance load constituted by two diode-connected MOSFET devices (Md ) as shown in Figure 3(c). The VT /R current generator can be biased using either an input current (Ibias ) or a bias resistor (Rbias ). For a given headroom voltage and current value the noise of a bias resistor is significantly lower than the one √ of a current mirror√(e.g., < 1 pA/ Hz for a 20 KΩ resistor, versus about 6 pA/ Hz for a 100 μA current source). However, using an Rbias resistor brings a strong supply voltage dependence of the input current (Ibias = (VDD − 2VGS )/Rbias ). This leads to a degraded PSRR of the current generator, increasing the sensitivity to supply noise injection. Three such VT /R current cells were connected in cascade to improve the PSRR of the output reference voltage (see Figure 3(c)). Each VT /R cell contributes at least 20–25 dB rejection of the input bias current supply dependence, resulting in an overall PSRR well in excess of 60 dB. The PSRR is no longer dominated by the input bias current, but is set by the resistive divider given by the output impedance of the turnaround PFET current mirror (M p ) and the low impedance of the diodeconnected load devices (Md ). Resistive degeneration (Rdeg ) was used in the PFET current mirrors to reduce its noise contribution and improve the PSRR. The Cc compensation capacitance provides a dominant pole to the local feedback loop (Mref , Mcasc ), ensuring a phase margin in excess of 60◦ . The low noise performance of the VT /R current generator comes at the price of a wide process and temperature variation. Optimizing the VCO phase noise performance requires the maximization of the oscillating amplitude, which in turns requires an accurate supply voltage level. A digital controlled resistor (Rcal v ) was used to calibrate the VT referenced supply voltage (Vreg ) to an accurate bandgap reference. To further reduce the noise and supply sensitivity of the output VT /R reference current, a supplementary Rn , Cn noise filter was inserted in series with the output current leg.

5.

SUPPLY REGULATORS

Active RC filters are generally recommended for low current blocks, when simplicity comes on the first place. The relatively large output impedance of the active RC filters (1/gm ) and also the increased voltage drop at large load currents due to an elevated Von prevents their usage for biasing high supply current blocks. In these situations a regulator is more appropriate for reducing the supply noise injection. However, the regulator requires a larger voltage drop in comparison with a filter. One solution to achieve a high PSRR, while still using a moderate headroom, is using a cascade RC filter and series regulator as presented in Figure 4. The R f , C f , Mfol active filter helps improving the PSRR of the series regulator at high frequencies (above the regulator’s bandwidth), where the PSRR drops sharply. At DC and low to medium frequencies (inside the regulator bandwidth) the active filter is not helping much, most of the PSRR being ensured by the regulator itself. The series regulator uses a native (zero-VT ) NFET output device (Mnreg ) to provide the high load current. Reducing the PSRR degradation caused by the Cgd (Mnreg ) was achieved by using a PFET follower (Mpfol ) that drives with a low impedance the gate of the output device. Its bulk needs to be connected at the source in order to avoid the substrate noise injection through the body effect. The Mpfol source follower helps also increasing the headroom available to the folding cascode current mirrors and allows the implementation of the Cc compensation capacitance with a lower area thin gate oxide NFET. A high gain amplifier is realized with a folded cascode NFET input differential pair (Min). The reference voltage for the series regulator was generated with an Ibg = Vbg /R current injected into a matched Rbg resistor. The Cpsrr capacitor helps improving the PSRR of the reference voltage, while the Rn , Cn filter reduces the noise contribution of the local bandgap voltage generator (Ibg , Rbg ). Using a cascaded RC filter and regulator, a relatively high PSRR (> 50 dB) was achieved up to frequencies of tens of MHz. This is sufficiently high to reject the supply noise even in high bandwidth PLLs (several MHz). The cascade filterregulator architecture can be applied to the noise sensitive

Adrian Maxim

7 VDD

VDD Active RC filter

Rf Mnfol

Passive or active RC filter

Ishift

Cf

Mp Regulator Vcp PLL block

Mnreg

Mcp Mcn

Vcn

Cc

Mpfol

Ibg Rn Rbg (a)

Min Cn

Mn Series regulator

PLL block

(b)

Figure 4: Cascaded filter and regulator: (a) principle; (b) implementation.

blocks from the PLL front end that have a lowpass or bandpass transfer function to the output clock phase noise. In high-frequency VCOs the percentage of the tank capacitance coming from the nonlinear device parasitic capacitance is large, leading to a higher supply pushing gain (Kvdd ) in comparison with the low-frequency VCOs, where most of the tank capacitance is contributed by the linear MIM or metal capacitors. Furthermore, in large mixed signal SOCs the supply voltage is highly contaminated with spurious tones coupled both magnetically and electrically from the switching digital circuits. Using an off-chip filtered supply dedicated only to the low noise oscillator eliminates the board-level noise coupling, but it does not solve the supply noise injection through magnetic coupling between the different IC bondwires. On-chip filtering usually requires a very large die area. Increasing the distance between the sensitive analog pads and the aggressor digital pads and using a 90◦ orientation between the corresponding bondwires helps reducing the coupling. Flip-chip assemblies can be also used to avoid the bondwire coupling, but at a significant cost increase penalty. Multi-GHz VCOs have intrinsic supply pushing gains of several MHz/V. Bandgap√references come with noise levels around few hundred nV/ Hz. The resulting supply noise injection limits the VCO phase noise to less than 80 dBc/Hz at 100 KHz frequency offset, value that is not acceptable for many modern communication applications. Achieving less than −100 dBc/Hz VCO phase noise at 100 KHz offset re√ quires a supply noise no higher than few tens of nV/ Hz and a supply pushing gain of only few hundreds of KHz/V. In the present application, tolerating a broadband 100 mV peak-topeak supply voltage ripple with a 100 KHz/V supply pushing gain (after supply pushing cancellation) requires a minimum 65 dB PSRR at 1 MHz and in excess of −45 dB PSRR at 10 MHz to achieve the −80 dBc supply injected spur level. Most existing VCOs use a single regulator to minimize the phase noise degradation due to supply injected noise and

spurious tones [3, 5, 10–12]. The oscillator is usually placed inside a phase-locked loop to generate a stable output clock frequency. The PLL feedback loop highpass filters the noise and spurious tones of the oscillator. The corner frequency of the transfer function is PLL’s natural frequency ( fn ). At frequencies lower than fn the loop attenuates oscillator’s phase noise, while for frequencies higher than fn the feedback loop is inactive (open), letting the output clock phase noise follow the VCO phase noise characteristic. Achieving a low supply injected noise and spurs requires a high regulator PSRR up to at least one decade above the PLL’s natural frequency (typical up to several MHz, or few tens of MHz). Achieving a large PSRR value at high frequencies requires a large regulator bandwidth, which increases its output voltage noise due both to the reference voltage and the regulator amplifier contributions. This results in a significant degradation of the VCO phase noise through the supply pushing mechanism which upconverts the low-frequency noise of the regulator into phase noise skirts around the multi-GHz carrier. Particularly troublesome is the 1/ f noise of the regulator. Once 1/ f noise is created, it is hard to filter, since it requires very large R and C values, which are hard to integrate on-chip. The preference is to use a regulator with low 1/ f noise to begin with. Usually the PLL bandwidth is selected to be much larger than the VCO’s 1/ f 3 phase noise corner frequency, such that the 1/ f noise upconversion has a small impact on the PLL output integrated phase noise. Strong resistor degeneration was used in the regulator reference voltage circuit to minimize the active device 1/ f noise contribution (Rdeg in Figure 3(c)). A large regulator bandwidth as required by a high PSRR value comes in contradiction with the regulator’s low noise requirement. This paper uses a dual-regulator architecture to bias the VCO [15]. Using two cascaded regulators solves the contradiction between PSRR and noise requirements by distributing the two specifications over the two regulators. Figure 5(a) presents the principle diagram of the dualregulator architecture. It consists of a first wide-bandwidth

8

EURASIP Journal on Wireless Communications and Networking VDD

VDD Ibg High PSRR high bandwidth regulator

Vref 1 OAreg +

Rbg

Cpsrr

Mnreg Vreg 1

Low noise low bandwidth regulator Iref = V T/R PLL block

Mfold

Vcasc

Mamp

+ Md

Mpreg Vreg 2 L2 fo

Rfold Vref 2

Md

VCO C2 fo

(a)

(b)

Figure 5: Dual regulator: (a) principle; (b) implementation.

regulator that provides a large value PSRR up to high frequencies, followed by a second narrow-bandwidth regulator that provides the low noise output voltage. Since the noise requirements of the first regulator are relaxed, a standard bandgap voltage reference can be used, as shown in Figure 3(a). In contrast, the second regulator needs to use a very low noise reference voltage, achieved by using a VT reference circuit as shown in Figure 3(c). The degraded PSRR of the second regulator at high frequencies is not a concern, since most of the overall PSRR performance of the dualregulator architecture is ensured by the first wide-bandwidth regulator. Distributing the challenging noise and PSRR specifications between the two regulators results in a PSRR in excess of 60 dB up to tens of MHz, while the output voltage spot √ white noise is lower than 20 nV/ Hz. Figure 5(b) shows the detailed schematic of the dual VCO regulator. Standard VT NFETs cannot be used as series devices due to the large resulting voltage drop on the regulator, which leads to a reduced amplitude in the oscillator, with detrimental effect on the phase noise performance. A PFET output device will significantly degrade the PSRR of the first wideband regulator, particularly at medium and high frequencies. To solve the large voltage drop issue of the NFET series regulators, while simultaneously achieving a high PSRR, the first wideband regulator was implemented with a zero-VT (native) NFET device, which comes at no extra cost in the selected CMOS process. The bandgap reference voltage for the first regulator was generated by injecting an Ibg current into an Rbg resistor. The Cpsrr capacitor improves the PSRR of the reference voltage at high frequencies when the supply noise propagates directly through the capacitor divider given by the Cgd parasitic capacitance of the Ibg current mirror and the Cpsrr filtering capacitance. The second narrow-bandwidth regulator uses a singleended amplifier implemented with the Mamp common-gate stage, followed by the Mfold folding cascode stage. It minimizes the noise of the regulator, while ensuring a large feed-

back loop gain value. A differential amplifier leads to a larger intrinsic noise when compared with a single-ended implementation, for the same loop gain value. The supply voltage for the oscillator is given by VSG (Mamp ) and VGS (Md ). A digital calibration of the VT /R reference current was used to achieve a tight control on VCO’s local supply voltage, allowing its amplitude maximization. The mismatches in the clock path differential buffer create second-order distortion terms. If the second harmonic leaks to the oscillator a further degradation of its phase noise may happen [24]. To avoid this, a high quality factor series LC circuit tuned at the second harmonic of the highest oscillator operating frequency was placed in parallel with the oscillator. In the considered process the highest Q is achieved by the MIM capacitors and the bondwire inductors. Achieving a large rejection factor was possible by using a C2 fo MIM capacitor connected in series with an L2 fo bondwire connected to the package paddle, constituting the ground plane. At lower operating frequencies the L2 fo , C2 fo circuit shows less attenuation of the second harmonic, but the VCO phase noise is also lower. 6.

CRYSTAL OSCILLATOR

The main role of a crystal oscillator is to generate a low phase noise sinusoidal reference clock for the PLL. The operating frequencies of low-end XTALs are limited to 20–40 MHz due to their fundamental tone operation. Overtone crystals can go as high as few hundred MHz, but at a large cost increase. The PLL front-end noise is amplified by the feedback divider modulus (N). In multi-GHz frequency synthesizers the gain can be as high as 40–60 dB, resulting in a large magnification of the reference clock path phase noise. For this reason, it is preferred to use the XTAL with the highest available frequency within the targeted cost range. Historically, most of the XTAL oscillators are realized with Pierce configuration (common source amplifier) as shown in Figure 6(a) [3–6]. The main advantage of this

Adrian Maxim

9 VDD

VDD Rdeg

Rdeg

Rdeg

Mbias Lbond XTAL

Mamp Peak detector

Rg +

Mamp

C1

Mbias

Peak detector AAC

Iaac

+

Cg

C2

Lbond C1

C2

Ref. CLK

Ref. CLK Lbond

Lbond

BUF

Digital block

XTAL Lbond

(a)

AAC

Digital noise coupling

BUF

Digital block (b)

Figure 6: XTAL oscillators: (a) Pierce configuration, (b) Colpitts configuration.

architecture is that the two tank capacitors C1 and C2 are grounded and can be implemented with MOS capacitors, resulting in a relatively low die area. The bias current for the Mamp amplifier is generated by a resistive degenerated (Rdeg ) PFET current source (Mbias ) controlled by the automatic amplitude control loop (AAC). Another advantage of the Pierce configuration is the class C operation of the Mamp device that is ON only at the peak positive amplitude of the generated sine-wave, when the phase noise impulse sensitivity function is at a minimum [13]. This results in a very low phase noise contribution coming from the Mamp device. The XTAL oscillator phase noise is dominated by the crystal tank losses and the bias current source driven by the AAC loop that are always ON (operated in class A). A standard analog AAC loop consists of a peak detector, a reference voltage generator, and an AAC loop amplifier/comparator [16, 17]. Lower AAC loop phase noise contribution was achieved with a digital implementation in which the output of the peak detector is converted to digital domain by an ADC and the loop amplifier is replaced by a noiseless digital state machine that controls the bias current via a current DAC [18]. The most significant XTAL noise contribution to the PLL output clock phase noise is at low-frequency offsets from the carrier, where the 1/ f noise upconversion of the active devices dominates [13, 14]. Therefore from the multitude of Pierce oscillator configurations the lowest phase noise is achieved by the one using an NFET amplifier operated in class C and a PFET bias current source operated in class A (see Figure 6(a)). The justification resides in the much lower 1/ f noise of the deep-submicron PFETs (an order of magnitude lower) in comparison with the NFETs. Implementing the C1 and C2 capacitors off-chip is a bad choice in the case of large mixed analog-digital SOCs. This is because the XTAL bondwires may magnetically couple large spurs from the biasing bondwires of the digital circuits which carry high amplitude current spikes. The coupled voltage is divided between C1 or C2 capacitors and the Mamp parasitic capacitances. As the last ones are usually much lower in comparison with C1 and C2 , most of the magnetically coupled

voltage appears at the gate of Mamp and therefore at the input of the reference clock squaring buffer (REF-BUF). The XTAL oscillator generates a sinusoidal signal, while the PLL requires a square-wave clock. A squaring buffer is usually used to accomplish the edge squaring operation. The nonlinear edge squaring performed by REF-BUF buffer is in fact a phase sampling action that results in high-frequency noise and spurs aliasing down into an fref interval around the XTAL carrier. Thus the squaring buffer is capable of downconverting into the PLL bandwidth the high-frequency noise and spurs that reach the buffer input. Reducing the amplitude of the coupled spurs at the input of the squaring buffer requires an on-chip implementation of the C1 and C2 capacitors. In this case the bondwire coupled voltage is heavily attenuated by the capacitive divider formed with the parasitic pin and pad capacitance added with the PCB capacitance on one side and the on-chip C1 /C2 capacitors and the amplifier parasitic capacitance on the other side. From the phase noise perspective using an NFET amplifier is a major drawback for a Pierce oscillator. Furthermore, it requires two bonding pads to connect the crystal, being ill-suited for pad-limited SOC applications. Figure 6(b) presents an alternative way to implement a crystal oscillator using a Colpitts configuration (common drain amplifier). A PFET amplifier Mamp is used in order to reduce the 1/ f noise impact, while a resistively degenerated (Rdeg ) current mirror (Mbias ) was used to bias the amplifier. The common-mode voltage at the gate of Mamp was chosen close to the supply voltage, such that a class C operation can be achieved, with its dramatic phase noise improvement impact. Moreover, the crystal requires only a single connecting bondwire (Lbond ), being advantageous for pad-limited SOCs. An Rg , Cg filter was used to minimize the noise contribution of the Mbias device. The main drawback of the Colpitts common-drain configuration is the requirement of a floating capacitance (C1 ) that needs to be implemented either as a MIM or as a metal interconnect capacitance. Therefore it requires a larger die area in comparison with a MOS capacitor. The last ones cannot be used as floating capacitor since their large bottom plate parasitic capacitance gives a high substrate noise

10

EURASIP Journal on Wireless Communications and Networking VDD Lbond

XTAL Mb1 osc.

Iref = V T/R Mcasc + Vcasc

XTAL Filter pole calibration

R-DAC

Mb2 Rlpf

Shunt regulator

Coax line C

c

Inv 5

Cc Clpf Inv 1

Inv 2

Fref Up PFD Fdiv Dw

Inv 3 Inv 4

Figure 7: Low noise and low coupled spurs reference clock signal path.

injection. The larger die area taken by the Colpitts XTAL is offset by the much lower phase noise in comparison with a Pierce configuration. This results both from a larger oscillation amplitude allowed by a common drain amplifier (only one device versus two stacked devices in the Pierce oscillator) and the reduced contribution of the Mbias noise to the oscillator phase noise. Another important design choice is the type of FET devices (thin or thick gate oxide FETs) used for both the amplifier and the AAC loop. The thick gate I/O devices can hold a larger voltage (2.5 to 3.3 V), resulting in a larger amplitude with a quadratic impact on the phase noise [13]. Thin oxide FETs can withstand only a 1 to 1.3 V voltage, drastically limiting the oscillator amplitude. However, they have a significantly lower 1/ f noise (direct proportional with Tox oxide thickness), which results in a much lower 1/ f 3 phase noise. The spurs coupled to the XTAL local supply are translated near the XTAL carrier through the crystal oscillator supply pushing resulted from the nonlinear capacitance connected in parallel with the crystal [14]. Any spur that appears on the reference clock path is amplified by the large PLL closed-loop gain (equal to the N modulus value inside the loop bandwidth), often resulting as the dominant spur mechanism in the PLL. A dual-regulator architecture was used to achieve a PSRR in excess of 60 dB up to high frequencies (at least one decade above the PLL natural frequency). With 0.5 V voltage drop on each regulator and a 2.5 V global supply, the local supply of the XTAL oscillator comes close to the breakdown voltage of the thin oxide FETs. Therefore both the amplifier with its bias current source and the AAC loop peak detector and amplitude comparator were implemented with thin oxide FETs, benefiting of their much lower 1/ f noise. 7.

REFERENCE CLOCK PATH

For a low noise PLL it is crucial to achieve a low phase noise edge squaring operation. This is performed by the reference clock buffer presented in Figure 7. As mentioned before, this nonlinear operation is capable of downconverting the high-frequency noise and spurious tones from both the squaring buffer input and its supply line, directly inside the PLL loop bandwidth, where no rejection is presented. This mechanism is particularly dangerous in large bandwidth PLLs when the chance of getting a spur inside the loop band-

width is much higher. Furthermore, large SOCs pose supplementary challenges when they have multiple clock domains that are not harmonically related, opening the path to spur down-conversion due to the nonlinear functions existent in the signal path. One of the dominant spur coupling mechanisms at the squaring buffer input is through the crystal bondwire. To minimize the spur that arrives at the input of the squaring buffer, an RC lowpass filter (Rlpf , Clpf ) was placed between the Lbond bondwire and the input of REF-BUF. This attenuates the high-frequency spurious tones before they are applied to the nonlinear edge squaring operation with downconversion capability. To avoid phase noise degradation due to reference clock slewing (which generates noise aliasing), the RC filter should have its corner frequency higher than the PLL reference frequency. Ensuring this condition over all process and temperature corners results in a larger typical corner frequency and thus a lower attenuation of the highfrequency spurs. A maximum attenuation can be achieved by using the lowest possible corner frequency in the RC filter. This design uses a calibrated RC filter that has a resistor DAC to adjust the RC filter time constant, such that its corner frequency stays constant over all process corners and is positioned with one octave above fref . The maximum Rlpf resistance is determined by its own noise contribution to the overall PLL phase noise. On the other side, a too low Rlpf resistance results in a very large Clpf capacitance that may heavily load the crystal tank, potentially reducing its quality factor and thus increasing the XTAL oscillator phase noise. To avoid large pulse-width distortion in the reference clock path due to differences between XTAL oscillator and squaring buffer common-mode levels, an AC coupling through the Cc capacitor was used. The DC bias voltage to the input of the squaring buffer is provided by two replica diode devices Mb1 , Mb2 and an isolation RC filter. The supply voltage for the front-end inverters of the squaring buffer (Inv 1 and Inv 2 ) is provided by an open-loop shunt regulator built with a low noise Iref = VT /R current injected into the Mb1 , Mb2 replica diode-connected devices. This circuit provides a high forward PSRR to minimize the supply noise and spur injection into the local buffer supply. Changes in the local supply modulate the inverter trip point and thus create jitter. To further improve the PSRR of the shunt regulator, the gate of the Mcasc cascode device is referenced to

Adrian Maxim ground via a Vcasc voltage source, as opposed to the supply referencing used by a standard cascode current mirror, which has a degraded PSRR due to the direct supply noise injection through the Cgd (Mcasc ) parasitic capacitance. The shunt regulator offers also a large reverse PSRR which is important for minimizing the reference spur contamination of the global PLL supply due to the large current spikes generated by the fast switching squaring buffer inverters. The reference frequency modulation of the supply given by its effective impedance (set with the on-chip bypass capacitance and the supply bondwire inductance) may couple to other sensitive analog blocks (e.g., loop filter or VCO) and thus degrade the PLL reference spur performance. In present design, for a 50 ps 10-to-90% rise/fall time and a 1.2 V supply the slew rate is 20 GV/s. For such fast reference clock edges a PSRR of only −40 dB is required from the corresponding shunt regulator to achieve output spurs lower than −80 dBc, when the PLL gain is 50 dB and the supply voltage ripple is 100 mV peakto-peak. Once the reference clock edges are squared up (have a high slew rate), it is important not to slow them down again before reaching the PFD, since this may create a second noise aliasing point in the reference clock path at the point where the edges are squared up a second time and thus degrade the reference clock phase noise. The first stages of the squaring buffer (Inv 1 and Inv 2 ) need a very low noise supply voltage. Bandgap references are often used to generate supply voltages [1–11]. However, they are notorious for their high noise level which disqualifies them for the reference clock path bias generator. A VT /R reference current was used instead (see Figure 3(b)) that has a much lower 1/ f and thermal noise due to a large degeneration resistor (Rref ). Injecting a low noise Iref = VT /R current into low impedance diodeconnected FETs, a very low noise supply voltage is achieved. The large process and temperature variation of this voltage is not an issue for the REF-BUF since it tracks the trip point of the squaring buffer inverters. The internal phase noise of the squaring buffer is dependent on the noise contributed by the NFET and PFET of the first inverter (Inv 1 ) around its trip point, where the edge position is decided. Using a low supply voltage equal to VT p + VTn for the squaring buffer allows only one device to be in strong inversion around the trip point (either the NFET or the PFET). Since the two devices cannot be simultaneously in strong inversion (as is the case for a standard inverter biased from an elevated supply voltage), the phase noise of the squaring buffer is significantly reduced. Using only one device to drive the load capacitance reduces somewhat the edge speed, but the much lower device noise offsets by a large amount the higher noise to phase noise conversion gain due to the lower edge slope. The PFD is usually operated at the nominal thin gate oxide FET supply voltage (e.g., 1.3 V in a 0.13 μm CMOS process). Therefore it was biased from a separate closed-loop shunt regulator. A second pair of capacitive coupled inverters (Inv 3 and Inv 4 ) was used to perform the level shifting of the reference clock digital levels and also provide the additional required drive strength. In most crystal oscillators the

11 phase noise of the rising and falling edges are not identical. For example, in the Pierce oscillator case (Figure 6(a)) the rising edge at the Mamp drain has a lower phase noise since the Mbias PFET with lower 1/ f noise is driving the edge. The falling edge is noisier due to the higher 1/ f noise of the Mamp NFET that is driving the edge. For a low noise PLL it is important to select the lower phase noise edge to drive the PFD. A similar situation happens in the Colpitts XTAL oscillator (Figure 6(b)) where the rising edge in the source of Mamp has lower phase noise. Therefore the Pierce oscillator requires a even number of inverters between the gate of Mamp and the input of the PFD (assuming the PFD is falling edge sensitive), while the Colpitts oscillator needs an odd number of inverters. If the XTAL oscillator (usually placed in the pad ring) and the PFD are not in close proximity, a coaxial metal shield needs to be used for the reference clock path in order to avoid parasitic coupling to the clean reference signal. 8.

PHASE-FREQUENCY DETECTOR

The PFD compares the phases of the reference and feedback clocks and generates the up/down digital control signals for the charge-pump. Both its input clocks and the internal node signals are square-waves with high edge slew rate, which minimizes the PFD phase noise contribution (both from internal device noise and the supply injected noise). Minimizing the phase noise contribution of the charge-pump current sources requires the reduction of the time interval that both currents are ON during each reference clock cycle. This also decreases the amount of supply noise and spurious tones that are downconverted by the charge-pump chopping action. To achieve this goal, the PFD needs to have a very fast reset signal propagation time, which requires a minimal number of logic gates in the PFD signal path and also the usage of the fast thin gate oxide FETs. PLLs that use source, gate, or drain switch chargepump architectures have a relatively slow switching time (few nanoseconds) and therefore require wide up/down PFD pulses to ensure that the charge-pump current sources are active when the phase difference measurement is performed. If the PFD control pulses are narrower than the CP switching time, the so-called dead-zone appears in the PFD-CP transfer function, since the CP does not have enough time to fully switch and thus correct for the phase difference measured by the PFD. The dead-zone in the charge-pump transfer function can seriously degrade the PLL jitter performance, since during this time interval the feedback loop is opened and the clock edges are moving randomly till they generate a phase difference enough large to bring the charge-pump out of the dead zone region. The seven-NAND implementation of the dual D-flip-flop PFD is very popular in CMOS PLLs [1–6]. However, it has a large reset time equal to seven gate propagation times, which typically ranges between 300 pioseconds and 1 nanoseconds depending on the device type and sizes. If a larger reset time is required (several nanoseconds), additional inverters can be introduced in the reset signal path [3]. If the CP transfer function is dead-zone-free, then the PLL reference spurs are reduced linearly with the decrease

12

EURASIP Journal on Wireless Communications and Networking VDD Ib Vref

+

Ishunt

I-DAC Rc

Mmir Mmir

Cc Ib

Processdependent current

Ib

Cbyp

Mfeed Fref

Inv

Iu

Upb

LVL

DFFu

Up

LVL Tu Inv

Dwb

LVL Mpho

Fdiv

Id

Inv

Dw

Mfol

Mnho

M pi DFFd

Td

Inv

Mni

LVL

Figure 8: Phase-frequency detector (PFD) with dedicated shunt regulator.

of the CP pump-up and pump-down pulse widths. The limit to which these pulses can be reduced is set by the CP switching speed. The selected differential current-steering CP architecture provides worst-case switching times as low as 50 pioseconds in 0.13 μ CMOS. A PFD reset time as low as 100–150 pioseconds was achieved by using thin gate oxide FET dynamic D-flip-flops as shown in Figure 8 [4]. They result in only three gate delays in the reset signal path. The PFD feedback NAND gate that generates the reset signal for the two flip-flops was built within the dynamic flip-flop structure by using the Mrst 1 and Mrst 2 devices. This reduces by one gate delay time the minimum up/down pulse width when the PLL is in lock condition. The PFD generates single ended up/down signals, while the differential current steering charge-pump requires also the complementary upb/dwb signals. These last ones are generated by adding a parallel path at PFD output, having one more inverter in comparison with the main up/dw signal path. Reducing the glitch current created by the chargepump switching requires a good synchronization of the up/dw and upb/dwb signals. To achieve this, two alwaysON transmission gates Tu /Td were added in the up/dw signal paths to match the propagation time through the extra inverters (Iu /Id ) from the complementary upb/dwb signal paths. Reducing the current glitch in the charge-pump requires keeping the common-mode voltage at the NFET differential current steering pair high and the common-mode at the PFET differential current steering pair low, such that at all times there is at least one device in each differential pair that is ON. If at a given moment both devices of the differential current steering pair are turned off due to an un-appropriate common-mode level, a large charge-pump current spike is

generated, which may result in significant VCO control voltage ripple and thus a serious PLL reference spur-level degradation. To achieve a fast reset in the PFD, thin oxide FETs were used, while a low supply voltage (e.g., 1.3 V) was provided in order to avoid device breakdown. In contrast, the chargepump uses the highest supply voltage available in the system, such that a large oscillator control voltage swing is ensured, as required by a low VCO gain. A level shifter stage need to be introduced between the PFD and the charge-pump, that performs the appropriate digital signal logic-level conversion. Positive feedback cross-coupled differential inverters are often used to perform the level shifting function [1]. Their main drawback is the lower edge speed due to the large gate capacitance of the cross-coupled devices that loads heavily the signal path. Furthermore, positive feedback circuits are notorious for their degraded phase noise and therefore they should be avoided in the low phase noise PLL front end. This design proposes a new level shifter architecture shown in Figure 8 that achieves a much higher edge speed in comparison with the cross-coupled architecture, without using the positive feedback to regenerate the logic level to the higher supply. It consists of a low voltage thin gate oxide inverter Mni /M pi and a protection high-voltage thick gate oxide current mirror Mfol /Mnho . For an output Low state the Mni device is pulling down and the Mnho device operates in triode region, propagating the Low state to the output. The fast thin oxide NFET guarantees a rapid discharge of the load capacitance and therefore a short fall time. For a logic High at the output, the input is in the Low state. Therefore a high voltage thick oxide PFET Mpho can be used to pull-up the output node. A proper sizing of this output PFET is required

Adrian Maxim to provide a balanced rise/fall time at the level shifter output. The input capacitance of the level shifter is given by the thin oxide inverter and the gate capacitance of the thick oxide pull-up PFET. The last inverter layer in the up/dw/upb/dwb signal paths need to be designed to drive this larger input capacitance of the level shifter, while the level shifter needs to be strong enough to be able to drive safely the input capacitance of the charge-pump switches. The switches size is dictated by the 1/ f noise of the differential current steering pair, which sets the W/L aspect ratio for the differential pair devices. Generating fast edges in the PFD and in its output level shifter requires large supply current spikes that may degrade the PLL reference spur performance if they leak to the sensitive analog blocks (e.g., loop filter or VCO). Preventing the reference ripple coupling through the PLL global supply is ensured by biasing the PFD and its input and output level shifters from a separate shunt regulator that has a large reverse PSRR. An open-loop shunt regulator cannot be used in this case due to its relatively large output impedance that would create a large local supply ripple as a response to the high amplitude supply current spikes. A closed-loop shunt regulator was used instead as presented in Figure 8 [19]. The reference voltage Vref is followed at the output through the Mmir PFET current mirror that is kept always active by the Ib bias current sources. The shunt regulator presents to the global PLL supply line a constant Ishunt current load. This current either provides the large supply current spikes of the digital circuitry, or it is dumped to ground by the Mfeed local feedback device. An Rc , Cc compensation circuit is used to guarantee a good phase margin of the local feedback loop constituted by Mmir and Mfeed . A local bypass capacitance Cbyp was added to provide the high-frequency component of the digital load current, while the low- and medium-frequency current components (up to the local feedback loop bandwidth) are provided by the shunt regulator. To guarantee a high reverse PSRR, it is necessary to design the Ishunt DC current to be larger than the highest DC component of the digital circuitry supply current over process, temperature, and supply corners (PTV). The digital circuit presents a very wide range supply current variation over PTV requiring an over-designed Ishunt current. To avoid current wasting in the shunt regulator, the IShunt current was set by a current DAC (I-DAC) controlled with a circuit that tracks the process corner of the thin gate oxide FETs, which constitute most of the digital circuitry load capacitance. 9.

CHARGE-PUMP

The charge-pump (CP) is a key block for a low noise and low spur-level frequency synthesizer. In lock conditions the CP current sources are turned-on for a very short period of time, being OFF for most of the reference clock cycle. Therefore the intrinsic noise of the CP is multiplied in time domain with a periodic rectangular switching function. This corresponds to a convolution in the frequency domain with a discrete sinc spectrum, having the spacing between the tones equal to the reference frequency, while the main lobe width is equal to twice the inverse of the CP on-state time. The 1/ f noise of

13 the charge-pump currents has usually a low corner frequency (few MHz down to hundreds of KHz) which is much lower than the PLL reference frequency (tens of MHz). Therefore the switching action of the charge-pump does not result in aliasing of the 1/ f noise. The PLL closed-loop transfer function has a lowpass shape with the corner frequency at the PLL loop natural frequency (≈ 0.5 MHz). Therefore at the output of the PLL appears only one lobe of the CP 1/ f noise spectrum. The 1/ f noise power spectrum is attenuated by the square of the switching waveform duty cycle. Hence the CP √ 1/ f noise current (A/ Hz) is effectively scaled down by the duty cycle of the switching waveform. The charge-pump white noise undergoes aliasing in the frequency domain due to its wide bandwidth spectrum. After piling up the different aliased white noise components (coming from the convolution with each discrete tone from the switching waveform spectrum), they are lowpass filtered by the PLL closed-loop transfer function. As a consequence, the aliasing effect diminishes the noise reduction brought by the switching waveform duty cycle. The noise power is reduced linearly with the duty-cycle, while the equivalent CP output white noise current is reduced by the square root of the duty cycle value. Summarizing, both the 1/ f and the white noise originated in the charge-pump can be reduced by minimizing the time interval that the CP is ON (low duty cycle of the switching waveform). Besides reducing the duty cycle, a second way to reduce CP noise contribution is to minimize its intrinsic noise. The charge-pump is in essence realized by two complementary current mirrors connected to the PLL loop filter high impedance node. In a current mirror both the input (master) and the output (slave) devices contribute noise. If the noise of the output devices Mno /M po is unavoidable, the noise of the input devices Mni /M pi can be filtered-out by using two very low corner frequency RC filters (Rn , Cn ) as shown in Figure 9. To provide an effective noise filtering, the corner frequency of the Rn , Cn lowpass filter needs to be at least one decade lower than the PLL natural frequency. The value of the Rn resistor is limited by its own white noise contribution. Therefore large on-chip Cn capacitors are usually required by the CP noise filters. Large-area deep-submicron FET filtering capacitors (thousands of μm2 ) come with relatively large gate leakage currents (μA at the maximum IC temperature), which in conjunction with the high Rn value (MΩ) can lead to significant voltage drops (hundreds of mV) that may impact the current mirror ratio. The gate leakage increases steeply with the gate voltage level. In the selected 0.13 μm CMOS process the NFETs have Ig leak = 0.1 nA/μm2 at Vgate = 1.5 V, Ig leak = 25 pA/μm2 at Vgate = 1 V, and Ig leak = 5 pA/μm2 at Vgate = 0.5 V at the room temperature. This issue is even more problematic in further scaled CMOS technologies (e.g., 90 nm and 65 nm CMOS). The leakage currents of the NFETs and the PFETs do not track over process and temperature. PFETs tend to have lower leakage currents, which may lead to a large mismatch between the pump-up and pump-down current. The PLL loop responds in lock conditions by introducing a static offset between the reference and the feedback

14

EURASIP Journal on Wireless Communications and Networking VDD

Rf

RC filter or regulator Mfol

Cf

Cn M pi

M po

Rn

Up

Upb

Up

Upb

Mswp Icp OAmatch

+

OAdum

Rs

Cs

+

Vctrl

Mswn Dwb

Dw

Mbias Mni

Rn

Cn

Dwb

Dw

Mno

Figure 9: Dynamic current-matching charge-pump with supply and bias noise filters.

clocks. The equilibrium point is reached when the charge injected by a wider pulse, low value pump current is balanced with the charge injected by the narrow pulse, higher value complementary pump current. The large duty cycle of one of the charge-pump currents determines a significant degradation of the CP noise contribution, and if the wider pump current is the PFET one, then it also increases the supply noise and spur injection. To avoid gate leakage induced current mismatches, the Mni /Mno and M pi /M po are implemented also as thick gate oxide devices, which have a negligible gate leakage current. Large-area devices were used to reduce their 1/ f noise component. A unity gain buffer OAdum is usually used to keep the dummy side of the current steering charge-pump at the same potential with the active output (loop filter side). This minimizes the charge-sharing from the dummy side and thus reduces the ripple on the loop filter due to sharing current glitches when the output switches are ON. The noise of this buffer is first sampled on the parasitic capacitances from the common source points of the differential current steering switches when the dummy switches are ON, and is then shared with the loop filter when the output switches are ON. To minimize the OAdum noise contributions a very large ratio needs to be maintained between the loop filter capacitance and the parasitic capacitance at the common source node. Reducing the pump-up/pump-down current mismatches is key for a low reference spur level. A dynamic current matching feedback loop was implemented by adding the OAmatch amplifier to drive the gates of the PFET current mirrors such that the NFET and PFET currents are well balanced [19, 28]. The ripple from the dummy side of the chargepump (followed by the OAdum wide-bandwidth operational amplifier) does not modulate the charge-pump PFET cur-

rent since both the Rn , Cn filter and the low OAmatch bandwidth are strongly attenuating it. The dynamic charge-pump current matching circuit consists of two feedback loops: a negative feedback given by OAmatch and M pi and a positive feedback given by OAmatch, M po , and Mswp with OAdum buffer. The low impedance provided by OAdum buffer at the inverting input of the OAmatch operational amplifier guarantees that the negative feedback has a much stronger loop gain in comparison with the positive one. Maximizing the voltage swing at the charge-pump output requires the reduction of the number of stacked devices in the NFET and PFET current mirror legs. Cascode tail current mirrors are preferred for their much larger output impedance and thus a lower up/down current mismatch due to the variation of the loop filter voltage. However, cascode current mirrors take a larger voltage headroom that adds to the voltage drop on the ON-state switch to give the minimal output voltage level. Present design proposes a much higher output voltage swing charge-pump in which the Mswn and Mswp switches are operated between OFF and saturated ON states, such that they act as cascode devices when they are ON. The current steering operation is determined by the state of the two switches connected to the gates of the differential pair, providing either the cascode bias to the gates of Mswn /Mswp devices, or connecting them to ground. Eliminating one device from the stacked telescopic architecture of the charge-pump is particularly advantageous for the high charge-pump currents applications. The noise coming from the supply lines is also sampled by the low duty-cycle switching waveform, determining a reduction of its power. Similar to the charge-pump devices internal noise, the supply injected white noise suffers aliasing, while the supply 1/ f noise does not. If a supply filter or a

Adrian Maxim regulator is used to bias the charge-pump, its 1/ f and white noise need to be carefully looked at. A second concern for a charge-pump is its spur downconversion capability. The switching action of the chargepump switches has a chopping operation that results in a frequency translation (mixing). Therefore the high-frequency spurious tones present on the charge-pump supply voltage or bias current are downconverted around the fref PLL reference frequency. The resulting low-frequency ripple of the VCO control voltage determines spurs around the multi-GHz output clock. If these spurious tones fall inside the PLL bandwidth, where no rejection is presented by the feedback loop, they are simply amplified by the large N feedback divider modulus. In PLLs having low XTAL frequencies and high output clock frequencies (large frequency multiplication factor), these spurs may be the dominant spur mechanism. The charge-pump presents this mixing property both to the supply voltage and the input bias current high-frequency spurious tones. The Rn , Cn CP noise filters also help rejecting the high-frequency spurs coming from the bias current. If additional rejection is required, a supplementary filter Rs , Cs can be added in series with the input bias current (Ibias ). To minimize the supply ripple, an RC filter or a regulator can be used to bias the charge-pump. Reducing the VCO gain requires the maximization of the voltage swing at the CP output (1.3 V for thin gate oxide FETs). Using a regulator to bias the CP takes at least 0.5 V of headroom, which may be too much, particularly in the low-voltage applications. This design uses an active RC filter built with a zero-VT NFET, which takes only 200 mV of voltage headroom and provides in excess of 40 dB of rejection for the high-frequency supply spurious tones. In this application the 1.8 V digital supply is sufficiently high to accommodate a 0.2 V voltage drop on the active filter and the 0.3 V headroom required by the PFET cascoded charge-pump current source. 10.

LOOP FILTER

The main functions of the loop filter are to provide the PLL stabilizing zero and to filter the ripple on the VCO control voltage. Passive RC filters are widely used [2, 5, 6] due to their simplicity and their excellent power supply noise rejection. A passive loop filter has no supply lines, the only supply injected noise is coming from the charge-pump supply line. This is minimized by ensuring a CP output impedance much larger than the loop filter impedance at the spur frequency. The major drawback of the passive filters is their large capacitor size, particularly in low PLL bandwidth applications. These capacitors are often implemented off-chip, increasing the external component count and exposing the sensitive VCO control line to parasitic magnetic coupling due to the connection bondwire and package lead [5, 6]. Active loop filters were used to reduce the size of the loop filter capacitor [19, 21, 22]. A further reduction was brought by implementing a Miller capacitance multiplication technique [1]. This magnifies the size of the physical loop filter capacitance, allowing the on-chip realization of a large PLL time constant. However, the Miller capacitance gain comes also

15 with a magnified noise from the Miller amplifier, this solution being suited only to mid noise performance PLLs. Furthermore, an active loop filter requires a supply line, resulting in a noise coupling path from the supply to the sensitive loop filter output node. To minimize the supply noise injection, the active loop filters are often biased from a dedicated high PSRR regulator [3, 4]. Reducing the gain of the oscillator and thus reducing the noise contribution of the PLL front end requires a very wide range voltage swing at the VCO control line. This in turn results in a large supply voltage requirement that prevents the usage of the dual-regulator technique. A single regulator needs to be used to bias the loop filter. A PFET output series regulator has the advantage of a low-voltage drop, but achieves a rather poor PSRR performance at medium and high frequencies. In contrast, an NFET output series regulator provides a higher PSRR up to high frequencies, but requires a larger voltage drop (at least a VGS + Von = 0.7 to 1 V). In modern deep-submicron CMOS processes the native NFET devices that do not undergo the threshold adjustment implantation have threshold voltages close to 0 V. Using them to build series NFET regulators results in a low-voltage drop and a high PSRR up to few tens of MHz [11]. Figure 10(a) shows one solution for realizing a very high PSRR series regulator for biasing an active PLL loop filter. The total voltage drop on the regulator is about 2Von ranging from 0.3 to 0.5 V, depending on the supplied current. To further improve the PSRR of the regulator at high frequencies, a supplementary active RC filter R f , C f , Mfol was used to filter the noise from the drain of the main series regulator output device Mnreg . An effective supply noise filtering requires that the corner frequency of the active RC filter be with at least one decade below the PLL natural frequency. In wideband PLLs (BW > 1 MHz) this can be easily achieved with an on-chip C f capacitor. In low PLL bandwidth applications (BW < 100 KHz) the active RC filter presented in Figure 2(c) needs to be used, since it has a decent PSRR staring from DC. Figure 10(b) presents an alternative solution for integrating the loop filter on-chip. The proposed loop filter uses a passive feedforward RC filter that consists of two charge-pumps: the integral one CPint that injects its current in the integral capacitance Ci and a proportional one CPprop that injects its current into the Rz series resistance [12]. Active loop filters use a summing amplifier to add the integral and proportional control path signals [20]. This degrades the PLL phase noise due to the amplifier internal noise and also exposes the VCO control line to further supply noise injection. Alternatively in the case of LC-VCOs a split varactor can be built that performs the summation of the two control paths signals [23]. In the proposed passive feedforward loop filter the summation is realized by simply placing the Ci capacitance in series with the Rz resistor. To allow the flow of the proportional current through the Rz resistor, it needs to be connected towards the ground, while the Ci capacitor is connected floating (opposite to what is done in a standard passive RC filter). A ripple filtering capacitance C p was added to reject the ripple from the VCO control line. A second-high frequency pole is realized with the R p2 , C p2 filter that further

16

EURASIP Journal on Wireless Communications and Networking VDD VDD

Rf

CPint

CPprop

Mfol Cf Vref +

+

OAreg

Vctrl

Mreg

R p2

Ci Rz

Active loop Vctrl filter

+

(a)

Cp

C p2

Vdc

(b)

Figure 10: PLL loop filters: (a) active filter with high PSRR regulator; (b) passive feedforward filter.

rejects the high-frequency noise and spurious tones. The stabilizing zero position is given by 1   , fz =  2π · Ci · Rz · 1 + Icpp /Icpi Rz

eq

  Icpp = Rz · 1 + .

Icpi

(1) (2)

The equivalent Rz eq resistance appears multiplied by one plus the ratio of the two charge-pump currents, factor that can be designed to be as high as 20 to 30. However, the noise of the Rz resistor is not multiplied in this passive feedforward architecture, which brought the name of noiseless resistor multiplication loop filter. As the resistor is multiplied by a large factor, for a given PLL bandwidth the required loop filter capacitance is reduced by the same amount, allowing its easy on-chip integration. If the Rz resistor is connected directly to ground, the potential at the output of the proportional charge-pump at the beginning of its ON state is 0 V, resulting in a triode-mode operation of the charge-pump NFET current mirror. This brings a large up/down current mismatch in the proportional charge-pump that is compensated by the PLL loop by locking with a large static phase error. In such conditions a large ripple appears at the VCO control line, degrading significantly the PLL reference spur performance. To avoid this spur degradation mechanism, the Rz resistor was connected at a low noise Vdc voltage generator that guarantees the saturation operation of the NFET current mirror during the entire charge-pump current pulse. This results in a good up/down current matching and thus a very low loop filter voltage ripple. The Vdc source can be implemented with several diode connected devices biased by a VT /R current coming from a well filtered and/or regulated supply voltage, such that the supply noise injection is minimized. Ensuring a low PLL phase noise profile at low offset frequencies (where the charge-pump current noise contribution dominates) requires a large Icp int integral charge-pump current (hundreds of μA). This increases the required size of the loop filter capacitance, growing its die area. Also the Rz

resistor multiplication factor is limited by the headroom constraints on the proportional charge-pump that operates at a very large current level (several mA), and therefore has larger device Von values. The single slight drawback of the proposed passive feedforward loop filter is that it requires a floating Ci capacitance that needs to be implemented either as a MIM or as a metal interconnect capacitance. The large gate leakage of the deepsubmicron FETs prevents their usage in PLL loop filters. The thick gate oxide FETs have a negligible gate leakage current and a higher capacitance density in comparison with MIM and metal capacitors, but they still cannot be used for the floating Ci capacitance due to their large bottom plate parasitic capacitance to the global IC substrate, which can bring a large substrate noise injection into the sensitive PLL loop filter. The PLL loop filter can be realized with either a singleended or differential architecture. A single-ended implementation benefits from a much lower die area (half the capacitor size in comparison with a differential architecture), but may suffer of substrate and supply noise injection. Differential implementations offer a better substrate and supply noise rejection, at the price of a twice as large loop filter area. Fully differential loop filters require both a differential charge-pump and a differential VCO tuning circuit, resulting in a more complex common-mode feedback circuit. Pseudodifferential architectures use two single-ended output charge-pumps controlled in opposite phase, such that when one is pumping up, the other one is pumping down [3, 4]. The loop filter capacitance is still twice as large, and an active differential-to-single-ended converter circuit is needed, but the oscillator has a simple single-ended tuning circuit. Differential loop filters are mandatory in SOCs implemented in standard CMOS processes, where there are no other means of attenuating the substrate noise coupling from the noisy digital core. Modern deep-submicron CMOS processes offer a deep N-well option [30, 31] that can be used to build P-wells for the sensitive analog blocks that are isolated from the noisy global SOC substrate. This technique

Adrian Maxim can provide up to 40 dB attenuation to the substrate noise at GHz frequencies (depending on the deep N-well area). In this case the loop filter can be realized single-ended (largearea saving), since the substrate noise coupling is no longer an issue. To minimize the area of the deep N-well and thus reduce the parasitic capacitance to the global substrate, the loop filter resistors and the PFET switches are placed in a separate N-well, while only the loop filter capacitors and the NFET switches are placed inside the isolated P-well. If an active loop filter is used, than the supply noise injection may be a concern. In this situation either a high value PSRR regulator needs to be used to bias the loop filter, or a differential loop filter can be implemented, since it has an intrinsic supply and ground noise rejection capability. The area of a regulator is usually much lower than the one of the loop filter capacitance. Therefore the regulator technique is preferred in moderate supply voltage applications (e.g., > 1.8 V). In low-voltage applications (1 V and below) there is no available voltage headroom to insert a regulator, making the differential loop filter a mandatory choice. Ground noise can be also a major source of PLL phase noise degradation. If the VCO and the driving loop filter that generates its control voltage (Vctrl ) are separated by a large distance, such that their local grounds may have different dynamic potentials (e.g., due to currents that are injected in the ground line), then this noise voltage appears in series with the oscillator control voltage and is upconverted in spurs and phase noise skirts around the carrier. Present design uses dedicated supply and ground connections for the PLL oscillator, while a star-connected ground layout with no injected currents was used for the VCO and loop filter, guaranteeing that their local grounds are at the same dynamic potential all the time. The passive loop filter architecture ensures a very high supply noise rejection, while the deep N-well isolation allows a single-ended implementation, bringing a large-area saving. 11.

LOW PHASE NOISE LC VCO

The top-level diagram of the proposed low phase noise multi-GHz LC-VCO for dual-band 802.11 a/b/g SOCs is presented in Figure 11. Using a single 5 GHz oscillator for both communication bands and deriving the 2.5 GHz clock via a divide by two of the main system clock results in a larger VCO tuning range and therefore a degraded PLL phase noise and spur performance. Present design uses two separate LCVCOs having the tuning ranges of 2.4-2.5 GHz and 5.15– 5.85 GHz, respectively. The larger area required by the two caged inductors was compromised to minimize the VCO tuning gain. An on-chip planar inductor built with a toplevel thick metal layer was used for the LC oscillator tank. To minimize the parasitic magnetic coupling to the VCO coming from the large number of SOC’s digital biasing and high-speed signal bondwires, the inductor was placed inside a metal cage using the top most thick metal layer. The proximity between the inductor and the metal cage reduces somewhat its quality factor (around 10), degrading the VCO phase noise. However, the good isolation from the large amount of

17 VCC High PSRR Vbg regulator

Regulators

Low noise V T/R regulator M12

M13

M16

M17 Frequency coarse selection

Out p

L

Cdiv 1

Outn

Cfix

CLK

Cc

Constant gain varactor

VCO clock buffer

Cdiv 3

Cdiv 2 LSB calibration C-DAC

Cc CLKb

MSB calibration C-DAC M14

M15 M10

M11 LC-VCO core

Figure 11: VCO top-level diagram including frequency calibration and tuning.

parasitic magnetic fields existent in a mixed signal SOC is far more important for a VCO operating in such a noisy environment than the slight degradation of the oscillator phase noise. To ease the frequency calibration process and also minimize the oscillator phase noise, the inductor value needs to be minimized, while the tank capacitance value needs to be maximized. Most existing oscillators use differential amplifiers with a tail current source [24–26]. Their drawbacks are first a reduced oscillating amplitude, which penalizes the signal to noise ratio, and second the tail current 1/ f and thermal noise up- and downconversion, resulted from the VCO amplifier switching action. Both effects penalize the VCO phase noise performance. Noise filtering was used at lower frequencies [24] to reduce the tail current noise impact. However, this method is not viable for high multi-GHz oscillators (5–10 GHz) due to the lack of high value inductors having high self-resonating frequencies (>10–20 GHz). The oscillator core was realized with a CMOS amplifier having both NFET (M10,11) and PFET (M12,13) cross-coupled differential stages. A grounded source stacked NFET and PFET amplifier was used to minimize the VCO power consumption resulted due to the larger transconductance achieved for a given current budget [19, 23]. The amplitude of oscillation depends on regulator’s output voltage Vreg, tank’s losses RL , amplifier’s equivalent threshold voltage Vtheq , and transconductance gmeq [15, 29]:  3 ∼ A= 1−

8

1 gmeq · RL

· Vreg +

1 3 · · Vtheq . 8 gmeq · RL

(3)

Therefore by adjusting the Vreg voltage the amplitude of oscillation can be altered. The oscillator uses a typical initial positive feedback loop gain of 2 (1.5–3 over process and

18

EURASIP Journal on Wireless Communications and Networking Cp

Msw

Out p

Cp

Out p

Cn Outn

Mpd

Mpd

Select

Msw

Mpu

Mpu

Mpd

Mpd

Select

I1

I2

Mpu Mpd

Rb

Cn Rb

Select Rd

I1

Digital GND (c)

I2

Cp

Mpu Mpd

Cd

Rg

Analog GND

Vreg

Msw 1

Msw 2

Rb

Cn

Outn

Msw

Out p

Cp

(b) Outn

Vreg

Cd Digital GND

Out p

(a)

Select Rd

Outn

Cn

Rb

Rg

Analog GND (d)

Figure 12: Frequency calibration capacitor legs: (a) all-NMOS switch, (b) CMOS switch, (c) CMOS switch with reduced pushing, and (d) CMOS switch with higher breakdown.

temperature corners) which ensures both a safe start-up and also achieves a minimum in the phase noise characteristic. Optimizing the VCO phase noise performance requires the maximum VCO amplitude within a given supply voltage budget and the process limited device breakdown voltage. The oscillating amplitude has a relatively low process and temperature variation, avoiding the need for an automatic amplitude control loop. To minimize the supply injected spurs, a high PSRR regulator is required to isolate the LC-VCO from the global supply lines [15]. The regulator needs to have a very low output noise voltage in order to limit the oscillator phase noise degradation via the supply pushing mechanism. The nonlinear voltage-dependent capacitances from the amplifier output nodes set the supply pushing level higher than few MHz/V, value that dominates the oscillator phase noise performance. Achieving phase noise levels as low as −120 dBc/Hz at 1 MHz offset requires supply pushing levels lower than 100 KHz/V. The amplifier gate capacitances have a positive voltage coefficient, while the drain-to-bulk capacitances have a negative voltage coefficient. A supply pushing cancellation architecture was implemented with gate to source shorted NFET and PFET dummy devices connected at the two output nodes of the oscillator (M14–17) that have a negative voltage coefficient, which together with the drain diffusion capacitance of the main amplifier and the frequency calibration network, cancel out the gate capacitance positive voltage coefficient. A perfect compensation is possible only for a given design corner. Over the PVT corners a residual voltage coefficient will result. The key to a low supply pushing gain is to maintain this residual voltage coefficient under a certain safety limit. The clock edges need to be fast enough when transitioning between two power supply domains (e.g., the transition from the VCO analog ground to the digital divider ground). To ensure enough gain for the multi-GHz clock, a clock buffer biased from the same clean VCO supply was used. The

buffer supply current spikes are perfectly synchronous with the VCO output clock and therefore the buffer can share the same supply with the VCO without degrading its phase noise. 11.1.

VCO frequency calibration network

Reducing the frequency synthesizer output clock phase noise requires a minimization of the oscillator gain. The targeted 0.25◦rms double-sided integrated phase noise (between 1 KHz and 10 MHz) requires an oscillator gain around few tens of MHz/V, which with a 1.3 V tuning voltage range (limited by the MOSFETs breakdown voltage) results in a relatively low-frequency tuning range. To achieve a functional oscillator over all process, temperature, and supply voltage corners, while using a narrow tuning range varactor, requires a highresolution frequency calibration network. The temperature variation of the oscillating frequency is about 0.2%, while a low supply pushing gain was achieved by using a pushing cancellation circuit. Reducing the VCO tuning range requires a low-frequency error, imposing a 0.1% frequency calibration resolution, which turns into a 0.2% frequency step. At the maximum operating frequency the 0.2% frequency step requires a 5 fF unit capacitor in the frequency calibration network for the selected inductor value. There exist several solutions to realize the switches for the frequency calibration network. Figure 12 presents the most popular existing switch implementations, together with the solution used in the present design. The all-NFET switches architecture presented in Figure 12(a) is widely used in integrated VCOs [25, 26]. It consists of a main NMOS differential switch (Msw ) that provides a low on-state resistance to connect the two capacitors C p and Cn to the LC tank, and two pull-down large L/W aspect ratio NFET devices (Mpd ) that bring the drain and source of the main switch to ground when it is ON. This maximizes Msw switch overdrive voltage, leading to a minimum Ron resistance for a given supply voltage headroom. The high on-state resistance of the Mpd

Adrian Maxim devices is not an issue since they provide only a DC level. The drain diffusion capacitance of the Mpd devices adds to the diffusion capacitance of the main switch (Msw ) to give the total nonlinear capacitance presented by the calibration leg to the LC tank. When the main switch is OFF, its drain and source are floating, their potential being set by the leakage currents. Having floating nodes in the calibration leg is not acceptable. If these potentials are driven to ground (e.g., by the NFET switches drain and source diffusion diodes leakage current), then at the maximum negative amplitude of the oscillation there is a risk of turning the drain and source diodes of the switches ON. This may lead to a significant loading of the LC tank and thus a severe degradation of the VCO phase noise. Figure 12(b) shows one possible solution to resolve the floating nodes potential. It uses two pull-up PFETs (Mpu ) in parallel with the C p and Cn capacitors of the calibration leg [23]. When the leg is not selected, these PFET switches short the floating nodes to the collectors of the VCO amplifier, providing a known potential level. Long and narrow channel PFETs were used to reduce the nonlinear capacitance shown to the LC tank, since their large Ron resistance is of no concern. When the main switch (Msw ) is OFF, it is required to present a minimum parasitic capacitance to the LC tank. The Mpu PFETs pull the source and drains of the Msw switch to the positive supply ensuring a minimal diffusion capacitance. The NFET pull-down and PFET pull-up devices constitute an inverter that drives the drain and source nodes of the main switch. The drawback of this implementation is the larger nonlinear capacitance shown to the LC tank due to the usage of two inverters per capacitor leg. Figure 12(c) presents one solution to reduce the nonlinear capacitance shown to the LC tank by replacing the two pull-up/pull-down CMOS inverters connected in the signal path, with a single inverter connected at the common-mode voltage [15]. The parasitic capacitances of the pull-up and pull-down devices are further isolated from the main switch with the high value Rb bias resistors. A moderately large value Rg resistor was connected in series with the gates of the MOS switches in order to isolate the drain diffusion output capacitance of the driving inverter from the frequency calibration leg. In a perfectly symmetric circuit this would have no impact since it is connected to an AC ground node. In reality any imbalance in the frequency calibration leg will reflect a fraction of the gate inverter nonlinear output capacitance (need to be kept negligible) back on the LC tank. The digital gate control signals that determine the ON or OFF state of the MOS switches in the calibration network come from the digital core of the IC and are referenced to the digital supplies, which carry a significant amount of noise. To avoid the noise leakage from the digital ground into the analog ground of the VCO, each digital control line has a dedicated Rd , Cd filter. The series resistance Rd increases the impedance looking towards the analog circuit, preventing the digital noisy current from going into the analog VCO ground, while the Cd capacitor connected at the digital ground closes locally the digital noise. To avoid noise coupling from the positive supply of the digital circuit, each digital control line is buffered with two inverters biased from

19 the same low noise and high PSRR regulator used by the LCVCO core. If the buffers would have been biased from the noisy global PLL supply, then the variation of the VCC supply voltage would propagate to the gates of the MOS switches, causing a parasitic modulation of their series channel resistance. Considering the parasitic capacitance of the MOS switch and the MIM capacitor of the calibration leg, the LC tank sees an RC network having three series connected capacitors from which the centre one that has a much smaller value is shorted by a voltage controlled resistor (Msw switch). Such a network is equivalent to a voltage controlled capacitor that appears in parallel with the LC tank and determines a parasitic modulation of the oscillating frequency. This variable capacitance results in an upconversion of the supply noise and spurs around the VCO carrier, degrading its phase noise performance. To solve this issue, a regulated voltage (Vreg ) was used to bias the inverters that buffer the digital control lines going to the MOS switches of the calibration network. Since there is no dynamic current going through these static input inverters of the frequency calibration network, they can be connected to the same regulator used by the LC-VCO core. Using a differential switch has the advantage of providing the minimum series resistance for a given supply voltage level and a targeted MOS switch parasitic capacitance value. However, the switch is exposed to the large peak-to-peak differential swing of the oscillator. Optimizing the VCO phase noise requires the maximization of this voltage. The targeted −100 dBc/Hz phase noise at 100 KHz offset requires a 3 V differential peak-to-peak amplitude that cannot be sustained by a single MOS switch in the calibration legs. A low phase noise oscillator design should have the single-ended amplitude as close as possible to the available headroom voltage. An optimal architecture should provide equal voltage stresses for all MOS devices from the VCO amplifier and from the frequency calibration network and tuning varactor. For the calibration leg shown in Figure 12(c) the MOSFET switches are the amplitude limiting factor [15]. Figure 12(d) presents a higher amplitude version of the single CMOS inverter-driven differential switch. It uses two grounded source switches (Msw 1 and Msw 2 ) instead of a single differential switch (Msw ). This doubles the maximum differential voltage sustained by the calibration leg allowing the required 3 V peak-to-peak differential swing. The price paid is doubling the series resistance and thus halving the quality factor of the calibration network. As there is no DC current in these MOS switches, they can tolerate a larger drain-to-source voltage (e.g., 1.5 V) than the process recommended maximum voltage (1.3 V). The frequency calibration range needs to cover the 10% process variation coming from both inductor value inaccuracy (small) and the tank capacitance variation (usually the dominant factor). Achieving a wide calibration range, while achieving the 5 fF capacitor step, requires at least an 8-bit resolution in the frequency calibration network. This is generally implemented as a capacitor DAC that switches the appropriately sized capacitor legs in or out of the LC tank. To accommodate the 40 fF minimum size MIM capacitor, while achieving a 5 fF unit capacitor step, a differential capacitor structure (doubles the minimum required capacitance

20

EURASIP Journal on Wireless Communications and Networking 50 Multiple varactor cell (b)

Oscillator gain (MHz/V)

40

30

20

Single varactor cell

(a)

10

0 0

0.25

0.5 0.75 Control voltage (V)

1

1.25

Figure 13: (a) Single accumulation-MOS varactor tuning gain; (b) multiple parallel-connected varactor cell with quasiconstant tuning gain.

unit) was used in conjunction with a 2-to-1 capacitor tap (see Figure 11). A 2-to-1 tap reduces the size of a capacitor connected to it by a factor of four when reflected back on the LC tank. The 8-bit frequency calibration DAC was split in two sub-DACs: an LSB-DAC connected at the 2-to-1 capacitor tap and an MSB-DAC connected directly on the LC tank. A minimum of two LSB bits need to be connected at the 2-to-1 tap in order to achieve the required 5 fF capacitor step. The accuracy of the MIM capacitors degrades sharply when going towards their minimum 40 fF size. Furthermore, maintaining a high-quality factor for the LC tank requires large-area series MOS switches that have sizable parasitic capacitances, which may limit the calibration resolution if they become comparable with the switched MIM capacitor size. To achieve a good monotonicity of the capacitor DAC, four LSBs where connected at the 2-to-1 tap, while the four MSBs were connected directly on the LC tank. Overlapping between the adjacent frequency ranges was built-in the capacitor DAC, such that the calibration algorithm can recover from decision errors. At each decision step of the successive approximation register (SAR) algorithm, the amount of capacitance that is left unswitched in the DAC is slightly higher than the capacitance that is switched in or out of the LC tank. Therefore if an erroneous decision of switching-out a capacitor is taken in a previous calibration step (e.g., due to a supply glitch), then there is enough capacitance left unswitched to achieve the desired value of the LC tank capacitance. 11.2. Constant gain Varactor Figure 13(a) illustrates the tuning gain variation of a single accumulation MOS capacitor which has a bell-shape characteristic. A wide variation of the tuning gain requires a more sophisticated PLL loop filter in order to achieve a constant damping factor and loop bandwidth over the entire frequency range. To solve this issue, several MOS capacitors were connected in parallel, while their control voltages are shifted such that the individual peak tuning gain points are

uniformly distributed over the entire control voltage range (Figure 13(b)). The equivalent tuning gain has an almost constant plateau, the gain ripple depending on the number of parallel cells. This design uses ten MOS capacitors in parallel to achieve less than 15% tuning gain ripple over all design corners. Figure 14 presents the detailed schematic of the constant gain varactor. A differential varactor cell was built using two accumulation MOS capacitors Cvarpi /Cvarni , having the gates connected towards the LC tank and the wells going to the loop filter control voltage (Vctrl ). To prevent the discharge of the loop filter integration capacitance due to the significant leakage current of the MOS capacitors bulk, a simple source follower buffer stage was interposed between the loop filter and the varactor control node. The MOS capacitors are AC coupled to the LC tank using the Ccip /Ccin fixed capacitors. This allows a separate DC bias voltage to be brought to the gate of each individual MOS capacitor, which shifts the position of the corresponding peak gain point. The R p resistors keep floating from the signal perspective the nodes between the AC coupling capacitors and the MOS capacitor. The simplest way to generate the offset voltages is using a resistor divider biased from the low noise VCO regulator. The noise of the resistor divider may significantly impact the VCO output phasenoise. Filtering capacitors can be used to limit the divider noise contribution, their main drawback being a large required capacitor area. To reduce the supply spur injection through the resistor divider, present design has implemented a switched capacitor bias network. The voltage levels generated by the resistor divider (Rdiv 1–10 ) are sampled periodically on a set of storage capacitors (Cdiv 1–10 ) at a low-frequency rate. Transmission gate switches Tg1–10 were used to sample the offset voltages (Voff1–10 ) on the corresponding storage capacitors. The Cdivi capacitors were connected directly to the gates of the accumulation MOS varactor. The main leakage components are given by the drain and source diffusions of the MOS varactors, which may results in a discharge of the Cdivi storage capacitors. The ripple on the offset voltage

Adrian Maxim

21 Vreg Rdiv 0

Out p

Offset bias generator

Outn Cvarp 1

Cc1p

Cvarn 1 Cc1n

Rp

+ Rdiv 1

Tg1

Cdiv 1

Rp Voff1 Cvarp 2 Cvarn 2

Cc2p Rp

Rdiv 2

Tg2

Cdiv 2

Tg3

Cdiv 3






Rp Voff3 Cvarp 10

Cvarn 10 Cc10n

Rp

Rdiv 10 Tg10

Parallel-connected multicell offset biased MOS varactor






Cc10p

Rdiv 9

Cc2n

Voff2 Cvarp 3 Cvarn 3 Cc3n

Cc3p

Loop filter

BUF

Rp

Rp Rdiv 3

Vctrl

Rp XTAL oscillator

Div. M

Voff10

Cdiv 10

Figure 14: Quasiconstant tuning gain accumulation-MOS varactor using offset bias parallel-connected legs.

VCO

Cc I nv 1 Inv 2

Ltune Inv 3

Inv 4

Inv 5 CLKb

Cc

Inv 1 Inv 2

Rcm

VDD

CLK

Inv 3

Inv 4

Inv 5

(a)

Cc

Ltune

Cm

Cc

Mcml

VCO Itail

Inv 1 Inv 2

Ccm CLK Cm

CLKb

Cl

Cl

(b)

Figure 15: Output clock buffers using: (a) CMOS inverters; (b) tuned load CML inverter.

nodes leads to output spurs whose amplitude is proportional with the Kvco oscillator gain and inversely proportional to the refresh frequency frefresh . The refresh rate of the switchedcapacitor bias generator needs to be high enough such that the resulting voltage ripple is lower than 1 μV, which results in negligible spur (< −80 dBc). To minimize the ripple at the offset voltage nodes, each sampling switch has a pair of halfsize dummy switches connected on its either sides to cancel (at least partially) the channel charge injection and reduce the clock feedthrough. The price paid is the twice as large leakage current due to the extra source and drain diffusions connected to the storage capacitors (Cdivi ). By having the sampling switches turnedoff most of the time minimizes the supply spur injection. The power of the injected tone is reduced by the sampling signal duty-cycle factor. To achieve a large attenuation, the sampling signal needs to have a very low duty cycle (1 to 5%). 12.

VCO OUTPUT CLOCK BUFFER

The LC oscillator generates a low phase noise sine-wave with a 3 V peak-to-peak differential amplitude. The multi-GHz

clock needs to drive both the frequency synthesizer divider and the RF front-end mixers. Furthermore, the kickback due to the digital circuits switching can be detrimental to the oscillator phase noise performance, mandating an isolation buffer between the VCO and its highly nonlinear load capacitance. This buffer has two main goals: first to squareup somewhat the VCO sine-wave and second to increase the drive capability of the clock path. At these high frequencies the achievable gain of a differential pair is fairly low (typically 3–10) even in high fT deep-submicron CMOS processes. Therefore only a limited amount of clock waveform squaring is possible. Figure 15(a) shows a straight CMOS implementation of the VCO clock buffer that requires a large number of cascaded stages in order to achieve the desired capacitive drive strength. This solution takes a large supply current and is prone to clock pulse width distortion due to the device VT mismatches. Figure 15(b) presents the detailed schematic of the proposed VCO output clock buffer. The oscillator is biased from a dedicated supply to avoid supply noise injection. The driven mixers are operated from a separate supply. The finite mismatches between the devices in the clock path (transistors, resistors, and parasitic

EURASIP Journal on Wireless Communications and Networking

capacitances) lead to a nonzero common-mode to differential gain. The transition between the two power supply domains needs to be performed inside the VCO clock buffer. If the transition is done at a point where the clock is still sinewave looking, the higher sensitivity to supply noise leads to a severe degradation of the clock phase noise. To limit the crosstalk between the analog and digital supply domains, the first gain stages (Inv 1 , Inv 2 ) of the clock buffer were built inside the VCO metal cage, while the third CML gain stage resides in the mixer core. The clock bus running from the analog to the digital section of the buffer is shielded with a coaxial metal structure connected to the analog ground. The length of the clock bus was minimized in order to reduce the parasitic capacitive loading at the clock lines. A high loading capacitance may result in a subsequent slowing down of the clock slew rate and expose again the signal to supply noise injection. The intrinsic noise of the different stages in the clock buffer path also contribute to phase noise. If enough gain (Av > 3) is achieved in the first gain stage, then the phase noise degradation is dominated by the front-end stages. The edge squaring process is in fact a phase sampling action, which results in aliasing of the wideband noise from the front-end buffer stages. Once the clock edges are squared up, a proper sizing of the following stages with respect to their corresponding load capacitance needs to be used, such that they will not significantly slow down the signal transitions, which may create a second point of wideband noise aliasing. Standard clock buffers require a large number of cascaded pseudodifferential inverter stages in order to drive large load capacitances (e.g., 1 pF). This leads to using a significant percentage of the IC power in the high-frequency clock path. Inductive peaking was used in the past to speedup the edges and thus reduce somewhat the power in the clock tree path. A larger power consumption reduction can be obtained by using an inductive tuned clock tree [27]. It consists of resonating the large load capacitance (CL ) with a shunt inductor (Ltune ). Therefore the size of the last clock buffer stage can be much smaller, since it needs only to maintain the oscillating clock waveform. The load capacitance tuning was possible due to the narrowband nature of the clock. A reduced number of gain stages is required in a tuned clock path (only three in this application), further reducing the power consumption in the clock path. The inductive tuning of the clock tree trades delay for a higher edge slew rate. A special care needs to be devoted to the tuning inductor layout. The parasitic coupling between the clock buffer and the oscillator can significantly degrade the VCO phase noise, while the coupling from the oscillator to the clock buffer output stage may result in a large reduction of the clock amplitude due to the summation of two signals having the same frequency, but different phases. To reduce the parasitic magnetic coupling to the VCO-BUF tuning inductor, an inductor-in-cage structure was used, similar to the VCO tank inductor. The substrate coupling between the two inductors was reduced by placing a low doped native P-well layer below the inductors. Fast clock edges require also a reduction of the capacitive load presented by the differential CML gain stages to the

20 Phase noise (dBc/Hz)

22

40 60 80 100 120 140

100

1K

10 K

100 K

1M

10 M

Frequency offset (Hz)

Figure 16: LC-VCO phase noise in open-loop operation.

front-end driving inverters. Miller capacitance neutralization was used to achieve this goal [32]. It consists of connecting two capacitors (Cm ) matched with the Cgd of the main gain stage devices from the gate of each differential pair device to the drain of the complementary device (cross-coupled capacitors). Therefore each input of the differential pair sees in essence two equal capacitors that have on the second terminal signals that are equal in value, but of opposite signs, resulting in a cancellation of the capacitor current from the input circuit perspective. The low value (few fF) Miller compensation capacitors were realized with metal interconnect capacitors (MIM capacitors have a minimum value of 40 fF in the selected CMOS process). 13.

EXPERIMENTAL RESULTS

The above-presented supply partition, filtering, and regulation techniques have been used to reduce the phase noise and coupled spurs of a 0.13 μm CMOS frequency synthesizer for a dual-band 802.11 a/b/g SOC. A low VCO phase noise degradation due to parasitic magnetic coupling and supply or substrate noise injection is crucial for meeting the transceiver sensitivity target. Figure 16 presents the openloop phase noise plot of the 5 GHz oscillator, while the entire digital side of the SOC is active. The phase noise is lower than −120 dBc/Hz at 1 MHz offset from the carrier, when measured after the divide by two of the quadrature I/Q generator. This value is very close to the estimated VCO phase noise, based on the LC tank quality factor and oscillator amplifier noise figure, showing a negligible phase noise degradation due to supply pushing, substrate injection, and parasitic magnetic coupling. This proves that the dual-regulator architecture and the inductor-in-cage layout are effective in reducing the secondary phase noise degradation effects. A very low 1/ f 3 corner frequency was achieved (around 5 KHz), showing the effectiveness of the tail-free voltage-mode bias of the VCO, which eliminates the tail current noise upconversion. Figure 17 presents the PLL output clock phase noise in the 802.11a mode, after a supplementary divide by 2 connected after the I/Q generator. A relatively large loop bandwidth (500 KHz) was selected in order to adequately reject any low offset frequency spur coupled to the VCO. This value is close to the optimum PLL bandwidth which is given by

23 Phase noise (dBc/Hz)

Adrian Maxim 90

Output CLK PN after divide by 2

110 130 150 Equipment accuracy limit

170 190

1K

10 K

100 K

1M

10 M

Frequency offset (Hz)

Figure 17: PLL output clock phase noise with entire digital core running.

the cross-over point of the VCO phase noise characteristic with the PLL front-end phase noise reflected at the PLL output. The in-band phase noise is −118 dBc/Hz, while the total phase noise integrated from 1 KHz to 10 MHz is as low as 0.25◦ rms, value that is substantially better than the 802.11 a/b/g requirement. The doted line in the phase noise plot represents the accuracy limit of the phase noise measurement equipment based on the delay line discriminator technique. Figure 18(a) presents the close-in frequency spectrum and Figure 18(b) shows the far-out frequency spectrum of the PLL output clock after it is downconverted to a low IF frequency. The reference spurs are lower than −85 dBc, while the major spurs coupled from the digital blocks are lower than −78 dBc (ADC, digital PLL, and digital core). These low value coupled spurs prove the effectiveness of the multiregulator PLL architecture. Figure 19 presents a detail of the 802.11 a/b/g SOC die photo, showing the frequency synthesizer floor-plan (the two caged inductors of the 2.5 GHz and 5 GHz LC-VCOs are not visible). A circular signal flow was used at the PLL top level, with minimal signal line lengths for the multi-GHz connections (VCO-to-BUF and BUF-toDiv.N) and with a longer length for the VCO control line that was shielded with a coaxial metal structure. One can observe that the different series and shunt regulators together with the test circuitry occupy about half the total PLL die area. However, this large area and the relative low-power efficiency are well justified by the excellent PLL noise and spur performance, while operating on the same die with a noisy digital core. Modern CMOS processes offer a deep N-well option [30, 31] that can be used to isolate the local substrate of sensitive analog blocks from the noisy global SOC substrate. The key role of the deep N-well is to collect and direct towards the unregulated supply the noise injected capacitively by the noisy global substrate and prevent it from getting to the bulks of the NFETs, from where it may leak into the signal path through the device body effect. To achieve this goal, the series resistance of the N-well walls needs to be minimized. This can be achieved, for example, by breaking a larger deep N-well in several smaller deep N-wells that share the lateral N-well walls. Increasing the N-well walls perimeter reduces significantly the series resistance to the analog supply, making this the main closing path for the substrate injected noise. All major blocks inside the PLL are placed inside local P-wells connected to the clean analog ground, while the

surrounding N-well ring and the deep N-well isolation layer are connected to the global (unregulated) supply and not at the regulator output in order to prevent the substrate noise contamination of the clean regulated voltages. To make effective the deep N-well isolation (at least 40 dB attenuation of the high-frequency substrate noise), its area needs to be kept to a minimum. Although placing the deep N-well layer under the N-well in which the PFETs are residing results in a more compact layout (shorter signal lines with lower parasitic capacitances), in mixed signal SOCs it is preferred to keep the PFETs outside the deep-N-well, in spite the large separation required between the NFETs deep N-well and the PFETs N-well. It is always preferred to close on-chip the magnetic loops (achieve a much lower loop area), rather than let the substrate noise to go off-chip through the Vdd supply bondwires and circulate in a large loop that is strongly dependent on the PCB layout. An even more dangerous situation is when the loop contains switching elements and the area of the loop changes in time at a given low-value frequency. This can result in large spurious tones in the LCVCO due to the magnetic coupling between the tank inductor and the variable area parasitic loop. Using caged inductors help to some extent reducing this type of spurs. Bypass capacitors were used to close on-chip to ground the substrate injected noise. In mixed signal RF ICs that have digital cores operating at multi-GHz frequencies the deep N-well isolation is less effective, requiring a careful placement of the analog and digital blocks in the top-level layout floor-plan, a reduction of the deep N-well protected areas, and the use of low doped native layer moats to isolate the analog circuitry from the digital core. At very high frequencies (5–10 GHz) all the local substrates are shorted to the global substrate by the relatively large deep N-well parasitic capacitance. The smaller the area of a deep N-well, the larger the frequency up to which it provides a good isolation. All major analog and digital blocks are surrounded by metal cages that attenuate the parasitic magnetic coupling. However, even the thick top metal layer of the selected 0.13 μm CMOS process offers only 15–20 dB attenuation to the magnetic coupling above 5 GHz. Both the VCO and VCO-BUF inductors are build inside metal cages in order to minimize the magnetic coupling from the surrounding bondwires, or any other magnetic loop present in the large SOC, reducing thus the spur and phase noise injection.

24

EURASIP Journal on Wireless Communications and Networking

20

Ref. 0 dBm

Att. 10 dB

40

RBW 1 KHz

20

Ref. 0 dBm

Att. 10 dB

RBW 1 KHz

40

ADC Digital PLL

60

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4

80

80

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Reference spurs 2

100

120

450 KHz Coupled spurs (dBc)

Span 4.5 MHz

120

(a)

3 MHz Reference spurs (dBc)

Span 30 MHz

(b)

Figure 18: Output clock frequency spectrum: (a) close-in coupled spurs; (b) far-out reference spurs.

Frequency synthesizer Shunt Shunt reg. reg.

XTAL Loop filter

Dividers

BUF

PFD

VCO BUF

CP VCO series regulator

Test & calibration

Figure 19: SOC die photo detail showing PLL layout floor-plan.

14.

CONCLUSIONS

This paper presents several power supply partitioning, filtering, and regulation techniques aimed at supply noise and spur rejection in frequency synthesizers operating in large mixed analog-digital SOCs. To prove experimentally their effectiveness, they were implemented in a multi-GHz PLL operating in the same die with a dual-band 802.11 a/b/g SOC. The test chip was realized in a 0.13 μm CMOS process. Keeping a clean global PLL supply and minimizing the noise and spur coupling between different analog and digital PLL building blocks requires that all supply current spikes generated by the digital circuits be closed locally with the help of dedicated shunt regulators having a high-value reverse PSRR. The boundary between the analog and digital supply domains was placed at the charge-pump high impedance output node, avoiding the leakage into the PLL signal path of the noise between the two supply domains. Series regulators were used to bias all sensitive analog blocks (XTAL oscillator and VCO) that require a supply line. To further improve the PSRR and noise performance of serial regulators, a dual-regulator architecture was proposed. A first wideband bandgap referenced regulator provides most of the

PSRR performance, while a second narrow-bandwidth VT /R referenced regulator was used to ensure a low output noise performance. A passive feedforward loop filter was proposed that has an excellent PSRR rejection and also allows the on-chip integration of the loop filter capacitance. To minimize the PLL front-end noise and spurs sensitivity, the gain of the oscillator was reduced by using a high accuracy frequency calibration network that compensates for the process variation of the oscillating frequency. Furthermore, a virtually flat VCO tuning gain over the entire frequency range was ensured by using several accumulation MOS varactors connected in parallel and having the bias voltage shifted one from another, such that the individual C(V ) gain peaks are uniformly distributed over the entire VCO tuning range. Using a dedicated series or shunt regulator for each PLL building block allows the SOC operation without the costly RC or LC off-chip filters on the frequency synthesizer supply lines, reducing significantly the external component count the proposed multiregulator PLL architecture delivers a very low 0.25◦ rms integrated noise, while the coupled spurs are lower than −78 dBc, performance that is compatible with the most stringent modern wireless communication standards. REFERENCES [1] D. Mijuskovic, M. Bayer, T. Chomicz, et al., “Cell-based fully integrated CMOS frequency synthesizers,” IEEE Journal of Solid-State Circuits, vol. 29, no. 3, pp. 271–279, 1994. [2] I. A. Young, J. K. Greason, and K. L. Wong, “A PLL clock generator with 5 to 10 MHz of lock range for microprocessors,” IEEE Journal of Solid-State Circuits, vol. 27, no. 11, pp. 1599– 1607, 1992. [3] A. Maxim, B. Scott, E. M. Schneider, M. L. Hagge, S. Chacko, and D. Stiurca, “A low-jitter 125-1250-MHz processindependent and ripple-poleless 0.18-μm CMOS PLL based on a sample-reset loop filter,” IEEE Journal of Solid-State Circuits, vol. 36, no. 11, pp. 1673–1683, 2001.

Adrian Maxim [4] A. Maxim, “A 0.16-2.55-GHz CMOS active clock deskewing PLL using analog phase interpolation,” IEEE Journal of SolidState Circuits, vol. 40, no. 1, pp. 110–131, 2005. [5] J. G. Maneatis, “Low-jitter process-independent DLL and PLL based on self-biased techniques,” IEEE Journal of Solid-State Circuits, vol. 31, no. 11, pp. 1723–1732, 1996. [6] I. I. Novof, J. Austin, R. Kelkar, D. Strayer, and S. Wyatt, “Fully integrated CMOS phase-locked loop with 15 to 240 MHz locking range and ±50 ps jitter,” IEEE Journal of Solid-State Circuits, vol. 30, no. 11, pp. 1259–1266, 1995. [7] L. Lin, L. Tee, and P. R. Gray, “A 1.4 GHz differential low-noise CMOS frequency synthesizer using a wideband PLL architecture,” in Proceedings of IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC ’00), pp. 204–205, 458, San Francisco, Calif, USA, February 2000. [8] D. W. Boerstler, “A low-jitter PLL clock generator for microprocessors with lock range of 340-612 MHz,” IEEE Journal of Solid-State Circuits, vol. 34, no. 4, pp. 513–519, 1999. [9] J. G. Maneatis, J. Kim, I. McClatchie, J. Maxety, and M. Shankaradas, “Self-biased high-bandwidth low-jitter 1-to4096 multiplier clock generator PLL,” IEEE Journal of SolidState Circuits, vol. 38, no. 11, pp. 1795–1803, 2003. [10] J. Lee and B. Kim, “A low-noise fast-lock phase-locked loop with adaptive bandwidth control,” IEEE Journal of Solid-State Circuits, vol. 35, no. 8, pp. 1137–1145, 2000. [11] A. Maxim, “A low voltage, 10-2550MHz, 0.15μm CMOS, process and divider modulus independent PLL using zero-VT MOSFETs,” in Proceedings of the 29th European Solid-State Circuits Conference (ESSCIRC ’03), pp. 105–108, Estoril, Portugal, September 2003. [12] A. Maxim and M. Gheorghe, “A sub-1psrms jitter 1-5GHz 0.13μm CMOS PLL using a passive feedforward loop filter with noiseless resistor multiplication [frequency synthesizer application],” in Proceedings of IEEE Radio Frequency Integrated Circuits Symposium (RFIC ’05), pp. 207–210, Long Beach, Colo, USA, June 2005. [13] A. Hajimiri and T. H. Lee, “A general theory of phase noise in electrical oscillators,” IEEE Journal of Solid-State Circuits, vol. 33, no. 2, pp. 179–194, 1998. [14] J. J. Rael and A. A. Abidi, “Physical processes of phase noise in differential LC oscillators,” in Proceedings of the IEEE Custom Integrated Circuits Conference (CICC ’00), pp. 569–572, Orlando, Fla, USA, May 2000. [15] A. Maxim and C. Turinici, “9.953-12.5GHz 0.13μm CMOS LC VCO using a high resolution calibration and a constant gain varactor,” in Proceedings of the IEEE Custom Integrated Circuits Conference (CICC ’05), pp. 545–548, San Jose, Calif, USA, September 2005. [16] M. A. Margarit, J. L. Tham, R. G. Meyer, and M. J. Deen, “A low-noise, low-power VCO with automatic amplitude control for wireless applications,” IEEE Journal of Solid-State Circuits, vol. 34, no. 6, pp. 761–771, 1999. [17] A. Zanchi, C. Samori, A. L. Lacaita, and S. Levantino, “Impact of AAC design on phase noise performance of VCOs,” IEEE Transactions on Circuits and Systems II, vol. 48, no. 6, pp. 537– 547, 2001. [18] J. W. M. Rogers, D. Rahn, and C. Plett, “A study of digital and analog automatic-amplitude control circuitry for voltagecontrolled oscillators,” IEEE Journal of Solid-State Circuits, vol. 38, no. 2, pp. 352–356, 2003.

25 [19] A. Maxim, “A 2-5GHz low jitter 0.13μm CMOS PLL using a dynamic current matching charge-pump and a noise attenuating loop-filter [frequency synthesizer application],” in Proceedings of the IEEE Custom Integrated Circuits Conference Digest of Technical Papers (CICC ’04), pp. 147–150, Orlando, Fla, USA, October 2004. [20] Y. Koo, H. Huh, Y. Cho, et al., “A fully integrated CMOS frequency synthesizer with charge-averaging charge pump and dual-path loop filter for PCS- and Cellular-CDMA wireless systems,” IEEE Journal of Solid-State Circuits, vol. 37, no. 5, pp. 536–542, 2002. [21] K. Shu, E. S´anchez-Sinencio, J. Silva-Mart´ınez, and S. H. K. Embabi, “A 2.4-GHz monolithic fractional-N frequency synthesizer with robust phase-switching prescaler and loop capacitance multiplier,” IEEE Journal of Solid-State Circuits, vol. 38, no. 6, pp. 866–874, 2003. [22] B. De Muer and M. S. J. Steyaert, “A CMOS monolithic ΔΣcontrolled fractional-N frequency synthesizer for DCS-1800,” IEEE Journal of Solid-State Circuits, vol. 37, no. 7, pp. 835–844, 2002. [23] A. Maxim, “A 9.953/10.7/12.5GHz 0.13μm CMOS LC oscillator using capacitor calibration and a VT /R based low noise regulator,” in Proceedings of IEEE Radio Frequency Integrated Circuits Symposium (RFIC ’05), pp. 411–414, Long Beach, Colo, USA, June 2005. [24] E. Hegazi, H. Sj¨oland, and A. A. Abidi, “A filtering technique to lower LC oscillator phase noise,” IEEE Journal of Solid-State Circuits, vol. 36, no. 12, pp. 1921–1930, 2001. [25] S.-P. Woyciehowsky and R. N. Nottenburg, “10GHz LC-tuned VCO with coarse and fine frequency control,” Electronics Letters, vol. 33, no. 11, pp. 917–918, 1997. [26] A. Kral, F. Behbahani, and A. A. Abidi, “RF-CMOS oscillators with switched tuning,” in Proceedings of the IEEE Custom Integrated Circuits Conference (CICC ’98), pp. 555–558, Santa Clara, Calif, USA, May 1998. [27] S. Sidiropoulos, N. Acharya, P. Chau, et al., “An 800 mW 10 Gb Ethernet transceiver in 0.13μm CMOS,” in Proceedings of IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC ’04), vol. 1, pp. 168–520, San Francisco, Calif, USA, February 2004. [28] S. Lizhang and D. Nelson, “A 1.0 V GHz range 0.13μm CMOS frequency synthesizer,” in Proceedings of the IEEE Custom Integrated Circuits Conference (CICC ’01), pp. 327–330, San Diego, Calif, USA, May 2001. [29] A. Maxim, “A multi-rate 9.953-12.5-GHz 0.2-μm SiGe BiCMOS LC oscillator using a resistor-tuned varactor and a supply pushing cancellation circuit,” IEEE Journal of Solid-State Circuits, vol. 41, no. 4, pp. 918–934, 2006. [30] J.-G. Su, H.-M. Hsu, S.-C. Wong, C.-Y. Chang, T.-Y. Huang, and J. Y.-C. Sun, “Improving the RF performance of 0.18μm CMOS with deep n-well implantation,” IEEE Electron Device Letters, vol. 22, no. 10, pp. 481–483, 2001. [31] D. Kosaka, M. Nagata, Y. Hiraoka, et al., “Isolation strategy against substrate coupling in CMOS mixed-signal/RF circuits,” in Proceedings of 18th International Conference on VLSI Circuits (VLSI ’05), pp. 276–279, Kyoto, Japan, June 2005. [32] A. Maxim, “A 10Gb/s SiGe compact laser diode driver using push-pull emitter followers and miller compensated output switch,” in Proceedings of the 29th European Solid-State Circuits Conference (ESSCIRC ’03), pp. 557–560, Estoril, Portugal, September 2003.

26 Adrian Maxim was born in Ias¸i, Romania, in 1968. He received the B.S.E.E. degree in 1992 and the M.S.E.E. degree in 1994 from the Technical University of Iasi, Romania. He received the Ph.D. degree (1997) from the Technical University of Iasi, Romania, and the National Polytechnic Institute of Toulouse, France, for his work on SPICE macromodeling of semiconductor devices. He was a Teaching Assistant (1994–1997) at the Department of Electronics and Telecommunications, Technical University of Iasi, Romania, where he was involved in research on semiconductor devices physics and modeling. During 1998 he was an Invited Professor at the National Polytechnic Institute of Toulouse, France. From 1998 to 2001, he was with Crystal Semiconductor Division of Cirrus Logic, Austin, Tex, as a Senior Mixed Analog-Digital Design Engineer and worked on multiGHz frequency synthesizers for large mixed analog-digital SOCs. From 2001 to 2004 he was with Maxim Integrated Products as a Senior Member of Technical Staff in the Fiber Optic Division, designing ICs for 10 Gbps optical links and clocking applications. He is now with Silicon Laboratories, Austin, Tex, as a Senior RF architect working on RF tuners and wireless transceivers. His research interests are in advanced PLL synthesizer and RF front-end architectures for wireless and wireline applications.

EURASIP Journal on Wireless Communications and Networking

Hindawi Publishing Corporation EURASIP Journal on Wireless Communications and Networking Volume 2006, Article ID 86531, Pages 1–11 DOI 10.1155/WCN/2006/86531

CMOS Silicon-on-Sapphire RF Tunable Matching Networks Ahmad Chamseddine,1, 2 James W. Haslett,1, 2 and Michal Okoniewski1, 2 1 Department 2 TRLabs,

of Electrical and Computer Engineering, University of Calgary, Calgary, AB, Canada T2N 1N4 Department of Electrical and Computer Engineering, University of Calgary, Calgary, AB, Canada T2L 2K7

Received 28 October 2005; Accepted 9 January 2006 This paper describes the design and optimization of an RF tunable network capable of matching highly mismatched loads to 50 Ω at 1.9 GHz. Tuning was achieved using switched capacitors with low-loss, single-transistor switches. Simulations show that the performance of the matching network depends strongly on the switch performances and on the inductor losses. A 0.5 μm siliconon-sapphire (SOS) CMOS technology was chosen for network implementation because of the relatively high-quality monolithic inductors achievable in the process. The matching network provides very good matching for inductive loads, and acceptable matching for highly capacitive loads. A 1 dB compression point greater than +15 dBm was obtained for a wide range of load impedances. Copyright © 2006 Ahmad Chamseddine et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

1.

INTRODUCTION

Matching impedance networks have become ubiquitous in all radio-frequency (RF) transmitters and receivers, especially in wireless mobile devices such as handheld computers (PDs) and cellular phones. Fixed matching networks are inserted between the power amplifier (PA) module and the antenna. However, antenna input impedance is affected by the presence of surrounding objects [1–4], and can vary considerably with the antenna close to the human body or with the position of the hand on a handset. The few published measurements of those variations showed a mismatch that can cause more than half of the transmitted power to be reflected [5]. When that mismatch occurs between the antenna and the PA, the radiated power efficiency decreases, increasing the demand on the battery. To address this issue, tunable matching networks have been considered by researchers in recent times [6–9]. Such circuits, known as antenna tuning units (ATUs), can be realized using tuned L-match, T-match, or Π-match (or a cascade of many sections of them) sections whose components can be controlled electronically through different algorithms such as the genetic algorithm, or simulated annealing. RF MEMS-based matching networks have been the subject of substantive efforts for the last decade [10]. However, their use remains limited to microwave and high-frequency applications (above 20 GHz). Issues of reliability, actuation voltage, and packaging prevent their acceptance in

commercial applications. Recently, an RF MEMS impedance tuner at 6–20 GHz was fabricated [11], but its impedance matching region at 6 GHz was limited. Recent advancements in CMOS-based IC technology have made it, arguably, the main contender for volume wireless products. A CMOSbased ATU was recently studied [12], demonstrating promising performance. In this work, the design and simulation results of different switching topologies using a commercial 0.5 μm siliconon-sapphire (SOS) UTSi technology [13] at 1.9 GHz are described. We analyze our results primarily in terms of S21 parameters, as S21 encompasses both the reflection loss and the loss in the matching network. An optimized switch circuit is used to design switchedcapacitor-based matching networks for 1.9 GHz operation, dedicated to matching loads within the voltage standing wave ratio (VSWR) circle of 5.6. It should be noted that the fabrication process provided transistors with constant widths and variable lengths. The transistor used in this work is an n-channel FET whose length can vary between 0.5 and 1 μm, and its finger width is fixed at 18 μm. The number of fingers ranges from 3 to 61 for this type of device. Furthermore, the SOS MOSFETs are different from bulk MOSFETs in that there is no substrate connection. In the commercial design kit used in this work, the device model P-channel body (NMOS) is tied to −50 V in order to avoid forward biasing the junction diodes under all signal conditions.

2

EURASIP Journal on Wireless Communications and Networking VH VL

R 1

2 R

(50 Ω)

1

(50 Ω)

2

VH VL

VH VL

R

Figure 2: The transmission gate. Figure 1: Single-transistor switch. R

2.

VH VL

RF SWITCH

Switches used in digital and low-frequency applications are usually characterized by their switching time and input capacitances. In RF applications, however, these metrics may not be adequate to describe their real properties. Instead, three parameters are commonly scrutinized before choosing a switch: the losses in ON and OFF states, known as insertion loss (IL) and isolation (ISO), respectively, and the linearity of the switch specified by its 1 dB compression point in the ON state. IL and ISO are obtained when the switch is connected in series with a 50 Ω RF source and a 50 Ω load resistance. A good switch should present low loss, high linearity, and high isolation. Hence, optimization must account for both ON and OFF states of the switch. The next subsections compare different switching circuits and select the one having the best tradeoff of IL, ISO, and linearity. All simulations and optimizations were performed using Agilent-ADS software, using the technology file provided by the process manufacturer. 2.1. Single-transistor switch A single-transistor switch (STS) represents the simplest switching topology, as shown in Figure 1. NMOS is usually used rather than PMOS since the NMOS has larger transconductance and higher electron mobility. In this circuit, the drain and source are biased equally by 0 V through bias resistors of 10 kΩ (not shown in the schematic). The control voltage is applied to the gate through a 10 kΩ resistor as well with values of +3 V (ON state) and −1 V (OFF state). These values can be adjusted upward or downward to accommodate a required dc signal path bias, or to avoid the negative supply. 2.2. Transmission gate switch The drawback of the STS is its increased nonlinearity with increased signal power. This is due to the dependency of the on-resistance on the input voltage amplitude. The transmission gate (TG) shown in Figure 2 accommodates greater voltage swings because the on-resistance is relatively signalindependent. However, such a switch requires complementary clocks to turn the transistors ON or OFF simultaneously. In this circuit, the drains and sources are biased equally by 0 V through bias resistors of 10 kΩ (not shown in the schematic). The high (3 V) and low (−1 V) control voltages are applied to the gates through 10 kΩ resistors.

1

2 R

VH VL

Figure 3: The resonant transmission gate (TG Res).

2.3.

The resonant transmission gate (TG Res)

An efficient way to improve the isolation of the TG switch consists of adding a shunt inductor that resonates with the off-state parasitic capacitances as shown in Figure 3. The value of the inductor is calculated based on the value of the √ off-state capacitances at the operating frequency ω0 = ( L · C)−1 , where C is the off-state capacitance of the switch. 2.4.

The LC-resonance switch

The LC-resonance switch depicted in Figure 4 was first suggested in [14]. In the OFF-mode, transistors M1 and M2 are ON, which will cause a parallel resonance formed by L and C1 that will isolate the signal. In the ON-mode, M1 and M2 are OFF, and a series resonance occurs through the L-C2 path that will allow the signal to pass. Figure 5 shows the insertion loss and isolation of the four different switching topologies as a function of the number of fingers (nf) of the transistors. Table 1 summarizes the best tradeoff between IL and ISO of these switches. The TG and TG Res have the same IL. However, TG Res achieves a much better isolation. When both NMOS and PMOS transistors have 36 fingers, the required value of the resonance inductor is then 11.54 nH at 1.9 GHz. The quality factor (Q) of the inductor is 20, which is available in the SOS fabrication process. The behavior of the LC resonance switch depends on the quality factor of the inductor. The best tradeoff between its IL and ISO was obtained for a number of fingers of 61, for both M1 and M2. The inductor value necessary to resonate with C1 at 1.9 GHz is 3.2 nH (Q = 20), and C1 = C2 = 2.2 pF. 3.

SWITCH ANALYSIS

The target matching network will use banks of parallel switched capacitors connected to ground through grounded

Ahmad Chamseddine et al.

3 C2

L

Switch

1

Zin

2 C1

M1

(50 Ω)

M2

Figure 6: Source-grounded switch configuration. Figure 4: The LC-resonance switch.

0

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−1.5 −15 −2 −20

−2.5

Isolation (dB)

Insertion loss (dB)

−0.5

STS (nf = 36) TG (nf = 36) TG Res (nf = 36) LC resonance (nf = 61)

−30

3

8

13 18 23 28 33 38 43 48 Number of fingers

IL LC Res IL TG & TG Res IL STS ISO TG

53 58

ISO LC Res, L = 3.2 nH ISO STS ISO TG Res, L = 11.54 nH

Figure 5: IL and ISO of all the switches, the technology limits the number of fingers to 61.

Table 1: Optimal IL and ISO of the different switching topologies. STS (nf = 36) TG (nf = 36) TG Res (nf = 36) LC resonance (nf = 61)

IL (dB) −0.5 −0.36 −0.36 −0.32

ISO (dB) −11 −5 −30 −13

switches, in conjunction with inductors in various configurations. This topology has shown the best performance, as previously described [11]. It is important to select a switch that presents a low on-resistance and low off-capacitances to maximize the performance of the final network. In the next subsections, we will examine the behavior of grounded switches and their power handling capabilities in order to select the most suitable switching topology for the application. 3.1. Source-grounded switch Figure 6 shows the source-grounded switch configuration. Table 2 shows the input impedances and the capacitances of the switches in their off-states. The table also provides the number of fingers of the transistors used. The parasitic

Zin (OFF) 2.7–j∗ 333 0.95–j∗ 138 880–j∗ 1160 336–j∗ 16

Real (Zin) 2.7 0.95 880 336

Cin (OFF) 0.25 pF 0.6 pF 72 fF 5 pF

Table 3: Summary of the switches maximum incident power handling performances.

−25

−3 −3.5

Table 2: Off-state input impedances of the switches when sources are grounded.

STS (nf = 36) TG (nf = 36) TG Res (nf = 36) LC resonance (nf = 61)

50 Ω ON state OFF state 25 dBm 22.5 dBm 26.5 dBm 2 dBm 26.5 dBm 0 dBm

Grounded source ON state OFF state 19.5 dBm 19.5 dBm 21 dBm 0 dBm 22 dBm 0 dBm

24.5 dBm 23.5 dBm

19 dBm

22 dBm

element that most significantly affects the operation of a bank of parallel switched capacitors is the parasitic off-state capacitance of the switch, which reduces its isolation. It can be seen that the STS and the resonant TG provide the lowest off-state capacitances. The STS has a lower parasitic resistance, whereas the resonant TG presents a higher value. 3.2.

Switch reliability: power handling

Reliability of the switch needs to be examined in the presence of a large RF input signal in combination with the output mismatch. Under these conditions, it is important to make sure that the switch is working below the maximum acceptable voltage drop across the gate oxide, which is 3.3 V in the process studied in this work. Table 3 summarizes the maximum incident power handling capability of the different switches either terminated in 50 Ω or grounded in ON and OFF states. The switch 1 dB compression point was also examined. Here, a major difference appears between bulk and SOS transistor technology. In a bulk MOSFET process, a switch starts compressing when an applied RF input signal is large enough to make the source/drain-to-body junctions forward biased in some portion of a cycle. A second mechanism occurs when the source is grounded and the switch is OFF. The drain voltage capacitively couples into the gate causing VGS to momentarily exceed the threshold voltage. This will result in channel conduction for a portion of the drain cycle. The first phenomenon does not exist in SOS technology because the bulk is isolated. It is only the second phenomenon that may

4

EURASIP Journal on Wireless Communications and Networking

take place when the switch is OFF. This has indeed been observed in simulations with the STS switch, which only compresses in its OFF state showing a P1 dB of +15 dBm in 50 Ω and ground terminations. From the above results, we can deduce that the STS presents the best tradeoff between IL and ISO for 50 Ω and grounded source configurations, while providing fairly good power handling. The STS and LC-resonance configurations have comparable power handling performance. However, the STS uses less elements and is less sensitive to frequency variations. As a result, the STS is selected as the switch in the matching networks described in the next sections.

2 1p

0.5 p

(a) 1

2 1.5 p

1.5 p

(50 Ω)

(50 Ω) 0.9 p

0.9 p

(b)

We first examine capacitor banks, which will form a major part of a complete matching network. A bank of four parallel capacitors connected to ground through four different sets of switches, all switched OFF, was simulated as shown in Figure 7(a). When the switches are turned off, the insertion loss (S21) between ports 1 and 2 should be very low. Figure 7(b) is another topology that loads the through line with only two capacitive branches, instead of four, as in Figure 7(a). This new topology provides the same selection of capacitance values as does the circuit of Figure 7(a). Figure 7(c) shows the simulated insertion loss of the two circuits with the dimensions given in Table 2. Figure 7(c) shows that the topology that presents the least effect on the thru line is that of Figure 7(b). This is an expected result since it loads the line with less elements than does the first topology. The TG switch was not included in the simulation because of its bad isolation. Now that the behavior of the individual switched capacitor banks has been examined, we consider a complete matching network. The simplest type of reactive matching network is the L-section [15]. The L-section allows two degrees of freedom among three specifications: centre frequency, impedance transformation (load/source impedances), and network Q (or bandwidth). Once impedance transformation and center frequency are specified, Q (or bandwidth) is automatically determined. Π (Pi) and T-match networks present more flexibility whereby one can independently specify center frequency, Q, and the impedance transformation ratio [16]. A Π-match can be considered as a cascade of two Lsections, and they lead to the same matching properties [17– 20]. The next subsections will focus on the design of ideal and real Π-matching networks to match loads having high VSWR. 4.1. Ideal Π-matching network Figure 8(a) shows the target impedance locations to be matched by the matching network. These impedances ZL are located on the circle which represents a VSWR of 5.6, and are defined as 1 + |ρ|e jφ , 1 − |ρ|e jφ

1p

(50 Ω)

MATCHING NETWORKS

ZL = 50 ·

0.5 p

(50 Ω)

(1)

0 −0.05 −0.1 −0.15

S21 (dB)

4.

1

−0.2 −0.25 −0.3 −0.35 −0.4 −0.45 −0.5

1.5

1.55 1.6

1.65 1.7

1.75 1.8

1.85 1.9

1.95 2

Frequency (GHz) Ideal (Figures 7(a) + 7(b)) New topology (STS, Figure 7(b))

STS (Figure 7(a)) TG Res (Figure 7(a))

(c)

Figure 7: (a) A bank of 4 parallel capacitors, (b) new topology, and (c) simulation results.

where |ρ| is the magnitude of the reflection coefficient, and φ is its angle (in rad or its equivalent in degrees −180 < φ < 180). VSWR of 5.6 is equivalent to a reflection coefficient |ρ| of 0.7 (S11 = S21 = −3 dB), and it encompasses a wide range of mismatched loads in a practical circuit. The Π-matching network topology is shown in Figure 8(b). It uses one fixed inductor of 3.2 nH, and two banks of four switched capacitors. To begin the discussion, all components are assumed to be ideal, and the switches are controlled independently. The elements of each capacitor bank are arranged in a binary array, and the discrete capacitive values of each capacitor bank may be expressed as 

CL,R = a1 20 + a2 21 + a3 22 + a4 23 )Cmin ,

(2)

where CL and CR are left- and right-hand side capacitor bank values, respectively, and Cmin is the minimum value of each capacitor bank. The coefficients a1 to a4 are either 0 when a switch is OFF, or 1 when a switch is ON. The maximum and

Ahmad Chamseddine et al.

5 0

VSWR = 5.6 ρ

QL = 20

−1

S21 (dB)

ϕ

S(1, 1)

Ideal inductor

−0.5

−1.5 −2

QL = 10

−2.5 −3

QL = 5

No matching network

−3.5 −4

φ(0 to 360)

0

50

100

(a) L

(1) C1 C2 C3 C4

S21 initial S21 ideal S21 reallnd Q5

(2) C1 C2 C3 C4

Load (φ)

300

350

S21 reallnd Q10 S21 reallnd Q20

Figure 9: Comparison of insertion losses obtained with ideal and real inductors with different Q values. The switches are ideal in all cases.

CR

CL

150 200 250 Load angle (degrees)

(b) 0 −0.5

VSWR circle of 5.6, separated evenly by π/9 rad (phi = 20 degrees). This result shows the best matching that can be obtained with this 1-Π circuit. The effect of the use of real components on this result will be highlighted in the next subsections.

S21 (dB)

−1 −1.5 −2

4.2.

−2.5

Real Π-matching network

This section shows how the matching network performs when realistic rather than ideal inductors and switches are used.

−3 −3.5

0

50

100

150

200

250

300

350

Load angle (degrees)

4.2.1. Real inductor and ideal switches

Matched ideal No matching network (c)

Figure 8: (a) Circle of load impedances of VSWR of 5.6; (b) ideal Πmatching network; and (c) the insertion losses obtained before and after matching of loads located on the circle circumference (S11 = S21 = −3 dB).

minimum capacitance values of each bank can be related as CLmax,Rmax = 2n − 1 = 15, Cmin

First, the effect of a real inductor will be investigated. Its value used in this Π-match is 3.2 nH at 1.9 GHz operation. Replacing the ideal inductor with realistic inductors with Q = 5, 10, and 20, respectively, leads to the result displayed in Figure 9. Note that Q of 20 is close to the value achievable in the chosen SOS process. The capacitors used here are MIMCAPS whose quality factor is higher than 100, however, the switches are still ideal. It can be seen that despite the use of a real inductor, the matching does not deteriorate considerably, and the result remains acceptable provided the inductor is not highly lossy.

(3)

where n is the number of switched capacitors of each bank. We choose a realistic value for Cmin = 0.5 pF (or C1). Thus, C2 = 1 pF, C3 = 2 pF, and C4 = 4 pF. Figure 8(c) shows the simulated insertion losses obtained with and without matching with the ideal Π-matching network. The simulated load impedances are located on the

4.2.2. Ideal inductor and real switches The matching behavior was then investigated using real switches. The inductor is ideal in order to only assess the effect of the switches. The final result is shown in Figure 10. Again, the TG switch was not simulated in this case because of its bad isolation.

6

EURASIP Journal on Wireless Communications and Networking L1 (1) C1 C2 C1 C2 C3 C4

0 −1

L2

(2) C1 C2 C3 C4

S21 (dB)

−2

(a)

−3 −4

0

−5

−0.5

−6

−8

0

50

100

150 200 250 Load angle (degrees)

STS TG Res

300

350

S21 (dB)

−1

−7

−1.5 −2 −2.5

No matching network Resonance LC

−3 −3.5

Figure 10: Comparison of insertion losses obtained with different real switches and ideal inductor.

0

50

100

150 200 250 Load angle (degrees)

300

350

Matched ideal No matching network

It is clear that the resonance-LC switch adds huge parasitic capacitances (as shown in Table 2) and thus cannot be used. The resonant TG switch shows good performance, but its low-power capability keeps it from being used for high-power signals. On the other hand, the single-transistor switch (STS) has a good matching potential as well as a good power-handling capability as shown previously. Therefore, the STS is selected for the matching network. The combined effects of nonideal switches and inductors will be discussed in the next sections. 5.

(b)

Figure 11: (a) Ideal 2-Π matching network and (b) the insertion losses obtained before and after matching a load with a VSWR of 5.6 (S11 = S21 = −3 dB).

obtained with a 2-Π matching network. The effect of the use of real components on the circuit will be pointed out in the next subsections.

2-Π MATCHING NETWORK

It is apparent from the previous section that a 1-Π network does not significantly improve the match for some loads. Cascading two 1-Π matching networks may provide the required latitude in circuit parameters to acceptably match a wider range of impedances. The next subsections will introduce a 2-Π matching network with ideal as well as realistic components. 5.1. Ideal 2-Π matching network Figure 11(a) shows a 2-Π matching network, which uses 2 inductors and 3 banks of switched capacitors. In this example, all components are assumed to be ideal, and the 10 switches are controlled independently. The inductors used are L1 = 4.2 nH and L2 = 3.2 nH. This network uses the same capacitor bank topology used in the previous case. The capacitor values are C1 = 0.5 pF, C2 = 1 pF, C3 = 2 pF, and C4 = 4 pF. Figure 11(b) shows the simulated insertion losses obtained with and without matching with the ideal 2-Π matching network. Again, the load impedances are located on the VSWR circle of 5.6, separated evenly by π/9 rad (phi = 20 degrees). This result shows that excellent matching can be

5.2.

Real 2-Π matching network

Figure 12 shows the insertion losses obtained with the 2-Π matching network using (1) real inductors (Q = 20) and ideal switches, (2) real switches and ideal inductors, and (3) real inductors and switches. The capacitors are MIMCAPS, and the transistor switches are controlled independently by digital signals of amplitudes of −1 V (OFF state) and +3 V (ON state). Drains and sources of the switches are biased by 0 V through 10 kΩ resistors (not shown in the figure). It can be seen from the figure that the effect of the switches is greater than that of the inductors. Furthermore, it is observed that both switch and inductor losses lead to significantly reduced matching performance with capacitive loads. Hence, it is expected that introduction of a phase shifter in front of the matching circuits can improve overall system performance. 5.3.

2-Π matching network with phase shifter

A tunable phase shifter was then designed to shift the capacitive load phases for a maximum phase shift of 100 degrees. The phase shifter shown in Figure 13(a) [21, 22] presents a maximum phase shift of 80 degrees when its input and

Ahmad Chamseddine et al.

7

0 −0.5 −1

S21 (dB)

−1.5 −2 −2.5 −3 −3.5 −4 −4.5

0

50

100

150 200 250 Load angle (degrees)

Real inductor Q = 20 Real switch

300

350

Real inductor & switch No matching network

Figure 12: Comparison of insertion losses obtained with real inductors (Q = 20), real switches, and real switches and inductors. Loads have VSWR = 5.6.

2-Π matching net

1.8 p

1.8 p

Phase shifter (a) 0 −0.5 −1 −1.5

S21 (dB)

5.4.

−2 −2.5 −3 −3.5 −4

5.5.

−4.5

0

50

100

150 200 250 Load angle (degrees)

300

New 2-Π match core

The new 2-Π matching network topology is depicted in Figure 14(a). It uses three capacitor banks and two inductors, the same as the circuit of Figure 11(a). The first capacitor bank provides two different capacitive loads of C1 = 1.5 pF (switch S1 is ON and S2 is OFF) and C1//C2 = 0.56 pF (S1 is OFF and S2 is ON). The middle capacitor bank provides four capacitive loads controlled in a similar way as the first bank, as does the third bank. Figure 14(b) shows the schematic of the real matching circuitry (bias network not shown). The component values are C1 = C3 = C7 = 1.5 pF; C2 = C4 = C8 = 0.9 pF; C5 = C9 = 1 pF; C6 = C10 = 20 pF (used as decoupling capacitors). The values of inductors L1 and L2 are 4.2 nH and 3.8 nH, respectively, with a Q of 20 for both. The STS characteristics are given in Table 2. The simulated insertion loss obtained with this topology is shown in Figure 14(c). This new topology is capable of providing a good matching for inductive loads, but unacceptable matching for capacitive loads. Using a variable phase shifter should address this shortcoming.

Load

3.2 n

output ports are terminated in 50 Ω. However, this phase shift becomes as high as 120 degrees when its output port is mismatched. While one can argue that this phase shifter is nothing but another Π-matching network, the circuit has been designed separately to provide the required phase shift. Figure 13(b) shows the insertion loss of the 2-Π matching network with and without the phase shifter. The matching network and phase shifter use real components with all inductors assumed to have Q of 20. It can be seen that the mismatch in the capacitive zone has been reduced and all capacitive loads, but one, have their matching conditions improved. Note that the capacitor banks used so far are the ones of the topology of Figure 7(a). However, it has been demonstrated that switched capacitors of Figure 7(b) have less parasitic effects on the signal carried on the through line. Consequently, this new topology has been examined on the 2-Π matching network.

350

No phase shifter With phase shifter No matching network (b)

Figure 13: (a) 2-Π matching network followed by a tunable phase shifter; (b) insertion losses of the 2-Π matching network with and without phase shifter. All components are realistic.

New 2-Π match core with phase shifter

The new 2-Π matching network was then augmented with a tunable phase shifter, as shown in Figure 15(a). The characteristics of this phase shifter are similar to the ones in the previous section. It provides a maximum phase shift of 80 degrees when terminated with 50 Ω. However, this phase shift increases when one of its port impedances is different from 50 Ω. This phase shifter uses two capacitor banks controlled by single-transistor switches (STS). The inductor Q is also 20. The resulting insertion loss of the whole circuit is shown in Figure 15(b).

8

EURASIP Journal on Wireless Communications and Networking L1

(1)

L2

C1 S1

S2

C2

C3 S3

S4

(2) Load

C5

S5 C4

S6

C6

C7 S7

S8

S9 C8

3.2 n

Matching net

C9

1.8 p

S10 C10

S11

S12 S13 1p

(a)

Load 1.8 p S14 1p

Phase shifter L1 S1

C1 S3

S2

C2

L2 C3 S4 S5

C5 S6

C4

C6

S7

Load C7 S8 S9

(a)

C9 S10

C8

0

C10

−0.5

(b)

−1

S21 (dB)

0 −0.5 −1

S21 (dB)

−1.5

−1.5 −2 −2.5 −3

−2

−3.5

−2.5

−4

−3 −3.5 −4

50

100

150 200 250 Load angle (degrees)

300

350

Matched No matching network (c)

Figure 14: (a) and (b) 2-Π matching network using the new capacitor bank topology; (c) simulated insertion loss. All components are real.

5.6. Optimization of the new 2-Π matching network The matching network of Figure 15(a) was further optimized in order to improve its matching capability for capacitive loads. This has been done through the following procedure: given that each load impedance is matched by finding the right combination of switch states, there are then X switches ON and (N–X) switches OFF for each load where N is the number of switches of the network. In the example being discussed, N = 14 with the phase shifter included (Figures 13(a) and 14(a)). Then, those (N–X) switches (which are OFF) have been compared for each load and it has been observed that switches 5, 7, and 9 of Figure 14(a) are ON for only one time for all load impedances. Consequently, removing those three switches, as shown in Figure 16(a), and comparing the new insertion loss with the one of Figure 15(a), we obtain the result displayed in Figure 16(b). The final result shows improvement in the general behavior of the matching network with highly capacitive loads.

50

100

150 200 250 Load angle (degrees)

300

350

No phase shifter With phase shifter No matching network

−4.5

0

0

(b)

Figure 15: (a) The new 2-Π matching network followed by a tunable phase shifter; (b) insertion losses of the 2-Π matching network with and without phase shifter.

5.7.

Matching different loads

The optimized new matching network has been examined to match heavily mismatched loads. The result is shown in Figure 17 for loads having VSWR of 9 (|ρ| = 0.8; S21 = −4.4 dB), and 12.3 (|ρ| = 0.85; S21 = −5.5 dB). The result shows improvement in their matching behavior, even though capacitive loads are not as well matched as inductive loads. It should be noted that when the network is actually matched, that is, the load is 50 Ω, the network’s simulated insertion loss is 1 dB. This mismatch is due to the presence of the three inductors of the network between the generator and the 50 Ω load, and switches S6 and S8 are ON to compensate for their effects. Consequently, the system VSWRs will always be greater than or equal to 2.5. However, at the same time, large improvements in the match are seen for significantly mismatched networks, improving the overall power savings. 6.

POWER CAPABILITY OF THE OPTIMIZED NETWORK

Figure 18 shows the simulation results of the insertion loss and power capability of the optimized new 2-Π matching

Ahmad Chamseddine et al.

9 L2

S1

S2

C2

C3 S3

S4 C4

S6

C5

C7

C9

C6

S8 C8

S10 C10

0

Load

−1 −2

S21 (dB)

C1

Phase shifter

(a) 0

−3

Matched |0.85|

−4

−0.5

No matching network ρ = |0.8|

−5

−1

S21 (dB)

Matched |0.8|

−1.5

−6

0

−2

50

−2.5

100 150 200 250 Load angle (degrees)

S21 NoMatch |ρ| = 0.8 S21 Match |ρ| = 0.8

−3 −3.5 −4

0

50

100

150 200 250 Load angle (degrees)

No phase shifter With phase shifter

300

350

Optimized No matching network

network shown in Figure 16(a) at 1.9 GHz for load impedances with VSWR of 5.6, separated evenly by π/9 rad (phi = 20 degrees). The result shows 1 dB compression points that vary with the load values. The power handling capability is quite good over the entire range of load impedances. CONCLUSION

The design and optimization of matching networks in an SOS CMOS process have been presented in this paper. Different switching components have been described. The ability of the networks to match loads depends strongly on the Q factor of the inductors used as well as IL and ISO of the switches. The selected single-transistor switch (STS) topology is capable of handling signal power as high as +20 dBm. The goal of matching highly mismatched loads with VSWR > 5.6 required the cascade of two Π matching networks with a phase shifter. The final network configuration was capable of matching a wide range of inductive and capacitive loads. ACKNOWLEDGMENT Financial and infrastructure support provided by iCORE, NSERC, TRLabs, the University of Calgary, and CMC Microsystems is gratefully acknowledged.

S21 (dB)

Figure 16: (a) The optimized new 2-Π matching network followed by a tunable phase shifter; (b) insertion losses of the 2-Π matching network with and without phase shifter.

300

350

S21 NoMatch |ρ| = 0.85 S21 Match |ρ| = 0.85

Figure 17: Insertion loss obtained with the optimized new 2-Π matching network for load having reflection coefficients of 0.8 and 0.85.

(b)

7.

No matching network ρ = |0.85|

0

27

−0.5

24

−1

21 18

−1.5

15

−2

12

−2.5

9

−3

6

−3.5

3

−4

0

50

100

150

200

250

300

P1 dB (dBm)

L1

0 350

Load angle (degrees) P1 dB (dBm) S21 matched S21 no matching network

Figure 18: Insertion loss and the 1 dB compression points obtained with the optimized new 2-Π matching network for loads having a reflection coefficient of 0.7.

REFERENCES [1] K. Karimullah, D. Nyquist, and K. Chen, “Interaction of thinwire antennas with conducting, polarizable bodies—theory and experiment,” in Proceedings of IEEE International Symposium on Antennas and Propagation Society (APS ’78), vol. 16, pp. 219–222, College Park, Md, USA, May 1978. [2] O. Norklit, P. D. Teal, and R. G. Vaughan, “Measurement and evaluation of multi-antenna handsets in indoor mobile communication,” IEEE Transactions on Antennas and Propagation, vol. 49, no. 3, pp. 429–437, 2001. [3] M. A. Jensen and Y. Rahmat-Samii, “Performance analysis of antennas for hand-held transceivers using FDTD,” IEEE Transactions on Antennas and Propagation, vol. 42, no. 8, pp. 1106– 1113, 1994.

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EURASIP Journal on Wireless Communications and Networking

[4] J. Toftgard, S. N. Hornsleth, and J. B. Andersen, “Effects on portable antennas of the presence of a person,” IEEE Transactions on Antennas and Propagation, vol. 41, no. 6, pp. 739–746, 1993. [5] J. de Mingo, A. Valdovinos, A. Crespo, D. Navarro, and P. Garcia, “An RF electronically controlled impedance tuning network design and its application to an antenna input impedance automatic matching system,” IEEE Transactions on Microwave Theory and Techniques, vol. 52, no. 2, pp. 489–497, 2004. [6] L.-Y. Vicki Chen, R. Forse, D. Chase, and R. A. York, “Analog tunable matching network using integrated thin-film BST capacitors,” in IEEE MTT-S International Microwave Symposium Digest, vol. 1, pp. 261–264, Fort Worth, Tex, USA, June 2004. [7] J. R. Moritz and Y. Sun, “Frequency agile antenna tuning and matching,” in Proceedings of 8th International Conference on HF Radio Systems and Techniques (IEE Conf. Publ. No. 474), pp. 169–174, Guildford, UK, July 2000. [8] D. M. W. Leenaerts, “Low power RF IC design for wireless communication,” in Proceedings of International Symposium on Low Power Electronics and Design, pp. 428–433, Seoul, Korea, August 2003. [9] A. A. Abidi, “Low-power radio-frequency IC’s for portable communications,” Proceedings of the IEEE, vol. 83, no. 4, pp. 544–569, 1995. [10] T. Vaha-Heikkila, J. Varis, J. Tuovinen, and G. M. Rebeiz, “A 20-50 GHz RF MEMS single-stub impedance tuner,” IEEE Microwave and Wireless Components Letters, vol. 15, no. 4, pp. 205–207, 2005. [11] T. Vaha-Heikkila, J. Varis, J. Tuovinen, and G. M. Rebeiz, “A reconfigurable 6-20 GHz RF MEMS impedance tuner,” in IEEE MTT-S International Microwave Symposium Digest, vol. 2, pp. 729–732, Fort Worth, Tex, USA, June 2004. [12] P. Sjoblom and H. Sjoland, “An adaptive impedance tuning CMOS circuit for ISM 2.4-GHz band,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 52, no. 6, pp. 1115– 1124, 2005. [13] Peregrine website: http://www.psemi.com. [14] T. Tokumitsu, I. Toyoda, and M. Aikawa, “A low-voltage, highpower T/R-switch MMIC using LC resonators,” IEEE Transactions on Microwave Theory and Techniques, vol. 43, no. 5, pp. 997–1003, 1995. [15] C. Bowick, RF Circuit Design, Howard W. Sams, London, UK, 1985. [16] T. H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits, Cambridge University Press, Cambridge, UK, 2nd edition, 2004. [17] Y. Sun and J. K. Fidler, “Design method for impedance matching networks,” IEE Proceedings - Circuits, Devices and Systems, vol. 143, no. 4, pp. 186–194, 1996. [18] Y. Sun and J. K. Fidler, “Component value ranges of tunable impedance matching networks in RF communications systems,” in Proceedings of 7th International Conference on HF Radio Systems and Techniques (Conf. Publ. No. 441), pp. 185–189, Nottingham, UK, July 1997. [19] J. K. Fidler and Y. Sun, “Computer-aided determination of impedance matching domain,” in IEE 12th Saraga Colloquium on Digital and Analogue Filters and Filtering Systems, pp. 1/1– 1/6, London, UK, November 1992. [20] M. Thompson and J. K. Fidler, “Determination of the impedance matching domain of impedance matching networks,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 51, no. 10, pp. 2098–2106, 2004.

[21] F. Ellinger, H. Jackel, and W. Bachtold, “Varactor-loaded transmission-line phase shifter at C-band using lumped elements,” IEEE Transactions on Microwave Theory and Techniques, vol. 51, no. 4, pp. 1135–1140, 2003. [22] F. Ellinger, R. Vogt, and W. Bachtold, “Ultra compact, low loss, varactor tuned phase shifter MMIC at C-band,” IEEE Microwave and Wireless Components Letters, vol. 11, no. 3, pp. 104–105, 2001. Ahmad Chamseddine received the B.S. degree in electrical engineering from the Lebanese University, Beirut, in 1996, and the M.S. and Ph.D. degrees in electrical engineering from the Institut d’Electronique, de Micro´electronique et de Nanotechnologie (IEMN), University of Science and Technology of Lille, France, in 1997 and 2001, respectively. From 2002 to 2003, he was with AMI Semiconductor, Inc., Belgium, as a Mixed-Signal Design Engineer. Currently, he is with the Department of Electrical and Computer Engineering at the University of Calgary. His current research interests include RF circuit design for wireless applications. James W. Haslett received the B.S. degree in electrical engineering from the University of Saskatchewan in 1966, and the M.S. and Ph.D. degrees in electrical engineering from the University of Calgary in 1968 and 1970, respectively. He currently holds the TRLabs/iCORE/NSERC Senior Industrial Research Chair in Broadband Wireless RFIC Design Group in the Department of Electrical and Computer Engineering at the University of Calgary. He was the Head of the Department from 1986 to 1997, and has been the President of his own engineering consulting firm since 1981, consulting to oilfield instrumentation firms primarily on high temperature and downhole instrumentation. He was also a Member of several national and international science teams designing satellite instrumentation in the late 1970s and 1980s. He has authored and coauthored 140 publications in the field of analog microelectronics, more than 40 technical reports to industry, and holds 11 patents. He has an extensive service history and has served as a Reviewer and Technical Program Committee Member for many international journals and conferences. He is currently a Member of the Editorial Review Committee of the IEEE Transactions on Instrumentation and Measurement, and was an Associate Editor of the Canadian Journal of Electrical & Computer Engineering from 2001 to 2004. He is a Fellow of the IEEE, a Fellow of the Engineering Institute of Canada, and a Fellow of the Canadian Academy of Engineering. Michal Okoniewski is a Professor and Canada Research Chair at the Department of Electrical and Computer Engineering, University of Calgary. He is also affiliated to TRLabs, Calgary. He received the M.S. and Ph.D. degrees from the Gdansk University of Technology, and had his postdoctoral training at the University of Victoria, BC. He is heading the Applied Electromagnetics Group at the University of Calgary.

Ahmad Chamseddine et al. He is interested in many aspects of applied electromagnetics, ranging from computational electrodynamics to reflectarrays and self-configuring antennas, RF MEMS and micromachined devices, as well as reconfigurable computational hardware for electromagnetics applications. He is also actively involved in bioelectromagnetics, where he works on tissue spectroscopy and cancer detection. He published over 50 journal and over 150 conference papers. In 2004, he cofunded Acceleware Inc., a publicly traded company developing acceleration hardware for simulation software.

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Hindawi Publishing Corporation EURASIP Journal on Wireless Communications and Networking Volume 2006, Article ID 16518, Pages 1–9 DOI 10.1155/WCN/2006/16518

Using MEMS Capacitive Switches in Tunable RF Amplifiers John Danson, Calvin Plett, and Niall Tait Department of Electronics, Carleton University Ottawa, ON, Canada K1S 5B6 Received 15 October 2005; Revised 27 February 2006; Accepted 14 March 2006 A MEMS capacitive switch suitable for use in tunable RF amplifiers is described. A MEMS switch is designed, fabricated, and characterized with physical and RF measurements for inclusion in simulations. Using the MEMS switch models, a dual-band lownoise amplifier (LNA) operating at 2.4 GHz and 5.2 GHz, and a tunable power amplifier (PA) at 5.2 GHz are simulated in 0.18 μm CMOS. MEMS switches allow the LNA to operate with 11 dB of isolation between the two bands while maintaining 11.6 dB of gain and sub-4.5 dB noise figure. MEMS switches are used to implement a variable matching network that allows the PA to realize up to 37% PAE improvement at low input powers. Copyright © 2006 John Danson et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

1.

INTRODUCTION

The current push towards smaller devices in wireless technologies is driving the development of more highly integrated, low-power radios. The desire for interoperability between different networks requires that multiple-standard radios be implemented in a single product. There are obvious advantages to having a product that operates in both bands. However, this presents a challenge to designers seeking to reduce chip area. Many radios use separate receive and transmit chains, duplicating circuitry for each band of operation. Unfortunately, there are few alternatives using traditional circuit techniques. Micro-electrical-mechanical systems (MEMS) offer the circuit designer new possibilities for including high-performance tuning and switching elements in their designs. MEMS are mechanical structures built directly on a substrate using processes similar to those used in IC fabrication. RF MEMS devices find applications in a variety of areas, including filter tuning, phase shifters, reconfigurable matching networks, receive/transmit switches, and duplexers. Devices range from tunable capacitors and integrated inductors to mechanical and acoustical resonators [1]. One type of MEMS device is a capacitive switch. This paper outlines the operation of the switch and describes a design procedure for the switch, with emphasis on integrating the device into a standard IC design from a circuit designer’s point of view. A MEMS switch is designed and characterized for use in simulations of a dual-band low-noise amplifier (LNA) and a tunable power amplifier.

2. 2.1.

MEMS CAPACITIVE SWITCHES Device overview

There are many different types of MEMS switches in both series and shunt configurations [2]. These switches can be DC contact switches, where there is direct metal contact between the two plates or capacitive switches as discussed below. MEMS capacitive switches are fabricated with a metaldielectric-air gap-metal cross section as shown in Figure 1. The upper metal plate (also known as a bridge) can be actuated from an up state to a down state. In the up state, the plate is relaxed and the air gap is present between the dielectric and the upper plate. In the down state, an electrostatic force is applied by an external control voltage to the upper plate causing it to collapse and eliminating the air gap between the dielectric and upper plate. Capacitance ratios between the two states of 600 : 1 are attainable [3] although 30–40 : 1 is more typical. Due to the mechanical nature of the switches, the frequency response of the bridge follows a lowpass characteristic with a mechanical resonance in the range of 10–200 kHz [4]. Although the switching speed of MEMS switches is relatively low compared with active devices, they offer the advantage of very low static power dissipation. MEMS switches still face challenges in the areas of reliability and packaging to be competitive, however their wide tuning range allows for new circuit topologies. The actuation voltage of a MEMS switch is determined by equating the electrostatic force of the applied voltage to the mechanical restoring force of the beam. This is dependent

2

EURASIP Journal on Wireless Communications and Networking t

Upper plate

tox

Air gap

Substrate

l 2

wc

g0 l 2

2.2.

Dielectric

Given the main parameters of interest to the circuit designer, a typical design procedure can be proposed for a MEMS capacitive switch. The primary goal of the design procedure is to provide the circuit designer with a simple set of parameters, while avoiding the level of detail that is generally the domain of the device engineer. Along with this simple set of parameters, an accurate RF model of the device, such as those in [6, 7], is clearly required.

Lower plate

Figure 1: MEMS capacitive switch cross section.

on the spring constant, k, for a fixed-fixed bridge as shown in Figure 1 k=

32Et 3 w , l3

(1)

where E is Young’s modulus, t is the bridge thickness, w is the bridge width, and l is the bridge length over which the electrostatic force is applied. In the case of the switch shown in Figure 1, the electrostatic force is applied over the two ground planes on either side of the center conductor, denoted by l/2. The actuation voltage is given by [4] 

Vsw =

 2k 2  g g0 − g , 0 A

(2)

(3)

Knowing the bridge height, and substituting for k and A, the pull-down voltage can be determined [4]: V p = Vsw|(2/3) g0

   256Eg03 t 3 = . 270 l4

2.2.1. Identify type of implementation Ideally, the devices would be postprocessed on the die containing the active devices. This may not be practical due to die handling limitations, particularly for prototype designs. For proof-of-concept designs, the MEMS switches may be located on a separate die, then wire bonded to the active device die. However, the effect of the bond wire inductance must be included and it may constrain circuit topologies. 2.2.2. Determine size ratios

where g0 is the bridge height in the up state (at 0 V bias), g is the current beam height, and A = wl is the area of the bridge that overlaps the lower-ground plane. Equation (2) shows that there are two possible voltages for every bridge height. This is due to the instability that occurs when the electrostatic force exceeds the restoring force. At this point, the bridge pulls down. This instability occurs at a bridge height of [4] 2 g = g0 . 3

Switch design procedure

Size ratios between the two capacitances are determined in conjunction with the circuit design. Although the typical capacitance ratio for a MEMS switch is in the 30–40 : 1 range, this may be too high. In cases where a smaller ratio is desired, the switch dimensions can be adjusted or a fixed capacitance can be added in parallel with the switch. 2.2.3. Size capacitor and allocate chip area The circuit designer must determine how much chip area can be devoted to the switch. Given the maximum pull-down voltage that can be implemented by the control circuitry, the maximum capacitance density can be found from the minimum dielectric thickness that will not break down. Along with the chip area, the maximum capacitance density limits the size of capacitor that can be realized.

(4)

The pull-down voltage must not exceed the breakdown voltage of the dielectric layer, therefore limiting the thickness and type of the dielectric material. The pull-down voltage is also important to circuit designers as it determines what type of actuation circuitry is required. The dielectric thickness previously set to avoid breakdown imposes a maximum capacitance density. This allows the circuit designer to determine the maximum practical capacitance given the standard die area trade-offs of large on-chip passives such as MIM caps and spiral inductors. A further consideration is the potential for nonlinearity in the switch. Two RF tones separated by a frequency below the resonant frequency of the switch create an envelope effect that acts to modulate the air gap in the switch, hence changing the capacitance. Careful design to increase the bridge spring constant can mitigate this problem. It should be noted that MEMS switches are still more linear than diode or FETbased devices [5].

2.2.4. Adjust switch for linearity Finally, the bridge width must be adjusted for adequate linearity. By substituting the spring constant, shown in (1), into the expression for actuation voltage, it can be seen that while spring constant is proportional to bridge width, actuation voltage is independent of bridge width. Since the capacitance between the bridge and the signal conductor dominates the device capacitance, the conductor width can be adjusted to compensate for any change in capacitance caused by changing the bridge width. A spring constant k > 10 N/m was determined in [5] to be practical for most designs, however it may be higher than necessary for a given circuit. A more complete device model for the MEMS switch that includes dynamic response would allow the circuit designer to adjust the bridge width as necessary. The dynamic model would incorporate the mechanical force balance equations, the high-frequency electrical response, and the low-frequency interaction between the two.

John Danson et al.

3 Table 1: Dimensions of the MEMS switch.

Actuation contact

Parameter Ground

Bridge thickness, t (μm)

Signal Ground

Dimension

Bridge

1

Bridge width, w (μm) Bridge length where force is applied, l (μm)

310 370

Bridge height at 0 V bias, g0 (μm) Dielectric thickness, tox (μm) Signal conductor width, wc (μm)

1.7 100 100

Figure 2: Die photo of a MEMS capacitive switch. ×10−5

2.3. Experimental results Z (m)

1

Using the design procedure above, a set of MEMS capacitive switches has been designed for use in the dual-band LNA described in Section 3. A die photo is shown in Figure 2. As shown in the die photo, the switches are designed in a coplanar waveguide configuration to facilitate testing and integration with the active circuitry. The switch geometry is based on a common fixed-fixed bridge as reported in the literature. The upper plate, or bridge, at center is controlled through the actuation voltage contact at the top of the figure. Signal and ground lines form the lower plate. The bridge is perforated with a grid of holes to allow the sacrificial spacer material to be etched away. The MEMS switches are based on a process developed at Carleton University and built in Carleton’s Microelectronics Fabrication Lab [8]. The switches use aluminum metallization and an organic sacrificial spacer (Shipley S1811 photoresist) in a 4-mask process. Both the metallization and dielectric deposition are performed at low temperature, and the sacrificial spacer does not require an aggressive release etch (solvent or oxygen plasma only). Hence, the MEMS process is adaptable to postprocessing on most substrates, so the switches would ideally be postprocessed directly on the RF wafer. Due to die handling constraints, the MEMS switches for the circuits described in Section 3 are designed to be built on a separate die, then wire-bonded to the active circuitry using chip-on-board. Although one of the motivations for this research is to reduce chip area, building the switches on a separate die actually increases area because of the extra bondpads required to connect the dice. Dimensions of the MEMS switch are listed in Table 1. The switches are examined under a WYCO MHT-III optical profiler to check for any anomalies from fabrication. A plot of a switch in the down state is shown in Figure 3. The small deformity along the center of the bridge indicates some residual stress from fabrication. The switches have a pull-down voltage of 3.8 V, which is higher than the 1.8 V CMOS supply voltage. A separate supply would be required to actuate these particular switches, however there are alternate design techniques that allow the pull-down voltage to be lowered. For the proof-of-concept designs presented in Section 3, this pull-down voltage was deemed to be acceptable.

0 −1

800 600

X (um)

400 200 0 1000 800

600

400

200

0

Y (um)

Figure 3: 3D surface plot of a MEMS switch in the down state.

The switches use silicon nitride (r = 7.5) for the dielectric layer. The physical dimensions were selected to provide a capacitance ratio of 8 : 1, however bond wire inductance reduced the effective capacitance ratio to 6 : 1. This is less than optimal for the LNA, but still produces acceptable inband gain. The bridge width meets the condition for linearity with a spring constant of 13.7 N/m. Capacitance measurements are shown in Figure 4. At the frequencies of interest for the LNA design, the switches have a Q of 25 at 2.4 GHz in the down state and a Q of 77 at 5.2 GHz in the up state. This was incorporated in two simple series R-L-C lumped element models (one at 2.4 GHz and the other at 5.2 GHz) fitted to the measurements for inclusion in the LNA simulations. 3.

APPLICATIONS

This section describes two circuits that use MEMS capacitive switches and are designed using the design procedure outlined above. The first is a dual-band LNA that operates in the 2.4 GHz and 5.2 GHz wireless LAN bands. The second is a tunable power amplifier at 5.2 GHz for improved efficiency at lower input power. 3.1.

Dual-band low-noise amplifier

A proposed dual-band LNA circuit is shown in Figure 5. The LNA is to operate at 2.4 GHz and 5.2 GHz and to be built in a 0.18 μm CMOS process using MEMS capacitive switches.

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EURASIP Journal on Wireless Communications and Networking Cup

Cdown 5 Capacitance (pF)

Capacitance (fF)

330 320 310 300 290

4 3 2 1

280 1

2

3

4

5

6

7

8

9

10

1

2

3

Frequency (GHz)

4

5

6

7

8

9

10

Frequency (GHz)

Measured Fitted model

Measured Fitted model

Figure 4: RF measurements and fitted data for a MEMS switch. VDD Ltank Out−

CMEMS

MEMS capacitive switches Out+

M2

Lg1

VCTRL

In + Lg2

M1

In−

Ls

Cg

Figure 5: Simplified LNA schematic (bond pads/wires, ESD, and biasing are not shown).

Tunable LNAs have some distinct advantages over their fixed counterparts. They offer the ability to change the operating frequency of the amplifier by adjusting matching and resonant tank circuits. There are different methods to tune LNAs, all of which have limitations. Multiple FETs can be used to select between fixed capacitors to increase or decrease the capacitance on a particular node. The disadvantage with this approach is that the FETs introduce noise into the circuit [9]. The added channel resistance also limits the range of capacitances that can be switched into the circuit. Varactors are a different method of tuning the circuit. The range of capacitance that can be achieved is limited to the tuning range of the varactor. These methods are better suited to narrowband tuning of an LNA as in [10]. For wider-band operation, a different approach is necessary. Several dual-band LNAs are presented in [11–13] that use a separate LNA circuit for each band. Various methods are used to select the desired band. Although this topology does simplify the task of input matching and the tuned load, it requires twice the number of components. Since onchip inductors consume large amounts of chip area, it is desirable to find new topologies that reduce the number of components. A concurrent dual-band LNA for operation at 2.45 GHz and 5.25 GHz is presented in [14]. This LNA uses dual-tuned circuits for the input match and load to achieve simultaneous operation at both frequencies. Since the LNA amplifies both bands concurrently, there is the potential for cross-band compression and intermodulation.

In the proposed design, a cascode topology is used to achieve the desired gain at both frequencies and for isolation between the input matching and the tuned tank. This is important since switching the tuned tank of a simple common source amplifier would present a significantly different impedance at the amplifier input. The differential design limits packaging effects from bond wire inductance. There are several different circuits that yield a good input match at both frequencies, some using MEMS switches and some using dual-tuned circuits. With the switches being fabricated on a separate die, many of the switched matching circuits are not practical. For this reason a dual-tuned circuit as in [14] is selected for the input matching. With lowquality factor on-chip inductors, the input matching network contributes to higher noise figure. Postprocessing the MEMS components offers the advantage that higher Q inductors, not available in the CMOS process, could be included. Inductive degeneration is used to improve linearity, lower noise figure, and boost the input impedance as discussed in [15, 16]. The width of the input transistor is increased to match a 50 Ω source impedance with the dual-tuned circuit. The cascoding device is made the same width as the input transistor to allow drain-source sharing, minimizing its noise contribution. The cross-band distortion problems are considerably reduced by using a tuned tank realized with an on-chip symmetrical inductor and MEMS switches. Since the LNA only amplifies one band at a time, there is greater isolation between the two bands.

20 10 0 −10 −20 −30 −40

5 0

11.7 dB

S11 (dB)

S21 (dB)

John Danson et al.

19.5 dB

1

1.5

2

2.5

3

3.5

4

4.5

5

5.5

−5 −10 −15 −20 −25 −30 −35

6

1

1.5

2

2.5

Frequency (GHz)

3

3.5

4

4.5

5

5.5

6

Frequency (GHz) 5.2 GHz 2.4 GHz

NF (dB)

5.2 GHz 2.4 GHz 35 30 25 20 15 10 5 0 1

1.5

2

2.5

3

3.5

4

4.5

5

5.5

6

Frequency (GHz) 5.2 GHz 2.4 GHz

Figure 6: Extracted simulations of the LNA showing gain and cross-band isolation, input return loss, and noise figure. Table 2: Performance comparison with other dual-band LNAS. Technology Operating bands (GHz) Gain, S21 (dB) Noise figure (dB) Input return loss, S11 ( dB) Input P1 dB compression (dBm) Cross-band isolation (dB) Input IP3 (dBm) Supply voltage (V) Power consumption (mW) Area (mm2 ) Notes

[14] 0.35 μm CMOS 2.45 5.25 14 15.5 2.3 4.5 −25 −15 −8.5 −1.5 1.5 0.0 5.6 2.5 10 0.64 Concurrent design, input matching off-chip

Due to parasitic capacitances in the layout from bondpads and interconnect, the circuit requires a switch capacitance of Cup = 200 fF at 5.2 GHz and Cdown = 1.7 pF at 2.4 GHz. This means for optimal performance the MEMS switch must have an up-down capacitance ratio of 8 : 1. At 6 : 1, as is the case with the measured switches, optimal gain in the 5.2 GHz band is shifted down in frequency to 4.7 GHz. In the case where the MEMS switches are postprocessed on the CMOS wafer, the bond pad parasitics would not be present and the capacitance change could be lower than the optimal 8 : 1 ratio. Extracted simulations of the LNA, shown in Figure 6, predict forward gain greater than 11.6 dB for both bands with

[17] 0.18 μm CMOS 2.4 5 11.6 10.8 2.3 2.9 −5.1 −26.3 −7.9 −7.1 12.5 17 No data 1 14.2 0.9 FET-switched inductor

[18] 0.18 μm CMOS 2.4 5.2 10.1 10.9 2.9 3.4 −10.1 −11 −7 −16 No data 4 −5 1.8 11.7 5.7 No data

This work 0.18 μm CMOS 2.4 5.2 12.2 11.6 4.5 4.2 −27.6 −8.5 −4.9 −7.6 11.7 19.5 3.1 3.9 1.8 16.7 1.58

FET-switched capacitor

MEMS capacitive switches

sub-4.5 dB noise figure. The forward gain plot in Figure 6 shows a minimum cross-band isolation of 11.7 dB for both bands. The measured model of the MEMS switch is included in these simulations, along with bond pads, bond wires, ESD structures, and capacitive parasitics from interconnect. Simulations show that the LNA is stable across frequency. This is achieved with a power consumption of 16.7 mW from a 1.8 V supply. The results are compared with other dual-band LNAs in Table 2. 3.2.

Tunable power amplifier

The output stage of a 20 dBm, 5.2 GHz class AB tunable power amplifier is to be designed in a 0.18 μm CMOS process

6

EURASIP Journal on Wireless Communications and Networking VDD RFC CDC

M2

Lg

Vin

Lmatch

CDC L1

C1

CMEMS1

CMEMS2

RL

M1 Cg

RFC

Lbond wire VGG

Figure 7: Class AB tunable PA. B3 Zo

B2

B1

YL = GL + jBL

Figure 8: Variable matching network represented by susceptances.

using MEMS capacitive switches with a goal of increasing efficiency over a range of power levels. The main goal of this PA is to increase efficiency at lower power levels where the output stage is typically inefficient. Other methods for increasing efficiency at low power include dynamically adjusting the power supply voltage [19, 20] or using parallel amplifiers (such as the Doherty configuration) [21]. This design is loosely based on a 500 MHz, 100 W PA in [22]. In that amplifier, PIN diodes are used as switches in an L matching network to adjust a capacitor bank. This design uses a similar approach, but tailored for MEMS capacitors. The proposed PA is shown in Figure 7. The input transistor, M1, is matched with a lowpass network formed by Lg and Cg to limit harmonic content. The source bond wire inductance is modeled with Lbondwire . This is actually formed of several bond wires in parallel to lower the inductance and to provide heat sinking to the die. DC blocking is provided by the bypass capacitors, CDC . A filter, formed by L1 and C1 , helps increase efficiency by shunting harmonic power at the drain to ground. The π network formed by CMEMS1 , CMEMS2 , and Lmatch is a variable matching network that adjusts the 50 Ω load, RL , to the optimal load impedance, Γopt , to increase efficiency at lower power. Since the variable matching network must match to two different impedances, equations are derived for a π network implemented with a fixed inductor and two variable capacitors, shown by susceptances B1 , B2 , and B3 in Figure 8. The equations to relate B1 , B2 , and B3 back to CMEMS1 , CMEMS2 , and Lmatch are as follows: Lmatch =

1 2π fhigh B3

 ≤

Zo Rsmall , 2π fhigh

CMEMS1 · 2π f = B1 = −BL − B3 ± GL B32 Zo − G2L , 1 CMEMS2 · 2π f = B2 = −B3 ± GL B32 Zo − G2L , Zo G L

(5)

where Rsmall is the smallest of the two load resistances, and fhigh is the highest frequency (in the case that the matching network is being used at two different frequencies). Zo is the load resistance, typically 50 Ω, and YL is the complex conjugate of Γopt . To design the amplifier, a series of load pull simulations are performed over increasing input powers. Due to amplifier nonlinearities, optimal output power cannot be obtained by matching to the conjugate of the small-signal output impedance. The load pull simulation sweeps all possible values of output impedance, then plots contours of constant power on the Smith chart. An example at 0 dBm is shown in Figure 9. As shown in Figure 10, at high input power levels (and hence higher output power), the optimal load impedance is mostly resistive with a small inductive component. As the input power drops, the optimal load becomes more inductive, acting to cancel the drain capacitance as would happen in the conjugate match of a small-signal amplifier. Based on the range of optimal loads, two impedances are chosen to be presented by the variable matching network. The variable matching network adjusts the load to be more inductive as the input power decreases by switching the MEMS capacitors. Although there are four possible impedances that can be presented by the switched network, only two are used as shown by the triangles in Figure 10. Simulations compare the performance of the class AB PA with a fixed and variable matching network. The Pout graph in Figure 11 shows minimal difference between the two networks. The design goal of 20 dBm output power is achieved at an input power of 12.5 dBm for a gain of 7.5 dB. The power added efficiency (PAE) graph shows the expected increase in efficiency. At Pin = 0 dBm, there is a 37% increase in PAE over the fixed match. Even at Pin = 10 dBm, there is still an 8% improvement. There is no

John Danson et al.

7 −0.2

−0.2

0.5

−0.1

−1

1.5

0.7

1.95

3

0.3

0.2

10 10

0.1 0 0.1 0 −0.1

0.5

2

1

5

−10 −0.2

−0.1

−0.3

−3

−0.5

−0.7

−1

−1.5

−1.95

−0.2

−1

Figure 9: A load pull simulation showing constant power contours at 0 dBm input power. j1 j2

j0.5

Pin = 0 dBm

j0.2 Pin = 12.5 dBm 0

0.2

0.5

1

2

− j0.2

− j0.5

Zo = 50 Ohms

− j2 − j1

Figure 10: Γopt plotted for increasing input power (circles) overlaid with the two chosen loads presented by the variable output matching network (triangles).

difference in PAE at high input powers where the two matching networks effectively have the same values. The PA is operating in a strongly nonlinear mode with an input referred 1 dB compression point of 4.3 dBm and an input IP3 of 13.9 dBm. Power consumption for Pout = 15 dBm is 153 mW.

4.

CONCLUSION

A design procedure for a MEMS capacitive switch, emphasizing integration in a standard IC design, has been presented. The procedure focuses on the circuit designer’s requirements for inclusion in new circuit topologies. The design procedure

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EURASIP Journal on Wireless Communications and Networking 70 60 PAE (%)

Pout (dBm)

22 20 18 16 14 12 10

50 40 30 20

0

5

10

15

0

5

Pin (dBm)

10

15

Pin (dBm)

Fixed match Variable match

Fixed match Variable match

Figure 11: Pout and PAE for the fixed (optimized for high power only) and variable (optimized for high and low power) matching networks.

is applied to create a MEMS switch for use in a dual-band LNA. RF and physical measurements characterize the device for simulation. The LNA is designed in 0.18 μm CMOS to operate at 2.4 GHz and 5.2 GHz with forward gain of 11.6 dB and sub-4.5 dB noise figure for both bands, and with improved isolation between bands. A tunable power amplifier at 5.2 GHz is also designed in 0.18 μm CMOS using MEMS switches and realizes a 37% improvement in PAE at lower input powers. ACKNOWLEDGMENTS This work is supported in part by the National Sciences and Engineering Research Council of Canada and Micronet. CMOS fabrication access was provided by CMC Microsystems.

[9]

[10]

[11]

[12]

REFERENCES [13] [1] J. J. Yao, “RF MEMS from a device perspective,” Journal of Micromechanics and Microengineering, vol. 10, no. 4, pp. R9–R38, 2000. [2] G. M. Rebeiz and J. B. Muldavin, “RF MEMS switches and switch circuits,” IEEE Microwave Magazine, vol. 2, no. 4, pp. 59–71, 2001. [3] J. Y. Park, G. H. Kim, K. W. Chung, and J. U. Bu, “Fully integrated micromachined capacitive switches for RF applications,” in Proceedings of IEEE MTT-S International Microwave Symposium Digest, vol. 1, pp. 283–286, Boston, Mass, USA, June 2000. [4] G. M. Rebeiz, RF MEMS: Theory, Design, and Technology, John Wiley & Sons, Hoboken, NJ, USA, 2003. [5] L. Dussopt and G. M. Rebeiz, “Intermodulation distortion and power handling in RF MEMS switches, varactors, and tunable filters,” IEEE Transactions on Microwave Theory and Techniques, vol. 51, no. 4, part 1, pp. 1247–1256, 2003. [6] J. B. Muldavin and G. M. Rebeiz, “High-isolation CPW MEMS shunt switches - part 1: modeling,” IEEE Transactions on Microwave Theory and Techniques, vol. 48, no. 6, pp. 1045–1052, 2000. [7] J. Y. Qian, G. P. Li, and F. De Flaviis, “Parametric model of MEMS capacitive switch operating at microwave frequencies,” in Proceedings of IEEE MTT-S International Microwave Symposium Digest, vol. 2, pp. 1229–1232, Boston, Mass, USA, June 2000. [8] J. Rose, L. Roy, and N. Tait, “Development of a MEMS microwave switch and application to adaptive integrated

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antennas,” in Proceedings of the IEEE Canadian Conference on Electrical and Computer Engineering (CCECE ’03), vol. 3, pp. 1901–1904, Montreal, Canada, May 2003. Z. Li and K. O. Kenneth, “A low-phase-noise and low-power multiband CMOS voltage-controlled oscillator,” IEEE Journal of Solid-State Circuits, vol. 40, no. 6, pp. 1296–1302, 2005. W.-S. Wuen and K.-A. Wen, “Dual-band switchable low noise amplifier for 5-GHz wireless LAN radio receivers,” in Proceedings of the 45th IEEE Midwest Symposium on Circuits and Systems (MWSCAS ’02), vol. 2, pp. 258–261, Tulsa, Okla, USA, August 2002. K. L. Fong, “Dual-band high-linearity variable-gain low-noise amplifiers for wireless applications,” in Proceedings of the IEEE International Solid-State Circuits Conference (ISSCC ’99), pp. 224–225, San Francisco, Calif, USA, February 1999. A. Schmidt and S. Catala, “A universal dual band LNA implementation in SiGe technology for wireless applications,” IEEE Journal of Solid-State Circuits, vol. 36, no. 7, pp. 1127–1131, 2001. M.-Y. Wang, R. R.-B. Sheen, O. T.-C. Chen, and R. Y. J. Tsen, “A dualband RF front-end for WCDMA and GPS applications,” in Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS ’02), vol. 4, pp. 113–116, Scottsdale, Ariz, USA, May 2002. H. Hashemi and A. Hajimiri, “Concurrent dual-band CMOS low noise amplifiers and receiver architectures,” in Proceedings of the IEEE Symposium on VLSI Circuits, pp. 247–250, Kyoto, Japan, June 2001. D. K. Shaeffer and T. H. Lee, “A 1.5 V, 1.5 GHz CMOS low noise amplifier,” in Proceedings of the IEEE Symposium on VLSI Circuits, pp. 32–33, Honolulu, Hawaii, USA, June 1996. D. K. Shaeffer and T. H. Lee, “Erratum: a 1.5 V, 1.5 GHz CMOS low noise amplifier,” IEEE Journal of Solid-State Circuits, vol. 40, no. 6, pp. 1397–1398, 2005. T. K. K. Tsang and M. N. El-Gamal, “Dual-band sub-1V CMOS LNA for 802.11A/B WLAN applications,” in Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS ’03), vol. 1, pp. 217–220, Bangkok, Thailand, May 2003. L.-H. Lu, H.-H. Hsieh, and Y.-S. Wang, “A compact 2.4/5.2GHz CMOS dual-band low-noise amplifier,” IEEE Microwave Wireless Components Letters, vol. 15, no. 10, pp. 685–687, 2005. G. Hanington, P.-F. Chen, P. M. Asbeck, and L. E. Larson, “High-efficiency power amplifier using dynamic powersupply voltage for CDMA applications,” IEEE Transactions on Microwave Theory and Techniques, vol. 47, no. 8, pp. 1471– 1476, 1999.

John Danson et al. [20] B. Sahu and G. A. Rincon-Mora, “A high-efficiency linear RF power amplifier with a power-tracking dynamically adaptive buck-boost supply,” IEEE Transactions on Microwave Theory and Techniques, vol. 52, no. 1, part 1, pp. 112–120, 2004. [21] N. Srirattana, A. Raghavan, D. Heo, P. E. Allen, and J. Laskar, “Analysis and design of a high-efficiency multistage Doherty power amplifier for wireless communications,” IEEE Transactions on Microwave Theory and Techniques, vol. 53, no. 3, pp. 852–859, 2005. [22] A. C. Cotler and E. R. Brown, “The feasibility of a variable output matching circuit in a high-power SSPA,” in Proceedings of IEEE Radio and Wireless Conference, pp. 189–191, Boston, Mass, USA, August 2002. John Danson received his B.Eng. and M.A.Sc. degrees in electrical engineering from Carleton University, Ottawa, Ontario, Canada in 2002 and 2005, respectively. He has worked with several companies on RF projects including Nautel, Research In Motion, and TransCore. As a Member of the IEEE, his research interests include applications for MEMS devices in RF integrated circuits. Calvin Plett has been with Carleton University, Ottawa, Canada since 1989 and is now an Associate Professor. Prior to 1982, he worked for a number of companies including nearly four years with Atomic Energy of Canada, and shorter periods with Xerox, Valcom, Central Dynamics, and Philips. From 1982 to 1984, he worked with BellNorthern Research doing analog circuit design. For some years he did consulting work for Nortel Networks in RFIC design. For the last number of years he has been involved in collaborative research, with numerous graduate and undergraduate students and various companies including Nortel Networks, SiGe Semiconductor, Philsar, Conexant, Skyworks, IBM, and Gennum. He has authored or coauthored more than 60 technical papers which have appeared in international journals and conferences. He is a coauthor of Radio Frequency Integrated Circuit Design and a coauthor for Integrated Circuit Design for High-Speed Frequency Synthesis. His research interests include the design of analog and radio-frequency integrated circuits, including filter design, and communications applications. He is a Member of AES, the PEO, and a Senior Member of the IEEE. He was the coauthor of papers that won the Best Student Paper Awards at BCTM 1999 and at RFIC 2002. Niall Tait received a B.S. degree in engineering physics from the University of Alberta, M.A.Sc. degree in physics from University of British Columbia, and Ph.D. degree in electrical engineering from the University of Alberta. In 1992 he joined the Alberta Microelectronic Center as a Research Scientist working on silicon MEMS and thin film technology. Since 1997 he has been a faculty member in the Department of Electronics at Carleton University working on MEMS and thin film technology for RF and microwave applications, sensors, photonics, and microfluidics.

9

Hindawi Publishing Corporation EURASIP Journal on Wireless Communications and Networking Volume 2006, Article ID 93712, Pages 1–12 DOI 10.1155/WCN/2006/93712

Modeling and Characterization of VCOs with MOS Varactors for RF Transceivers Pedram Sameni,1 Chris Siu,2 Shahriar Mirabbasi,1 Hormoz Djahanshahi,3 Marwa Hamour,1 Krzysztof Iniewski,2 and Jatinder Chana3 1 Department

of Electrical and Computer Engineering, University of British Columbia, Vancouver, British Columbia, Canada V6T 1Z4 of Electrical and Computer Engineering, University of Alberta, Edmonton, Alberta, Canada T6G 2V4 3 PMC-Sierra, Burnaby, British Columbia, Canada V5A 4X1 2 Department

Received 1 September 2005; Revised 8 March 2006; Accepted 17 May 2006 As more broadband wireless standards are introduced and ratified, the complexity of wireless communication systems increases, which necessitates extra care and vigilance in their design. In this paper, various aspects of popular voltage-controlled oscillators (VCOs) as key components in RF transceivers are discussed. The importance of phase noise of these key blocks in the overall performance of RF transceivers is highlighted. Varactors are identified as an important component of LC-based oscillators. A new model for accumulation-mode MOS varactors is introduced. The model is experimentally verified through measurements on LCbased VCOs designed in a standard 0.13 μm CMOS process. Copyright © 2006 Pedram Sameni et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

1.

INTRODUCTION

In the recent years, the demand for wireless communications has increased considerably. Wireless communication systems encompass a wide variety of standards. Such systems include cellular phones (e.g., GSM, CDMA), wireless local area networks (WLANs), wireless personal area networks (WPANs), wireless metropolitan area networks (WMANs), and so forth. The adoption of any of these technologies depends on many variables such as cost and market demand. Over time, the implementation cost of the technologies goes down, which further accelerates their adoption. The hightech market research firm, In-Stat, forecasts that the worldwide wireless market will grow to more than 2.3 billion subscribers by 2009. Typical RF transceivers have a built-in frequency synthesizer, namely local oscillator (LO), to generate a signal with the desired frequency used for up and down conversions. Wireless standards strictly specify the minimum level of the received signal, the maximum level of unwanted signal, the channel bandwidth, and the spacing between two adjacent channels. Using these specifications and targeting the required signal-to-noise ratio (SNR) after downconversion, the maximum amount of acceptable phase noise on the LO can be calculated. This procedure is conceptually depicted in

Figure 1 for the GSM-1800 standard. Using the information provided in the figure and knowing the desired SNR (e.g., 9 dB after downconversion), the maximum acceptable phase noise at 600 kHz offset from the carrier (which is at the center of the adjacent channel) is calculated to be 121 dBc/Hz [1]. Figure 2 illustrates the problems that may arise if the LO spectrum extends to the adjacent channel with relatively high-power spectral density: after downconversion, there will be an overlap between the spectra of the desired signal and the unwanted adjacent channel. Unless a special technique is used, the recovery of the data becomes almost impossible. LOs are usually in the form of voltage-controlled oscillators (VCOs) and are placed inside a feedback loop as part of a phase-locked loop (PLL) system. As a result, they constantly align their zero-crossings with the reference clock. The amount of generated phase noise, within the bandwidth of the PLL, can be reduced by the loop characteristics. Table 1 compares the maximum allowable phase noise of some of the wireless standards at their nominal frequencies. Figure 3 shows the block diagram of a PLL-based frequency synthesizer typically used in integrated wireless transceivers. This synthesizer comprises of phase (and usually frequency) detector (PD or PFD), charge pump, lowpass

2

EURASIP Journal on Wireless Communications and Networking Unwanted signal of the adjacent channel with maximum of 43 dBm

Desired channel with minimum allowable GSM signal of 102 dBm

Unwanted signal of the adjacent channel

White noise floor

 1.8 GHz

200 KHz

600 KHz 200 KHz

200 KHz

Figure 1: GSM channel around 1.8 GHz.

Unwanted signal in the adjacent channel

Desired signal

fRF

Local oscillator (LO)

fLO

Desired signal overlaps with interference after downconversion fRF

LO

Figure 2: Channel interference in the case of larger-than-expected phase noise.

filter, voltage-controlled oscillator (VCO), reference, and feedback divider blocks (/M and /N). The output frequency of the block is N/M times the reference frequency. Therefore, by adjusting the N/M ratio, different multiples (integer or fractions) of the reference frequency can be generated. The phase transfer function from the reference to the output of this system exhibits a lowpass characteristic. As a result, high-frequency phase noise1 of the reference clock is attenuated by the loop, while its low-frequency (close-in) noise passes through the system to the output. On the other hand, phase jitter of the VCO will see a high-pass function to the output, which means that low-frequency jitter of the VCO is suppressed within the bandwidth of the phase-locked system. The total output phase noise is a function of the phase noise of each of the PLL blocks, the input phase noise generated by the reference clock, and noise shaping characteristics of the loop. While there are different techniques for optimizing the performance of the synthesizers to reduce the total phase noise, VCO plays a key role in total phase noise of the system. This is because high-frequency perturbation on the VCO control line tends to appear at the output in the form of phase variations. In addition, any high-frequency (a.k.a. outof-band) phase noise generated by the VCO due to supply, substrate, or device noise cannot be suppressed by the loop and directly travels to the output. In this paper, our main focus will be on VCO as a key block of RF transceivers. 1

The time-domain counterpart of phase noise is jitter, which is a more common term in wireline applications.

Frequency synthesizer circuits have been predominantly implemented in technologies such as III-V, silicon bipolar, or SiGe BiCMOS due to their high-speed and low-noise characteristics. However, circuits implemented in these technologies are still expensive, and are not very area efficient. Moreover, they are not suitable for system-on-chip integration. Recent advances in CMOS technologies have made CMOS an attractive alternative for implementing high-speed systems, including their oscillators. Advantages of CMOS implementation include lower cost, higher manufacturing yield, lower power, and higher levels of integration, with the possibility of integrating analog and digital circuits on the same chip. Therefore, there is a growing trend in industry to extend the use of CMOS circuits to high-speed integrated digital and mixed-signal systems, system-on-a-chip (SoC), and systemin-a-package (SiP) designs. However, designing high-speed mixed-signal circuits (e.g., multi-gigahertz systems) in advanced CMOS technologies is very challenging. Issues such as speed, substrate noise coupling, reduced voltage headroom, and increased leakage current pose many difficulties in the design of high-speed CMOS circuits. In the following sections, first, various aspects of some of the well-known VCO architectures, including their phase noise performance, are compared. LC VCO is identified as having the best performance in terms of phase noise. In Section 3, the building components of various LC VCOs are investigated and their effects on overall phase noise are studied. To facilitate this investigation, three forms of LC VCOs are used that are implemented in a standard 0.13 μm CMOS process. In addition, some varactor test structures are used to characterize the tuning curve of the LC VCOs and their

Pedram Sameni et al.

3 Table 1: Comparison between phase noises of different wireless standards.

Wireless standard GSM

WLAN

WPAN

850 900 1800 1900

Frequency 850 MHz 900 MHz 1800 MHz 1900 MHz

802.11a

5 GHz

802.11b

2.4 GHz

802.11g

2.4 GHz

ZigBee (802.15.4)

900 MHz 2.4 GHz

95 dBc/Hz at 5 MHz

Bluetooth (802.15.1)

2.4 GHz

94 dBc/Hz at 100 KHz [2]

Crystal osc. Ref.

M

Phase noise 121 dBc/Hz at 600 KHz 121 dBc/Hz at 600 KHz 121 dBc/Hz at 600 KHz [1] 121 dBc/Hz at 600 KHz Many WLAN transceivers specify “integral” noise in degrees rms over a frequency range, for example, integral of phase noise from 10 K to 10 M < 1.2Æ rms for the whole TX path, or 0.8Æ rms for the synthesizer. This may also be translated to an average phase noise spec, like P.N. < 90 dBc/Hz at < 100 KHz (in-band, or close-in)

Phase/ freq. detector

Charge pump

N

Lowpass filter

VCO

Output

Figure 3: A block diagram of a frequency synthesizer.

relationship with the C-V curve of varactors. A new practical model for accumulation-mode MOS varactors is then introduced. Experimental results follow in Section 4 and concluding remarks in Section 5. 2.

Vin

+

+

H(s)

Vout

+

COMPARISON OF POPULAR VCO ARCHITECTURES

VCOs are one of the main building blocks of RF transceivers. They are utilized inside PLL-based circuits (e.g., frequency synthesizers as part of LO) to generate a clean and low-jitter clock signal for the operation of other blocks of the frequency synthesizer or transceiver. Typical oscillator circuits require some form of positive feedback around a gain stage in order to sustain their oscillation. This concept is illustrated in Figure 4. The closed-loop system (oscillator) has to fulfill the following two Barkhausen conditions at all times for continuous oscillation:   H( jω)  1,

∠H( jω) = 360Æ .

(1)

Three common categories of oscillator circuits are relaxation (Figure 5), ring (Figure 6), and LC-based (Figure 7) os-

Figure 4: A gain stage with a positive feedback loop.

cillators. In a relaxation oscillator (a.k.a., multivibrator), the oscillation relies on nonlinear switching that charges and discharges a capacitor with a time constant. The oscillation frequency is tuned by varying this time constant (e.g., through a current source). Relaxation oscillators are usually limited to moderate frequencies. Ring oscillators (Figure 6) are normally designed by cascading an odd number of inverters in a loop. Alternatively, an even number of differential delay cells can be used with an explicit polarity inversion in the feedback connection. A variable delay element (e.g., variable resistor or current source) is used for tuning. The frequency range

4

EURASIP Journal on Wireless Communications and Networking VDD

VDD Vbias R2

R1

M1

M0

VDD

M2

L1

L2

C

C1

Vcontrol

M1

M2

C2

L

Itune

C1 M1

Vcontrol

C2

M2 M3

Figure 5: Relaxation oscillator.

Vbias

Inverters with controllable delay

M4

M0

(a) Simple LC VCO

(b) LC VCO with a PMOS current source






VDD

M1

M2

Figure 6: Ring oscillator.

L C1

can also be adjusted by digitally adding or removing inverters from the chain (coarse tuning). On the downside, the ring and relaxation oscillators suffer from a poor frequency stability, which manifests itself as higher phase noise. LC-based oscillators are usually made with a differential pair amplifier, using LC tank as the load. By connecting the outputs to the inputs, the amplifier starts to amplify the noise at its inputs around the resonance frequency of the tank, provided that its open loop gain is greater than one (first of the two Barkhausen conditions). Noise at other frequencies gets filtered out by the LC tank. This filtering characteristic of LC-based oscillators has made them the best in terms of phase-noise performance. Furthermore, compared to the other two oscillator architectures, LC oscillators typically operate more reliably at higher frequencies, provided an LC tank of moderate- to high-quality factor. However, they suffer from their inherently narrower tuning range. Moreover, the integration of LC-based oscillators is more costly due to the large space allocated to on-chip inductors. It should be noted that, as technology advances, achieving higher frequencies becomes more feasible, which in turn requires smaller (less spacious) inductors. Table 2 summarizes the advantages and disadvantages of the three oscillator architectures [3]. 3.

LC-BASED VCOs

Figure 7 illustrates three forms of typical LC VCO implementations in CMOS. Figure 7(a) represents the simplest implementation, with an nMOS current source and an nMOS dif-

Vcontrol

M3

Vbias

C2

M4

M0

(c) LC VCO with an nMOS current source

Figure 7: Different versions of LC-based oscillator.

ferential pair as the gain stage (also referred to as “negative resistance”), which cancels out the loss of the tank. A pair of varactors has been used for frequency tuning. The use of differential signaling is another advantage compared to single-ended VCOs (e.g., ring oscillator in Figure 6). It results in higher oscillation swing in a constantly shrinking supply voltage environment, and less susceptibility to environmental noise due to rejection of the common-mode component of the noise. Figures 7(b) and 7(c) represent two other popular implementations of LC VCOs, which result in lower overall phase noise compared to simple LC VCO in Figure 7(a). They have two differential pairs that generate negative transconductance to cancel the tank loss. According to [4], if the

Pedram Sameni et al.

5 Table 2: Comparison of existing popular oscillator architectures [3]. LC oscillator

Speed Phase noise Integration Tunability Stability

Ring oscillator Technology dependent (0.01–10 s of GHz)

Good Poor (inductor and varactor) Narrow/slow Good

oscillation waveform is symmetrical (i.e., equal rise and fall times), the DC component of the phase noise gets eliminated, which is the component that also carries flicker (1/ f ) noise. As a result, the two architectures shown in Figures 7(b) and 7(c) potentially have lower phase noise compared to the architecture in Figure 7(a), which has asymmetrical rise and fall times. The use of nMOS or pMOS current sources creates a level of shielding between substrate (ground) or power supply (VDD), respectively, which subsequently lowers the phase noise due to substrate or supply noise. In technologies where larger supply voltages are available, using voltage regulators is recommended for the VCO to further reduce the oscillator phase noise resulting from substrate and supply noise. Other than noise components contributed by the oscillator’s active elements (as well as supply and substrate), there are other sources of noise resulting from the losses in nonideal passive elements (inductors and varactors), which further degrade the overall phase noise performance of the LC oscillator. To reduce the noise floor due to the lossy inductors, inductors with higher quality factors (Q) need to be used, since they result in lower resistive loss and subsequently lower thermal noise and lower power dissipation. To some extent, however, this is limited by the technology, as the thickness of the metal layers and substrate losses are technology dependent, leaving the designer with fewer degrees of design freedom (e.g., increasing the width of inductor wires to lower the loss would degrade the self-resonance frequency). Various solutions are limited by other criteria, such as silicon-area usage. Although design of high-Q onchip inductors is a topic of active research, our focus in the following sections remains on varactors as the tuning element of LC VCOs. The design, characterization, and modeling of the varactors significantly affect the overall performance of the LC VCO. 3.1. Varactors Varactors are a principal component of LC VCOs used for frequency fine tuning. Digitally controlled switched varactors or switched capacitors could also be used for coarse tuning in some designs. Traditionally, reversed-biased pn junction diodes acted as the varactor for LC VCOs (this is still true in the case of bipolar VCOs). However, MOS-based varactors are gaining popularity over the reverse-biased diodes due to wider tuning range and higher Q factor, both of which improve with every new process generation. Higher doping levels in silicon, which in turn result in lower resistive losses

Multivibrator

Poor Excellent Wide/fast Poor (needs acquisition aid with a PLL)

A

B

Figure 8: An nMOS transistor configured as a varactor.

and lower phase noise, have driven this improvement. It has become more evident in recent designs in advanced CMOS technologies (e.g., 0.18 μm, 0.13 μm, 90 nm) as implementation of monolithic high-speed VCOs becomes feasible. An nMOS varactor can have the same structure as an nMOS transistor, with gate as the first terminal and drain, source, and bulk connected together to form the second terminal (Figure 8). MOS varactors operate in four main regions, based on the biasing point (voltage across the varactor terminals): accumulation, depletion, weak inversion, and strong inversion. Accumulation and strong inversion are two regions where most varactors are designed to operate in. Furthermore, a study on accumulation-mode and inversion-mode varactors reveals that LC oscillators based on accumulation-mode varactors demonstrate lower power consumption and lower phase noise at large offset frequencies from the carrier, compared to those based on strong inversion varactors [5]. In most applications, designers would like to ensure that the capacitance of the varactor is a monotonic function of the biasing voltage. For instance, in an LC VCO, it would be desirable, as mentioned earlier, to have the varactor operating predominantly in accumulation mode. However, using a regular nMOS, as in Figure 8, does not warrant this, as the operation region is voltage dependant. It is also worth noting that the C-V curve of a regular nMOS is frequency dependant. Figure 9 illustrates the cross-section of a varactor structure. It may seem similar to an nMOS transistor, however, the n+ regions have been buried in n-well, instead of p-well. This configuration guarantees that the device does not enter the inversion-mode at all; hence the name accumulation-mode MOS (AMOS) varactor. The C-V characteristics of an MOS varactor can be predicted using 2D/3D numerical simulators. Unfortunately, these simulation tasks require precise knowledge of the underlying doping profiles, which usually are not readily available. An alternative is to perform capacitance measurements.

6

EURASIP Journal on Wireless Communications and Networking 7

Gate (G) Bulk (B)

p+

n+

n-well

6.8

n+

p-substrate

Figure 9: Cross-section of an accumulation-mode MOS (AMOS) varactor.

Oscillation frequency (GHz)

Sub

6.6 6.4 6.2 6 5.8 5.6 5.4 5.2 5

However, measuring subpico Farad capacitances is difficult and requires a fairly expensive S-parameter RF measurement setup. It is, therefore, very useful to predict the tuning characteristics of LC oscillators using standard foundry-supplied models for MOSFETs. Recently, a lot of effort has been expended on modeling the C-V characteristics of MOS varactors, partly due to the increasing popularity of CMOS LC VCOs in which such varactors are used. One type of model is based on physically meaningful parameters [6] that describe the characteristics of the device with different equations for different regions of operation. Another model based on the physical parameters of the device is reported in [7]. However, simulating and using these types of models are not simple in SPICE or similar simulators, as they require defining mathematical functions inside the tool. Other models have been developed based on subcircuits utilizing BSIM SPICE models [8]. These models are suitable for simulator implementation within the circuit-design environment and could be easily adopted for future technologies. In the following sections, we introduce a SPICE-like model that takes advantage of already developed foundry models of transistors to create a practical model for accumulation-mode varactors. First we take a closer look at the tuning characteristics of LC VCOs, which further emphasizes the need for a good varactor model. 3.2. VCO design and tuning characteristics For the following analysis, we used a standard LC VCO circuit with current source isolating the core of the oscillator from the ground, as shown in Figure 7(b). The structure is designed for 5–6 GHz operation. Inductance L is 1.5 nH, and the total equivalent capacitance is in the range of 0.35 pF to 0.65 pF. It may seem that the modeling of the tuning characteristics is a straightforward task, as the oscillation frequency is given by the following well-known formula: fosc =

1  , 2π L  C(V )

(2)

where L is the inductance and C(V ) is the equivalent capacitance for a given biasing point. However, a simple test indicates that the modeling process is more involved than it might initially appear. From the measured tuning

0

0.2

0.4

0.6

0.8

1

1.2

Control voltage (V) Simulation Measurement

Figure 10: Measured versus modeled VCO tuning characteristics (extracted piecewise linear model).

characteristics (the experimental devices are described later in the paper) the equivalent capacitance can be extracted using (2): C(V ) =

1 4π 2 f

osc

2

L

.

(3)

Having determined C(V ) values (3), an extracted piecewise linear model of the voltage-dependent capacitance is reconstructed and fed back to SPICE for simulation. The results of this comparison, shown in Figure 10, indicate discrepancies up to 7%. These discrepancies can be attributed to the effective varactor capacitance. The varactor capacitance gets modulated in time depending on the signal swing of the oscillator output, which in turn changes the effective capacitance of the tank [9–11]. We have used a method similar to that reported in [9] to calculate the effective capacitance. In our calculations, we neglect the current components at harmonics of fosc as they play only a small role in determining the frequency of oscillation. Equation (4) is the revised version of (2), used to obtain the VCO’s tuning characteristic: fosc =





1

2π L  Cav (V ) + Cpar (V )

.

(4)

In this equation, Cpar is the equivalent parasitic capacitance associated with input of the next buffer, interconnects, and device capacitances of M1–M4, the latter being somewhat voltage dependent. Cav is the average capacitance of C1 and C2 in series (Figure 7(b)), calculated according to the method described in [9]. The average capacitance is the ratio of the rms value of the varactor’s current, i(t), to the rms value of dV/dt, where V (t) is the voltage across the varactor. As shown in Figure 11, if the voltage swing is small (compared to nonlinearities of the C-V characteristics), then the

Pedram Sameni et al.

7

0.9

short structure, (b) the open structure, and (c) the device under test (DUT), that is, varactor array. Figure 13 shows the micrograph of some of the test structures on the die. These test structures from left to right are: short, open (including dummy varactors), and the varactor array (DUT).

0.8

Vpeak = 400 mV

0.6

Vpeak = 1.2 V

C1

av

(pF)

0.7

3.3.1. De-embedding technique

0.5 0.4 Vpeak = 800 mV

0.3 0.2 1.5

1

0.5

0

0.5

1

1.5

VBG (V)

Figure 11: C-V characteristics for three different values of the oscillator voltage swing (V peak).

equivalent large-signal C-V characteristic closely resembles its small-signal counterpart. Here, C1av refers to average capacitance of C1 calculated for different output swings. However, for large values of the voltage swing the equivalent characteristics get smoothed or averaged over larger voltage range. As a result, the tuning characteristic becomes dependent on the voltage swing, which in turn is affected by the magnetic and resistive losses in the tank. Calculation of the equivalent large-signal C-V characteristics depends on the shape of the oscillator’s output (rectangular, sinusoidal, etc.). However, at high frequencies the current waveform can be approximated by a sinusoid due to the finite switching time and limited gain [12]. Equation (5) shows the relationship between the swing and tank losses in this LC VCO: VTank  Itail  Rloss ,

(5)

where Rloss is the equivalent parallel resistance of the tank and Itail is the drain current of the current source transistor (M0 in Figure 7(b)). The effective C-V characteristics (Figure 11) and their associated VCO tuning curves are obtained using (4) and (5) and the method proposed in [9]. 3.3. Characterization Several accumulation-mode varactor test structures are placed on a test chip. Other than varactors, a short structure and an open structure are also placed on the chip to facilitate the de-embedding procedure. For this experiment, two different varactors are characterized. Both varactors are made up of multiples of a unit varactor cell: one has 100 multiples (m100 array) and the other has 60 multiples (m60 array). The unit varactor cell has a width of 7.9 μm and a gate length of 0.13 μm. To reduce the effect of distributed gate resistance, contacts are used on both sides of the polysilicon gates. Figure 12 illustrates the three test structures: (a) the

Agilent 8510C vector network analyzer (VNA) is used for two-port RF characterization. S-parameters of the varactors, open, and short structures are measured from 100 MHz up to 6 GHz. The varactor voltage is varied from 1.5 V to 1.5 V, with 100 mV resolution. Different de-embedding techniques are currently used. In [13], a three-step de-embedding technique is used that employs two short structures, an open structure and a thrustructure instead of only short and open structures. A number of de-embedding techniques have been discussed in [14]. We used two-step open/short de-embedding (OSD). Figure 14 shows the equivalent circuit representation of the parasitic series impedance and shunt admittance of interconnects and contact pads, respectively. Z1 and Z2 are the interconnection series impedances from pads to the varactor. Y1 and Y2 are the equivalent shunt admittances between the signal and ground (pad capacitance, substrate capacitance, and resistance). We used signal-ground (SG or GS) probes. However, GSG probes are preferred, as they result in balanced electrical characteristics. Figure 15 illustrates a different lumped model for OSD, as presented in [14]. Here Z1 and Z2 are the impedances between the probe tips and the pads on the CMOS chip as the probe calibration is performed on an impedance-standardsubstrate (ISS). The ISS uses gold metallization instead of typical aluminum traces, and has a lower resistance. Both approaches to de-embedding shown in Figures 14 and 15 were carefully considered. However, we concluded that in our setup, interconnection impedances are dominant. Based on the parasitic lumped model of Figure 14, Y1 and Y2 are extracted from the following equations: Y1 = Y11,open , Y2 = Y22,open .

(6)

Z1 and Z2 can then be calculated using the following equations: 1 Z1 = , Y11,short Y1 (7) 1 Z2 = . Y22,short Y2 Yii,open and Yii,short (i = 1, 2) are the input or output admittances of the open and short structures, respectively. 3.3.2. Parameter extraction procedure Figure 16 shows the circuit model of the accumulation-mode varactor [6]. In this figure, CS represents the main variable

8

EURASIP Journal on Wireless Communications and Networking

Signal

Signal

Signal

Signal

Signal

Signal

DUT

Ground

Ground

Ground

Ground

(a)

Ground

Ground

(b)

(c)

Figure 12: Top-view of the test structures: (a) short, (b) open, and (c) DUT (varactor array).

Rs is equal to real part of Za (i.e., Re(Za )), and Cs is calculated from CS =

ω 2 Lg

1  , ω  Im Za

(10)

where Lg is also calculated at higher frequencies (e.g., 6 GHz) using 

Figure 13: Micrograph of the test structures in 0.13 μm CMOS, from left to right: short, open, and the varactor array (DUT).

capacitance associated with the series capacitance of the gate oxide and the depletion region under the gate. C f models the fringing capacitance related to the sidewalls of the gate. Lg is the inductance of the poly gate. Rs is the poly gate and channel resistance (the latter is voltage dependent), and Rnwell is the resistance of the n-well. Cdep is the depletion capacitance associated with the reversed biased p-sub/n-well diode. Rsub and Csub are the substrate parasitics. Rsd is the resistance of the n+ regions (bulk electrode). In order to verify the model shown in Figure 16, we need to characterize the de-embedded on-chip varactors (m60 and m100 arrays). Figure 17 shows the simplified form of Figure 16. In this figure, we have neglected Rsd (Zc ), as the impedance of the highly doped n+ regions is very small (less than 1 Ω in these test structures). Using the simplified circuit shown in Figure 17, we extract Za and Zb from the following two equations: Za =

1 = Z11 Y11

Z12 , (8)

Zb = Z12 = Z21 = Z22 , where Z11 , Z12 , Z21 , and Z22 are the equivalent Z-parameters of the two-port varactor (Figure 17) and Y11 is the input admittance (gate-side) of the equivalent Y-parameters. Za can be written as (neglecting C f ): Za = RS +

1 + jωLg . jωCS

(9)

Using (9) and employing numerical methods, we extracted the elements of Za for both varactors (m60 and m100 arrays).

Lg =



1 + ωCS-Low  Im Za , ω2 CS-Low

(11)

CS-Low is the capacitance at lower frequencies (e.g., 100 MHz), where ω2 Lg is insignificant and can be removed from (10). The quality factor (Q) of the varactor, which is the ratio of the stored energy to the dissipated energy (resistive loss) in the varactor, can also be approximated by     Im Za    .

Q= 

Re Za

(12)

The substrate effect (Zb ) is calculated using similar methods described for Za . 3.4.

Varactor modeling

As indicated earlier, modeling of tuning characteristics using (2) is fairly complicated. Not only do the varactor C-V characteristics have to be measured, but also the losses of the tank have to be determined to properly find the oscillation swing and hence the effective tank capacitance. An alternative approach would be to use the equivalent circuit representation of the varactor created from foundry-supplied transistor models and SPICE simulation to predict the tuning range. If a varactor is operating in the strong inversion mode, an nMOS transistor with tied source and drain can be used as a primitive model, since the varactor structure is the same as that of an MOS transistor. However, varactors that are working in the accumulation mode are usually laid out as shown in Figure 9. This structure inhibits the formation of the inversion layer. Wider tuning range and lower parasitic resistance are other advantages of this implementation [5]. On the other hand, the use of a plain transistor for modeling this varactor is not viable because the device does not resemble a transistor.

Pedram Sameni et al.

9 Z1

Z2 S2 pad

S1 pad DUT (varactor)

Y1

Y2

Ground pad

Ground pad

Figure 14: Equivalent lumped model of the varactor (DUT) with associated parasitics (open/short de-embedding). Z1¼

Z2¼ DUT (varactor)

S1

S2

Y1¼

Y2¼

Ground

Ground

Figure 15: Alternative lumped model for open/short de-embedding (OSD).

Za

Za Cf

Gate

Bulk

Zc Gate

Lg

Rs

Rsd

Cs

Bulk Zb

Rnwell Cdep Sub

Csub

Rsub

Zb

Figure 16: Equivalent lumped model of the integrated varactor.

Figure 16 illustrates the model of this varactor constructed with passive circuit elements, and based on physical parameters [6]. As mentioned above, this model requires the implementation of nonstraightforward equations (e.g., hyperbolic tangent) in the circuit-design environment and may involve other approximations as well. Moreover, the model cannot be easily scaled to future technologies.

Sub

Figure 17: Simplified circuit of the two-port varactor in Figure 16.

We have considered a number of different equivalent models reported in the literature and developed a new model that closely approximates the measured characteristics of the VCO [15]. This improved model is shown in Figure 18, and is a modified version of that proposed in [8]. The overlap capacitance Cov , a voltage source Voffset , and a voltage source (dashed lines) between the bulk and drain/source have been added in the new model. To model the varactor capacitance, the equivalent circuit contains a voltage source Voffset , a capacitor Cov , and a pMOS with its source and drain connected to the ground with a high impedance (e.g., 1 GΩ resistors) to resemble floating (nonexisting) source and drain. The open circuit for the

10

EURASIP Journal on Wireless Communications and Networking Voffset = 1.1 V Gate

+

Cjunction is scaled down (e.g., by 10 6 ) or a negative power supply is used

Rg

Cav

+

5V

Bulk (n-well) Sidewall and area diode (n-well/p-sub)

Ra

Rarea and Rsidewall Sub

Figure 19: Micrograph of a VCO test structure in 0.13 μm CMOS. 50

Figure 18: SPICE model developed for the varactor.

60

4.

EXPERIMENTAL RESULTS

Three different VCO structures have been fabricated in a standard 0.13 μm CMOS process with a 1.2 V power supply. No special mixed-signal process options have been used. The micrograph of the chip is shown in Figure 19. Varactors are implemented as n+ accumulation-mode MOS capacitors with no additional mask required. Thus, the obtained designs are portable to various CMOS processes of different foundries. The three implementations have similar architectures as those depicted in Figures 7(b) and 7(c), but with different varactor values. The tail current in all three versions is 1.5 mA; hence the DC power consumption is 1.8 mW, excluding output driver and biasing circuits. The one that

70 Phase noise (dBc)

source/drain terminal is required to eliminate the inversion layer capacitance present in the channel of the pMOS but absent in the varactor structure (see Figure 9). As a result, the gate to n-well (bulk) capacitance of pMOS represents the varactor capacitance properly with an additional channel length correction for LDD (lightly doped source/drain) regions. Unfortunately in this configuration, the gate-source and gate-drain overlap components of the varactor get neglected; as a result, they have to be added back by using the fixed capacitor, Cov  Voffset represents a difference of the metal-semiconductor work function φMS , as the pMOS has p+ poly gate doping while the varactor has n+ poly doping due to their different source/drain diffusion. As doping levels in the polysilicon layer are typically close to degeneration, the Voffset is close to silicon bandgap (Eg (T)/q), which is about 1.1 V at room temperature. Finally, the junction capacitance of the pMOS transistor has to be scaled down. This can be done either by changing the scaling factor inside the SPICE model or adding a negative power supply between source/drain and the bulk (e.g., 5 V) to enlarge the depletion area and reduce the junction capacitance.

80 90 100 110 120 130 105

106

107

108

Frequency

Figure 20: Measured phase noise of the VCO with pMOS tail current (Figure 7(b)) at three different supply voltages (1.2 V, and 1.2 V  5%).

incorporates an nMOS tail current source (Figure 7(c)) exhibits higher sensitivity to the power supply noise, while the one with a pMOS tail current source (Figure 7(b)) has the best power-supply-rejection ratio (PSRR), due to the extra isolation from the power supply by the current source. In addition to the three VCO circuits, a biasing circuit and an output driver stage were added to drive external 50 Ω load. Individual varactor and inductor test structures were also included for S-parameter measurements. Open and short de-embedding structures were added for proper extraction of the equivalent circuit, as explained earlier in Section 3.3.1. The phase noise of all three VCOs was measured using a spectrum analyzer with a phase noise module. Figure 20 compares the phase noise of the VCO with the pMOS tail current shown in Figure 7(b), for three different supply voltages (1.2 V, and 1.2 V  5%) at the nominal temperature with the control voltage set to the mid-point

Pedram Sameni et al.

11

6

REFERENCES

Oscilliation frequency (GHz)

5.8

[1] J. Craninckx, M. Steyaert, and H. Miyakawa, “A fully integrated spiral-LC CMOS VCO set with prescaler for GSM and DCS-1800 systems,” in Proceedings of the IEEE Custom Integrated Circuits Conference, pp. 403–406, Santa Clara, Calif, USA, May 1997. [2] C. Samori, S. Levantino, and V. Boccuzzi, “A -94 dBc/Hz@100 kHz, fully-integrated, 5-GHz, CMOS VCO with 18% tuning range for Bluetooth applications,” in Proceedings of IEEE Custom Integrated Circuits Conference, pp. 201–204, San Diego, Calif, USA, May 2001.

5.6 5.4 5.2 5 4.8 4.6 4.4 4.2

0

0.2

0.4

0.6

0.8

1

1.2

Control voltage (V) Measurement Simulation

Figure 21: Measured versus modeled tuning characteristics (new SPICE model).

(600 mV). The phase noise at 1 MHz offset from the carrier is 95.8/ 95.5/ 95.5 dBc/Hz, respectively. The tuning characteristics were simulated using the varactor model described in Section 3.4. Excellent agreement between the model and the measurement was obtained, as shown in Figure 21. The results in Figure 21 are for a VCO test structure with an increased number of varactor fingers (varactor with 100 fingers) and hence lower center frequency compared to the results shown in Figure 10. 5.

CONCLUSION

VCOs are among the critical building blocks of wireless RF transceivers since their performance and phase noise potentially affects the overall transceiver performance. Among various VCO architectures, LC VCOs have superior phase noise performance and therefore are extensively used in RF transceivers. Varactors are the main tuning component of LC VCOs and play an important role in the phase noise performance and tuning capability of these types of VCOs. A new model for CMOS accumulation—mode varactors is presented. The model is used to predict the tuning curve of the LC VCOs. The shape of the tuning curve and the effective varactor capacitance were shown to depend on the losses of the tank and the magnitude of the tail current. The model is SPICE-based and has been verified experimentally in a standard 0.13 μm CMOS process with different VCO structures. ACKNOWLEDGMENTS The authors would like to thank Roberto Rosales of the University of British Columbia and Mark Hiebert of PMC-Sierra for assisting with the measurements. This research was supported in part by Natural Sciences and Engineering Research Council of Canada (NSERC), PMC Sierra, CMC Microsystems, and Canadian Foundation for Innovation (CFI).

[3] R. Walker, “Clock and Data Recovery for Serial Digital Communication,” ISSCC short Course, February, 2002. [4] A. Hajimiri and T. H. Lee, “A general theory of phase noise in electrical oscillators,” IEEE Journal of Solid-State Circuits, vol. 33, no. 2, pp. 179–194, 1998. [5] P. Andreani and S. Mattisson, “On the use of MOS varactors in RF VCOs,” IEEE Journal of Solid-State Circuits, vol. 35, no. 6, pp. 905–910, 2000. [6] S.-S. Song and H. Shin, “An RF model of the accumulationmode MOS varactor valid in both accumulation and depletion regions,” IEEE Transactions on Electron Devices, vol. 50, no. 9, pp. 1997–1999, 2003. [7] A.-S. Porret, T. Melly, C. C. Enz, and E. A. Vittoz, “Design of high-Q varactors for low-power wireless applications using a standard CMOS process,” IEEE Journal of Solid-State Circuits, vol. 35, no. 3, pp. 337–345, 2000. [8] K. Moln´ar, G. Rappitsch, Z. Huszka, and E. Seebacher, “MOS varactor modeling with a subcircuit utilizing the BSIM3v3 model,” IEEE Transactions on Electron Devices, vol. 49, no. 7, pp. 1206–1211, 2002. [9] R. L. Bunch and S. Raman, “Large-signal analysis of MOS varactors in C MOS -Gm LC VCOs,” IEEE Journal of Solid-State Circuits, vol. 38, no. 8, pp. 1325–1332, 2003. [10] E. Hegazi and A. A. Abidi, “Varactor characteristics, oscillator tuning curves, and AM-FM conversion,” IEEE Journal of SolidState Circuits, vol. 38, no. 6, pp. 1033–1039, 2003. [11] S. Levantino, C. Samori, A. Bonfanti, S. L. J. Gierkink, A. L. Lacaita, and V. Boccuzzi, “Frequency dependence on bias current in 5-GHz CMOS VCOs: impact on tuning range and flicker noise upconversion,” IEEE Journal of Solid-State Circuits, vol. 37, no. 8, pp. 1003–1011, 2002. [12] A. Hajimiri and T. H. Lee, “Design issues in CMOS differential LC oscillators,” IEEE Journal of Solid-State Circuits, vol. 34, no. 5, pp. 717–724, 1999. [13] H. Cho and D. E. Burk, “A three-step method for the deembedding of high-frequency S-parameter measurements,” IEEE Transactions on Electron Devices, vol. 38, no. 6, pp. 1371– 1375, 1991. [14] T. E. Kolding, “On-wafer calibration techniques for giga-hertz CMOS measurements,” in Proceedings of IEEE International Conference on Microelectronic Test Structures (ICMTS ’99), pp. 105–110, Goteborg, Sweden, March 1999. [15] P. Sameni, C. Siu, K. Iniewski, et al., “Modeling of MOS varactors and characterizing the tuning curve of 5-6 GHz of LC VCO,” in Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS ’05), pp. 5071–5074, Kobe, Japan, May 2005.

12 Pedram Sameni received his B.S. (honors) degree in electrical engineering from the University of Tehran, Iran, in 1999 and the M.A.S. degree in analog and mixed signal design from Simon Fraser University, Canada, in 2002. He is currently pursuing his Ph.D. in analog and mixed signal design in the System-on-Chip (SoC) Lab of the University of British Columbia, Vancouver, Canada. His research interests include clock and data recovery circuits for high-speed telecommunication systems. During the summer of 2004 he was with PMC-Sierra, Vancouver, Canada, where he worked on MOS varactor modeling and LC VCO characterization in CMOS 0.13 μm process. From August 2005 to March 2006 he was with Foveon, Inc., Santa Clara, USA where he worked on characterization and modeling of circuits and devices used in CMOS image censor circuits. Chris Siu received the B.S. degree in electrical engineering from Simon Fraser University, Burnaby, Canada, in 1991, and the M.S.E.E. degree from Stanford University, California, in 1994. He has over 10 years of experience in RF/Analog IC design and management, having worked for companies in both Canada and the US including PMCSierra, Philips, and Hewlett Packard. He was a Ph.D. student at the University of Alberta, Edmonton, Canada, involved in the research of RF transceiver circuits. Shahriar Mirabbasi received the B.S. degree in electrical engineering from Sharif University of Technology, Tehran, Iran, in 1990 and the M.A.S. and Ph.D. degrees in electrical and computer engineering from the University of Toronto, ON, Canada, in 1997 and 2002, respectively. During the summer of 1997, he was with Gennum Corporation, Burlington, ON, Canada, working on the system design of cable equalizers for serial digital video and HDTV applications. From January 2001 to June 2002, he was with Snowbush Microelectronics, Toronto, ON, Canada, where he worked on designing high-speed mixed-signal CMOS integrated circuits including ADC and serializer/deserializer blocks. Since August 2002, he has been an Assistant Professor in the Department of Electrical and Computer Engineering of the University of British Columbia, Vancouver, BC, Canada. His current research interests include analog and mixed-signal integrated circuits and systems design for wireless and wireline communication applications, biomedical implants, and sensor networks. Hormoz Djahanshahi received the B.S. (honors) and M.S. (honors) degrees in electrical engineering from Tehran Polytechnic University, and the Ph.D. degree in electrical and computer engineering from the University of Windsor, Canada, in 1998. In 1990–1992, he was with Fajr Microelectronics and developed biomedical instrumentation for patient monitoring in intensive care units. While at VLSI Research Group in Windsor, he worked on CMOS implementation of artificial neural networks and smart photosensors. In 1998 and 1999, he was a postdoctoral fellow at the University of Toronto, Canada, and

EURASIP Journal on Wireless Communications and Networking designed high-speed I/O, oscillators, and PLLs in CMOS and HBT technologies. He received the Best Paper Award at 1999 Micronet Symposium, Ottawa. Since 2000, he has been with PMC-Sierra, Vancouver, Canada, where he is currently a Leader in Technology Development Group. His work includes specification and design of high-performance mixed-signal blocks for multi-Gigabit-per second wireline and wireless applications. He has designed to production numerous clock synthesizer, clock/data recovery and SerDes components in 0.18 μm, 0.13 μm, and 90 nm CMOS. He has over 30 publications, one US patent, and is a Chapter Officer with IEEE SSCS in Vancouver. Marwa Hamour received her Bachelor’s of electrical and electronic engineering from the Imperial College of Science, Technology & Medicine in 2000. She received her Master’s of applied science from the University of British Columbia, Canada, and is currently reading for her Ph.D. at the same university. Krzysztof Iniewski is an Associate Professor at the Electrical and Computer Engineering Department of the University of Alberta. He is also the President of CMOS Emerging Technologies Inc., a consulting company in Vancouver. His research interests are in advanced CMOS devices and circuits for ultralow power wireless systems, medical imaging, and optical networks. From 1995 to 2003, he was with PMC-Sierra and held various technical and management positions in Research & Development and Strategic Marketing. Prior to joining PMCSierra, from 1990 to 1994 he was an Assistant Professor at the University of Toronto, Electrical Engineering and Computer Engineering Department. He has published over 80 research papers in international journals and conferences. He holds 18 international patents granted in USA, Canada, France, Germany, and Japan. He is a frequent invited speaker and consults for multiple organizations internationally. He received his Ph.D. degree in electronics (honors) from the Warsaw University of Technology (Warsaw, Poland) in 1988. Together with Carl McCrosky and Dan Minoli, he is an author of Data Networks—VLSI and Optical Fibre, Wiley, 2006. He is also an editor of Emerging Wireless Technologies, CRC Press, 2006. Jatinder Chana completed the Bachelor’s and Master’s degrees in electrical engineering at University of Victoria, BC, Canada, in 1992 and 1994, respectively. He joined PMC-Sierra in 1995 and have since then designed and implemented delta-sigma A/D converter, pipeline A/D converter, digital filters, high-speed data and clock recovery circuits for 3.125 Gbs, 2.5 Gbs Serdes, and low-jitter CSUs for 4.25 GHz and 6.25 Ghz Serdes. Prior to joining PMC-Sierra, he worked on a data acquisition and analysis system for coal, and researched digital video compression algorithms. Current interests include high-performance mixed-signal circuits and DSP.

Hindawi Publishing Corporation EURASIP Journal on Wireless Communications and Networking Volume 2006, Article ID 12945, Pages 1–16 DOI 10.1155/WCN/2006/12945

Parametric Conversion Using Custom MOS Varactors Howard Chan,1 Zhongbo Chen,1 Sebastian Magierowski,1 and Krzysztof (Kris) Iniewski2 1 Department 2 Department

of Electrical and Computer Engineering, University of Calgary, Calgary, AB, Canada T2N 1N4 of Electrical and Computer Engineering, University of Alberta, Edmonton, AB, Canada T6G 2V4

Received 14 October 2005; Revised 17 April 2006; Accepted 18 April 2006 The possible role of customized MOS varactors in amplification, mixing, and frequency control of future millimeter wave CMOS RFICs is outlined. First, the parametric conversion concept is revisited and discussed in terms of modern RF communications systems. Second, the modeling, design, and optimization of MOS varactors are reconsidered in the context of their central role in parametric circuits. Third, a balanced varactor structure is proposed for robust oscillator frequency control in the presence of large extrinsic noise expected in tightly integrated wireless communicators. Main points include the proposal of a subharmonic pumping scheme based on the MOS varactor, a nonequilibrium elastance-voltage model, optimal varactor layout suggestions, custom 0.13 μm-CMOS varactor design and measurement, device-level balanced varactor simulations, and parametric circuit evaluation based on measured device characteristics. Copyright © 2006 Howard Chan et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

1.

INTRODUCTION

Variable capacitors can play a very rich role in radio-frequency (RF) transceivers. In this paper we examine their use in two key front-end functions: amplification and frequency control. Parametric amplification, a relatively uncommon technique, is promoted in this paper. Improvements to this method are proposed by the incorporation of customized MOS varactors in place of the traditional junction varactor. Also, we discuss modifications to the MOS varactor in the context of its traditional role as a frequency control element. Anticipating a growing problem with interference between IC elements sharing one substrate, a four-terminal differential structure intended to desensitize voltage-controlled oscillators (VCOs) to large extrinsic noise variations is described. The paper is organized as follows. First a narrow outline of the history and status of parametric amplification is given in Section 2. A more detailed discussion of parametric circuit operation, improvements, and possible incorporation in a front-end transceiver is discussed in Section 3. Since the varactor constitutes the heart of parametric systems, Section 4 outlines the key integrated varactor structures, compares them based on two key merit figures, and introduces potential device-level augmentations. In Section 5 we return to parametric circuits and, with the results of Section 4, estimate the performance possibilities for an integrated setting. Frequency control, the second key topic of this report, is discussed in Section 6. This is approached from the

device level, where the advantage and limitations of employing a modified common-mode rejection varactor structure in a voltage-controlled oscillator (VCO) are discussed. 2.

PARAMETRIC CONVERSION: HISTORICAL REMARKS

Parametric circuits closely tie frequency conversion to amplification and therefore can seamlessly account for the mixing function of front ends as well. We broadly refer to them as parametric converters in this work. They are primarily known for their low-noise behavior and ability to operate at high frequencies. As implied by its name, parametric conversion involves the modulation of a system’s parameters as in the damped oscillatory equation below: 



x¨ + γx˙ + ω02 1 + p(t) x = 0.

(1)

Given a pumping disturbance at twice the oscillator’s natural frequency, 



p(t) = A p sin 2ω0 t ,

(2)

A subharmonic (relative to the pump) response x(t) = As eαt sin ω0 t

(3)

2

EURASIP Journal on Wireless Communications and Networking

can be solicited where α ranges between positive and negative values depending on the oscillator damping and the strength of the pumping signal. It is commonly acknowledged that such sustained parametric oscillations were first observed by Michael Faraday. In 1831 he reported the rise of subharmonic oscillation as part of experiments on acoustically pumped Chladni plates [1]. In 1957, following suggestions by Suhl [2] and Weiss [3], he reported the realization of an experimental solid-state microwave amplifier exploiting the parametric principle. Notable among a large number of intermediate contributions is Hartley’s work on electromechanical parametric amplifiers [4, 5] and Barrow’s fully active parametric vacuum tube implementation [6]. This space has been a subject of interest in the MEMS arena for low-frequency, precision sensing applications such as atomic force microscopy [7, 8] where the low-noise properties of parametric systems are of particular benefit. However, the use of parametric amplification in terrestrial communication systems is extremely rare. Recently, a discrete time parametric circuit in a 0.25 μm-CMOS technology was reported [9]. The circuit took particular advantage of the three-terminal inversion mode MOS varactor, but focused on low-frequency applications in the 100 kHz range. The absence of parametric converters from the communications mainstream is mainly due to the superior utility of transistor-based circuits for “low-” frequency commercial applications. Since the performance of parametric circuits is less dependent on the lateral dimensions (and hence delay) of their components, a key advantage of this approach is its ability to operate at higher frequencies early in the technology life cycle. However, improvements in transistor technology steadily encroached on the high-frequency reserve of parametric circuits thus marginalizing this advantage. Since more remote regions of the spectrum were better accommodated by maser and laser amplifiers, a loss of interest in the parametric circuit approach followed. Today, as personal commercial communications applications migrate to more exotic frequency domains, a niche for the parametric circuit may resurface. This may especially be the case for low-profile millimeter wave electronics intended for dense sensor or distributed network applications. Size and power constraints exclude many of today’s molecular amplifiers (although integration progress has been substantial [10]) from consideration while performance, power, and approaching physical limits have relegated millimeter wave applications to the domain of expensive IC technologies. 3.

PARAMETRIC CONVERSION: TECHNICAL REMARKS

Conventional electronic transistor amplifiers operate by using a small signal to modulate the resistance of a switch that, in turn, mediates the coupling between a large DC supply and a load. Amplification is achieved because the coupling is proportional to the small input signal and is efficient because, ideally, the supply does not influence the modulated resistance. Alternatively, parametric amplifiers utilize a nonlinear reactance (in this paper we consider only capacitive reactances) through which an AC supply “energizes” a small

signal. More specifically, a small signal deposits charge on a capacitor. An AC “pump” increases the potential energy of this charge by increasing the capacitance, the pumped charge is then siphoned off to a load. Immediately it is apparent that by foregoing resistive coupling such an amplification principle sidesteps, at least in part, thermal fluctuations and holds inherent noise behavior advantages. A handy “existance theorem” of sorts for parametric converters is available in the form of the Manley-Rowe relations [11] ∞ 

∞ 

m=0 n=−∞ ∞ 

n=0

mPm,n = 0, m fs + n f p

∞ 

nPm,n = 0. m fs + n f p m=−∞

(4)

The ideal circuit used to derive the Manley-Rowe relations is shown in Figure 1. These relations constrain the power, Pm,n , absorbed by a nonlinear capacitor at frequencies m fs + n f p that is driven by two sources operating at frequencies fs (the signal source) and f p (the pump source). The relations are fundamental in that they are based on the principle of energy conservation (zero total average power flowing into the capacitor) and are independent of the capacitance-voltage (CV) characteristics (aside from assuming no hysteresis in the voltage); the relations are limited in that they do not account for losses in the varactor which have a substantial impact on practical implementations. The raw circuit performance encapsulated by ManleyRowe relations needs to be constrained in order to realize practical functions like upconversion (signal at fs amplified and mixed to higher frequencies) or downconversion (signal at fs amplified and mixed to lower frequencies) or simply straight amplifiers (signal at fs amplified at fs ). The common way of doing this is to encase the capacitance in a multimode cavity. From a lumped circuit perspective, this means connecting the capacitance to some assembly of resonators. 3.1.

Upper-sideband upconverter

We imagine the nonlinear capacitor locked in a resonant configuration that allows power to flow only at frequencies fs , f p , and fu = fs + f p . For this scenario equation (4) is simplified to P P1,0 P P + 1,1 = s + u = 0, fs fs + f p fs fu

(5)

P p Pu P P0,1 + 1,1 = + = 0. fp fs + f p fp fu

(6)

As stated earlier the pump is our energy source in this circuit, it is responsible for a positive power flow, P p , into the capacitor. According to (6) this means that the power, Pu , at fu must be negative, hence flowing out of the capacitor and available

Howard Chan et al.

3

Es

fs

fp

+

+

fs + f p

fs

fp

fs + 2 f p

m fs + n f p

Ep

Figure 1: The ideal parametric converter used to derive the Manley-Rowe relations. Ideal impedance filters allow only a single tone to flow through any one branch.

to a load. From (5) the circuit has the operating power gain Gup =

fu Pu = . Ps fs

∞ 

n=−∞

Cn e j2πn f p t



(7)

A more physical description of USBUC operation may shed more light on its behavior. The potential energy of the charge that a small signal deposits on a capacitor can be increased by separating that charge. Work is needed to do this and this work is periodically supplied from a pump circuit. Under this condition, when a load extracts this charge from the capacitor, it will have access to higher energy carriers. Gain is achieved. However, the work used to energize the mediating capacitor increases the energy needed by the input signal to charge it again. Thus, the circuit is naturally at an advantage when pumping and energy extraction are done quickly compared to the dynamics of the signal input (i.e., when the capacitor signal is oversampled). Thus the higher the output frequency (hence pump), the greater the circuit gain. This configuration, the uppersideband upconverter (USBUC), is well suited for highfrequency transmission. For instance, under ideal conditions, converting a 6 MHz signal to a 60 GHz carrier promises a 40 dB operating power gain making the circuit more attractive for millimeter wave applications. Note that, under the ideal described by (5) and (6) (i.e., lossless varactor and perfect resonator), the gain is completely independent of the pumping power. Analysis and simulations of the impact wrought by varactor losses on circuit gain are presented in Section 5. Of course the maximum available output power is limited by the size of the input and pump signals. For a small input signal and fu  fs we have a maximum output power of approximately P p /2 hence an efficiency of 50%. As fs increases the efficiency improves, but the gain drops. Accounting for losses in the surrounding filter (cavity) network by itself does not directly influence the ideal gain prediction. Rather, as highlighted by Rowe [12], the bandwidth of the converter is compromised. Assuming that the pump’s action on the nonlinear varactor introduces a timevarying incremental capacitance between the USBUC’s fs and fu ports of Cpump (t) =

the bandwidth to signal-frequency ratio (γup / fs ) becomes [12]

(8)

γup C1  fu = 2 . fs C0 fs

(9)

Returning to the previous example, to accommodate a signal of 10 MHz bandwidth converted from a 6 MHz to a 60 GHz center frequency requires a C1 /C0 ratio of less than 1/80. This bodes extremely well for the pump. For a well-designed MOS varactor it is not unreasonable to expect a 50% variation around C0 , that is, assuming the common empirical MOS model we expect

CMOS = C0 +



3 C0 3C tanh vpump ≈ C0 + 0 vpump , 2 2 4

(10)

where the latter approximation is based on the assumption of a small pump voltage. This is confirmed by the small C1 /C0 requirements of our example. From (9) and (10), a peak-topeak pump voltage of only 16 mV is needed to sufficiently perturb the varactor so that a 10 MHz bandwidth is established. This must be tempered with the fact that in this case the pump needs to operate at 60 GHz which is not out of the question for production level technologies (albeit a significant stretch for CMOS) exploiting distributed operation [13], frequency doubling [14], or second-harmonic generation [15]. Further, it is possible to redesign the pumping scheme of the parametric converter to continue meeting the Manley-Rowe predictions while operating with a pump at lower frequencies. This is discussed in Section 3.3. The benefits available to the USBUC become serious impairments when considering this topology for a receiver’s downconversion block. The substantial gain available to the upconverter (7) becomes a tremendous loss as, naturally, fu  fs for downconverters. Fortunately, a large variety in parametric conversion topologies exists, some of which do allow for gain in the downconversion arrangement. One such topology is discussed presently. 3.2.

Lower-sideband downconverter

The lower-sideband downconverter (LSBDC) is one parametric topology capable of amplifying a signal mixed down to the intermediate frequency (IF) or baseband (BB). In this

4

EURASIP Journal on Wireless Communications and Networking

case, the converter’s cavity is aligned such that power only at fs (the RF signal), f p , and fd = f p − fs (the downconverter signal) can flow through the circuit. To obtain a low-frequency output, the constraints f p > fs (otherwise an upper-sideband downconverter is realized) and f p < 2 fs (otherwise a lower-sideband upconverter (LSBUC) is realized) must hold. Returning to the Manley-Rowe relations we get P1,0 P P P + 1,−1 = s − d = 0, fs fs − f p fs fd

(11)

P p Pd P−1,1 P0,1 + = + = 0. fp − fs + f p fp fd

(12)

Adding (11) and (12) results in P p Ps + =0 fp fs

(13)

which, given that the pump power flows into the circuit, implies that power emerges from the converter’s input (signal) port despite an input signal being fed into the receiver (e.g., from an antenna). Hence, the impedance of the LSBDC’s signal port is negative. Similarly, (12) states that the pump energy causes power to emerge from the downconversion port as well. Being related to the power emerging from the signal port (see (11)) this implies that the downconversion port impedance is also negative. The LSBDC doubles as a reflection amplifier. The operation of this circuit can be summarized as follows. The pump generates the highest frequency “signal” in the circuit. Thus, unlike the USBUC, on average it can couple power from the signal port (RF) to the downconversion port (IF) and vice versa. As with the USBUC, the power coupling and amplification is mitigated by work done by the pump in changing the varactor capacitance. Since the pump switches only slightly faster than the signal, it transfers a relatively small amount of the input power into the downconversion port’s IF frequency. However, being much higher than IF, the pump taps, amplifies, and converts a great deal of the IF back to RF (as predicted by (11)). Part of the larger input signal is then tapped once again by the pump and fed into the downconversion port. A positive feedback is established and the circuit functions as a regenerative amplifier. Thus the pump power emerges as RF and IF frequencies from the respective ports which now have a negative input resistance. The more power that is pumped into the circuit is, the higher the quality factor, Q, of the RF and IF modes is. Thinking of the input as a forcing signal on these modes we can automatically see that the higher the Q, the higher the signal gain, but the lower the bandwidth. Nonetheless, for signals centered around millimeterwave carriers, the LSBDC topology has a lot of relative bandwidth performance to sacrifice. What is a drawback to this circuit, however, is that an excess of pump power leads to instabilities (overcompensation of loss) and, simultaneously, a greater sensitivity to component variations (thus increasing the likelihood of instability). However, the advantage remains the potentially low-noise behavior about which the Manley-Rowe relations say nothing. We return to this in Section 5.

USBUC ωu

ωs

BB

RF ωp

Figure 2: A simple transmit chain employing the USBUC.

3.3.

Parametric transmit and receive chains

How can parametric converters be assembled into the transceiver chain? Since they combine oscillator, mixer, and amplifier functions under essentially one circuit, they hold the potential to form the basis for a diverse set of radio systems. Perhaps the most straightforward application is the use of an USBUC as a low-voltage upconverter of BB or IF signals to millimeter RF. For minimal complexity and power consumption, the design in Figure 2 can be used. This diagram suggests interfacing the USBUC directly to the antenna which, if the antenna is sufficiently narrowband, can serve as the upper-sideband bandpass filter. Employing a standard twoterminal varactor structure in this topology will impose extra gain limiting—significant upconverted signal amplitudes can induce lower-sideband signals to flow (i.e., ω p − ωs ) thus returning power back to the input source. A simple alternative is to use the USBUC as an upconverting mixer and preamplifier and leave the final millimeter wave amplification to a dedicated high-frequency (and high-cost) power amplifier. Alternatively, a double-balanced varactor structure (as described in Section 4.3 in the context of VCO frequency control) can be used in an attempt to desensitize the varactor capacitance to variations in the upconverted signal frequency. Another transmitter topology shown in Figure 3 incorporates a degenerate local oscillator (LO) in a heterodyne USBUC architecture. In this case, the gain of the USBUC is distributed over several stages. The benefit of such a partition is reaped by the pump which can potentially be generated in a staged fashion as well. In Figure 3 the staged pump is built out of degenerate parametric converters. In degenerate converters, the signal (i.e., the LO) acts simultaneously as the input and the pump. A self-mixing occurs which naturally results in a signal at twice the input frequency. As shown, two such stages attached back-to-back can produce a signal at four times the driving pump frequency (with the need of a high power output at ω p ) and be combined with a multistage USBUC to gradually upconvert a signal from ωs to 7ω p + ωs . Since parametric circuits couple power from low to high frequencies, the receiver’s downconversion function obviously poses a problem. As already described, the LSBDC gets around this by employing positive feedback which can give substantial gain at the expense of sensitivity. A possible receiver topology employing a LSBDC is shown in Figure 4. Since the circuit functions as a reflection amplifier for both RF and IF frequencies, a circulator is included to prevent

Howard Chan et al.

5

ω p + ωs

ωs

BB

USBUC 3ω p + ωs

7ω p + ωs RF

LO ωp

2ω p

4ω p

Degenerate

Figure 3: Multistage USBUC transmitter with degenerate pump.

LSBDC ωs RF

ωd

IF ADC

ωs ωp ADC

more abrupt MOS CV characteristics (compared to the junction varactor) can be of substantial benefit. For example, imagine a varactor pumped such that part of its Fourier series expansion from (8) is CA (t) = · · · + C−2 e− j2ω p t + C−1 e− jω p t + C0 + C1 e jω p t + C2 e j2ω p t + · · · . (14)

Figure 4: Receive chain using a LSBDC as a mixer and amplifier.

Another varactor, CB , pumped 180◦ out of phase relative to CA can be described with re-radiation and help maintain stability. A number of options are available even within the basic LSBDC receiver. Most simply it can be treated as a low-noise amplifier (LNA) and the amplified RF signal tapped out of the circulator to the remainder of the radio. In this case we benefit simply from the large gain and low-noise performance of the parametric converter. Any standard downconversion architecture or subsampling techniques can be employed afterwards. Compared to integrated transistor LNAs operating in the microwave region this benefit is marginal at best. However, at millimeter wave frequencies the improvements for amplification, noise, and power consumption become marked (at least compared to production-level CMOS technology). Using the downconversion port is another possibility, in this case taking advantage of the LSBDC’s conversion properties alongside its low-noise performance. The difficulty in this case is gain, as the downconversion gain is increased, the regenerative design becomes difficult to stabilize under practical conditions. An obvious issue with parametric converters is the high pump frequency needed to transfer power. As a result, a number of high-frequency pump generation and conversion techniques have already been mentioned. Another approach is to reconfigure the varactor structure for subharmonic pumping. Subharmonic pumping refers to an arrangement in which a certain pumping frequency transfers energy at the same rate as would a higher pumping frequency. The subharmonic pumping suggestion does not pose an immediate violation of the Manley-Rowe relations. Rather, one means of its realization is to simply utilize one of the higher pumped capacitance harmonics [16]. Herein, the

CB (t) = · · · + C−2 e− j2(ω p t+π) + C−1 e− j(ω p t+π) + C0 + C1 e j(ω p t+π) + C2 e j2(ω p t+π) + · · · .

(15)

Combining CA and CB , CA (t) + CB (t) = · · · + C−2 e− j2ω p t + 2C0 + C2 e j2ω p t + · · · , (16) leads to a net capacitance variation occurring at twice the actual pump rate. The schematic of a differentially driven subharmonic scheme based on this approach is shown in Figure 5. For subharmonic pumping to actually work here the varactors, CA and CB , must both have the same terminal (either gate or source) connected to the circuit proper. Aside from exciting the second harmonic, the differential pumping scheme allows the circuit to operate without a dedicated pump filter despite the use of two-terminal varactors. Alternatively, if the orientation of one varactor is flipped (i.e., terminal connections reversed or a complementary structure used) the subharmonic pumping effect is removed. The benefit of this connection, however, is the isolation of any pump frequencies from the signal and output ports allowing the filtering at these terminals to be significantly relaxed. A more extreme attempt at subharmonic pumping employing a four-phase excitation scheme is sketched in Figure 6. In this case a ring oscillator (an injection locked oscillator can be used for better purity) generates differential in-phase and quadrature signals. Altogether four pump signals offset by 90◦ are available. Each pumping signal is sent to a separate varactor with CV characteristics identical to the other three. Given sufficiently nonlinear (i.e., abrupt) CV characteristics

6

EURASIP Journal on Wireless Communications and Networking VG

Differential pump

VS

+ CA Signal source ωs

+

ωu n+

+

n+

CB

n-well

Figure 5: A differential subharmonic pumping scheme. Figure 7: A sketch of an n-type (referring to the body doping) accumulation-mode varactor’s cross-section.

90Æ

ωu

180Æ

270Æ

ωs Signal source

0Æ

Figure 6: A possible four-phase subharmonic pumping scheme.

the net capacitance seen between the signal (ωs ) and upconversion (ωu ) terminals of the varactor will vary at four times the injected pumping frequency. Of course, at this harmonic, a large degradation in capacitance can be expected compromising the benefit of low pumping frequencies. 4.

began to accommodate the accumulation-mode varactor [17, 18] (Figure 7). This simplified the device bias scheme as compared to the more common inversion-mode varactor and simultaneously lowered its resistive losses and parasitic contributions. As a frequency tuning element the advantages of the accumulation-mode varactor compared to the junction diode were clear, a large Cmax /Cmin ratio, an abrupt capacitive transition implying only the need for low tuning voltages, an isolated bias scheme, and acceptable Q. Optimization of these characteristics for LC-VCOs are straightforward: one must increase the Cmax /Cmin , and reduce resistive losses. For parametric circuits a more detailed assessment is necessary. First, unlike Manley-Rowe, a more accurate analysis of parametric circuit behavior must account for losses in the varactor. To this end a rough but physically realistic pumped varactor model employs a nonlinear capacitance in series with a resistance, Rs . As emphasized by Penfield and Rafuse [19] this varactor model sidesteps the difficulties and inaccuracies that emerge when a parallel RC equivalent is used or when the series resistance is incorporated into source and load impedances. The terminal characteristics of this physically motivated model are best described with the relation

v(t) =

VARACTOR STRUCTURES

Since the late 1950’s the junction diode has served as the de facto standard for all electronic parametric amplifiers. However, in parametric structures, and for oscillator frequency control, the junction diode is generally inferior to MOS varactor structures. Since the most vigorous research on electronic parametric circuits predates the rise of MOS technology, they have only sporadically been considered in the context of modern electronic technologies (and their applications); [9] is a rare example. In this section we look closer at the key varactor characteristics and design options for RF frequency control and parametric conversion. 4.1. Elastance model An important advance in customized MOS varactor technology for RF applications was taken when CMOS processes

S(t)i(t)dt + Rs (t)i(t).

(17)

This equation directly catalogues the influence of the pump voltage on the varactor as a whole. However, it contains a relatively obscure varactor measure, the incremental elastance, S(t).1 A rough approximation of a MOS varactor elastance per unit area is given by 



S VGS =





Qsd VGS 1 + , es Nd Cox

(18)

where Cox is the oxide capacitance, e is the electronic charge,

s is the permittivity of the semiconductor, Nd is the donor

1

For the remainder of the paper we refer to S(t) as simply the elastance, with the incremental properties of this value remaining implicit. As with the capacitance of nonlinear devices, practical measurement techniques allow the extraction of only incremental properties.

Howard Chan et al.

7

doping in the semiconductor (a uniformly doped n-type accumulation-mode varactor is assumed), and Qsd is the depletion charge in the semiconductor body. The depletion charge itself is modeled semi-empirically with e s Qsd = Cox Nd





4V 1 + MOS −1 , γ2

(19)

where γ is the device body factor and VMOS =

1 2

 

VGS − VFB

2



+ δ − VGS − VFB

 

.

(20)

The above follows a modeling technique reported in [20] and, as in that work, incorporates a small smoothing factor, δ. This correction is used since the transition from full accumulation to flat-band is not rigorously accounted for here. With such factors present it is best to consider this model as a rough design guide. A detailed account of the varactor device physics in compact model form is described in [21] for example. The value of the simple model described here lies in its direct exposure of the relations between performance and device characteristics. Section 4.2 discusses this, along with device losses, in detail. A comparison of this approximation to the normalized CV and SV characteristics extracted from a full charge-based analysis [22] as well as a simple tanh curve fit is presented in Figure 8. As shown, the tanh curve, a popular approach in empirical compact CV models, underestimates the elastance in depletion. We return to this point in Section 4.2. 4.2. Figures of merit The elastance characteristics must be considered along with device losses in estimating the impact of integrated MOS technology on parametric performance. Penfiled and Rafuse [19] highlighted two figures of merit, the cutoff frequency fc =

Smax − Smin 2πRs

(21)

|Sn | . Smax − Smin

(22)

and the modulation ratio mn =

The cutoff frequency, which we can express in more familiar varactor measures as C − Cmin fc = max , (23) 2πRs Cmax Cmin reflects only the influence that device properties bear on the circuit. Ideally, fc marks the maximum frequency at which it is worth pumping the capacitor. Conversely, the modulation ratio encompasses several contributions. The numerator, |Sn |, indicates the size of the elastance harmonic at the pumping frequency n· f p . That is, assuming small-signal conditions, we can treat the elastance as a linear time-varying component controlled by the pump S(t) =

∞ 

n=−∞

Sn e j2πn f p t .

(24)

This is the elastance analog to (8). The elastance harmonics are influenced by three things: the bias of the pumping signal, the amplitude of the pumping signal, and the steepness of the varactor’s elastance characteristics. The steeper the SV curve is, the more efficient the pump is in relaying its energy to the varactor. As shown in (18) and (19) a large impact on the abruptness of the elastance characteristic can be made by reducing the channel doping. This necessarily increases the series losses, but at a rate proportional to Nd , while the SV slope increases with Nd2 . Similarly, we can see from (19) that a decrease in the gate capacitance per unit area, Cox , also contributes to an improvement in the SV slope. This also comes with the benefit of allowing larger pumping signals to be applied across the gate oxide. These relationships run in a direction counter to the changes employed in scaling MOS devices. Nonetheless the variety present in most modern MOS technologies presents some room for optimization. For instance, many CMOS processes offer devices of various oxide thickness and channel doping. A plot of the SV characteristics extracted from Sparameter measurements on accumulation-mode devices in a 0.13 μm-CMOS technology with varying channel doping and oxide thickness is shown in Figure 9. In this case only devices with a marginal difference in oxide thickness were examined. As expected, a lower channel doping results in a steeper SV characteristic. The measured 4-to-1 ratio between Smax and Smin is about 2.5 times greater than that available from a junction diode. The two channel doping levels (nominal and high) are obtained by employing threshold adjust implants intended for the variety of NMOS and PMOS devices offered in the technology. Unfortunately, a fourth experiment employing one of the available counterdoping implants and intended to have the lowest channel doping was not correctly processed at the foundry. This, correctly combined with the thick-oxide option available in most CMOS technologies, constitutes the most direct approach to device customization for parametric circuit applications. Of note in the measurement results is the manner in which the elastance characteristic saturates in the depletion region. This is a characteristic encompassed by the tanh fit example included in Figure 8 but not the basic model of (18). The disparity between the predicted and measured elastance characteristics at large depletion bias can be traced to the fact that the varactor measurements were done with a small-signal, high-frequency (5 GHz) perturbation atop a slowly stepped bias—a common high-frequency CV extraction technique [23]. Such a set-up allows minority charge to respond to the bias settings thus preventing the onset of deep depletion as naturally included by the basic model. However, in parametric circuit applications we can expect a large-signal, high-frequency pump voltage to continuously excite the MOS varactor. Thus, the equilibrium bias conditions present during measurement hardly apply for pumped varactors. This supports the elastance predictions of the basic varactor model, but a convincing answer requires an analysis beyond the scope of this paper. As highlighted by the merit relations, SV performance alone is not a sufficient device selection criterion. Careful

8

EURASIP Journal on Wireless Communications and Networking 1

5

0.9

4.5

0.8 4 0.7 3.5 S/Sox

C/Cox

0.6 0.5 0.4

3 2.5

0.3 2 0.2 1.5

0.1 0

1

0.5 VGB

0 VFB (V)

0.5

1

1

1

0.5 VGB

Approximate model Full charge model tanh fit

0 VFB (V)

0.5

1

Approximate model Full charge model tanh fit

(a) Capacitance-voltage characteristics

(b) Elastance-voltage characteristics

Figure 8: Comparing the rough semi-empirical model to a complete charge-based description and a tanh fit.

1.6

Elastance (1/pF)

1.4 1.2 1 0.8 0.6 0.4

1

0.5

0 VGS (V)

0.5

1

Nominal doping and tox Nominal doping, low tox High doping, nominal tox

Figure 9: Elastance measurements for accumulation-mode varactors with varying degrees of channel doping in a 0.13 μm-CMOS technology.

consideration must be given to the reduction of series losses as attested by (23). For designers, with little control over the varactor’s physical characteristics, layout becomes paramount here. Without considering special layout techniques (such as differential excitation [24]), four controls are available: gate length (Lg ), gate width (Wg ), finger number (N f ), and number of stripes/segments (Ns ). These combine

to give an active varactor area of Lg · Wg · N f · Ns . To clarify, a varactor consists of Ns stripes in parallel, each containing N f fingers, in turn, each finger has dimensions Wg and Lg . We must consider what arrangement of these terms maximizes fc . This requires finding the right balance between layout influence on series resistance and capacitance properties. The series resistance can be divided into two main contributors, one is a constant value and is associated with the silicided poly gate, contacts, and via resistance on the terminals. The other contributor is associated with the channel material and is bias, doping, and frequency dependent. For the accumulation-mode varactor with one finger, its series RC components can be modeled as in Figure 10, where Rcg and Rcsd are the contact and via resistances on the poly gate and n+ diffusion pickups (source/drain), respectively, and Rg is the gate polysilicon resistance. Underneath the gate, the channel resistance is denoted by Rch , while Rw is the resistance of the n+ diffusion bulk pickups and the well. Cvar is the equivalent series capacitance of each finger. The model of the varactor with multiple fingers is shown in Figure 11, where Rs f g and Rs f sd are the series resistance between two fingers. For the gate resistance, if the gate poly of each finger is joined from both sides of source/drain, the equivalent poly resistance of one finger is Rg =

1 Wg · · Rg −sh , 12 Lg

(25)

where Rg −sh is the gate’s sheet resistance. On the other hand, for the channel and well resistance we have Rch , Rw ∝

Lg · Rch,w−sh . Wg

(26)

Howard Chan et al.

9 Rch

Gate

Rcg

Rg

Cvar

Rcsd

S/D

Rw

Figure 10: Model of a single-finger varactor.

Gate Rcg

Rg

Cvar

Rcsd

Rs f sd

Rw Rch Rs f g

Rcg

. ..

Nf

Ns

Cmax (f F)

Cmin (f F)

Rs (Ω)

fc (GHz)

180 60 30 15 5

1 3 6 12 36

477.8 481.5 481.8 482.3 483.5

187.3 188.1 188.3 188.7 190

13.77 2.429 0.8025 0.508 1.275

32.57 212.2 641.5 1011 399

S/D Rch

Rs f g

Table 1: Cutoff frequencies for varactor with Wg = 1 μm, Lg = 0.24 μm, and area = 43.2 μm2 .

Rg

Cvar

Rcsd

Rw

Rs f sd

. ..

Figure 11: Model of a parallel multiple-finger varactor.

Being lower doped and unsilicided, the sheet resistance of the well and bulk, Rch,w−sh , is greater than that of the polysilicon. This suggests that one would use the minimum channel length to reduce the body contribution to the series resistance. However, due to their inverse dependence on finger dimensions some tradeoff between the influence of (25) and (26) on the series resistance is present. This tradeoff affects the setting for Wg and Lg , but it is not the only consideration. As shown in (23) we want to maximize Cmax , minimize Cmin , and minimize Rs . Somewhat arbitrarily choosing a minimum practical value of Cmin = 100 fF (in anticipation of parasitic effects and process variations) we are left to consider how Lg , Wg , N f , and Ns influence the remaining two characteristics, obviously this complicates selection based purely on an Rg -Rch tradeoff. For instance, minimizing Lg · Wg maximizes the N f · Ns product and therefore reduces Rs , but at the cost of increasing the relative parasitic capacitance contribution and hence a reduction in Cmax − Cmin . Another important consideration is the contact and interconnect resistance introduced between fingers (Rs f g and Rs f sd in Figure 11) and stripes. This is often ignored when assessing device resistance, but can certainly be influential. With Rs f g and Rs f sd the equivalent resistance will not be reduced simply as a function of 1/N f . As N f is increased the series resistance will eventually saturate due to the contributions of the interfinger connections, Rs f g and Rs f sd . Getting a sense of how the characteristics Lg , Wg , N f , and Ns influence fc is greatly aided by the availability of verilogA based compact models such as the one described in [21]. Since these models account for both physical and layout characteristics a broad comparison between designs can

Table 2: Cutoff frequencies for varactor with Wg = 1.41 μm, Lg = 0.34 μm, and area = 43.2 μm2 . Nf

Ns

Cmax (f F)

Cmin (f F)

Rs (Ω)

fc (GHz)

90 45 30 15 5

1 2 3 5 18

475.8 476.3 476.5 476.8 477.5

147.5 147.8 147.8 148.1 149

7.281 2.777 1.538 0.7094 0.9085

102.2 267.5 482.8 1045 808.9

Table 3: Cutoff frequencies for varactor with Wg = 2 μm, Lg = 0.48 μm, and area = 43.2 μm2 . Nf

Ns

Cmax (f F)

Cmin (f F)

Rs (Ω)

fc (GHz)

45 5 15

1 9 3

475.8 476.3 477.5

147.5 122.1 123.5

4.359 0.9787 1.266

222.8 982.9 754.4

be made. Employing empirically based compact models the fc for a variety of accumulation-mode n-type varactors (excited in a single-ended manner) is shown in Tables 1–3. The total active area (Lg · Wg · N f · Ns = 43.2 μm2 ) is the only value that all designs have in common. It is chosen such that Cmin remains above 100 fF over the relevant region of operation (VGS ranges from −1 V to 1 V). Table 1 summarizes the results for varactors consisting of minimum unit area (i.e., Wg · Lg ) elements, Table 2 shows the results for devices composed of twice the minimum unit area, and Table 3 summarizes the characteristics of varactors composed of four times minimum unit area elements. Note that all Rs have been calculated for 5 GHz excitations. A layout dependent self-resonance frequency could not be extracted as the model did not account for inductive parasitics although it should be noted that self-resonant frequencies do not necessarily pose a problem for parametric circuits. The self-resonant frequency can be exploited as one of the modes of interest in the parametric circuit. The fc values shown are certainly optimistic as the compact models do not account for the effects that would limit device performance at such frequencies, nevertheless they are useful as a relative measure of the best device type. Judging by the fc results, it is best to use an intermediate unit area that ably juggles two conflicting characteristics: parasitic capacitance and series resistance. For a given total area, as the unit

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EURASIP Journal on Wireless Communications and Networking 2.5

1200 1000

2

1.5 C (pF)

fc (GHz)

800 600

1 400 0.5 200 0

0 0

5

10

15

20 Ns

25

30

35

40

area shrinks, more devices in parallel imply a smaller total resistance. As can be seen in all cases, this is best achieved by keeping N f and Ns on the same order. Unfortunately, the capacitance of small unit areas contains a higher relative proportion of parasitic capacitance. This lowers Cmax − Cmin which ends up hurting the fc . Attempts to get around this by increasing the unit area will be frustrated by an increase in series resistance simply due to a decrease in the parallel connection count. The simulated cutoff frequencies associated with these varactors are plotted in Figure 12 as a function of stripe count. As can be seen, fc is relatively forgiving of unit size, but quite sensitive to N f and Ns distributions. Measured results are available to double-check the CV characteristics of the scalable varactor model. The experimental varactor design has unit widths and lengths of 5 μm and 0.42 μm, respectively, which are arranged into Ns = 5 parallel stripes of N f = 20 gate fingers each. In Figure 13, the CV curve obtained from the model is plotted alongside the CV data obtained from a high-frequency (5 GHz) S-parameter characterization of the varactor. It is observed that the CV characteristic of the fabricated device matches very closely with the scalable model (at the frequency of extraction). We will attempt to tailor this varactor design for parametric circuits by changing the number of stripes from 5 to 1. The implications of this change on the device characteristics and USBUC and LSBDC are explored in detail in Section 5. Even though reducing Ns will shift the CV curve down and decrease the Cmax − Cmin (as shown in Figure 13), Cmin has also been reduced thus increasing fc . The large change in capacitance characteristics from Ns = 5 to Ns = 1 affects the performance quality of the parametric converter but not the substance of its operation, unlike, for example, that of a VCO, whose center frequency and tuning range would be severely

0.5

0 VGS (V)

0.5

1

Ns = 5: model Ns = 5: measurement Ns = 1: model

Wg = 1 μm, Lg = 0.24 μm Wg = 1.41 μm, Lg = 0.34 μm Wg = 2 μm, Lg = 0.48 μm

Figure 12: Plot of varactor cutoff frequencies versus number of stripes for a 43.2 μm2 (total active area) varactor.

1

Figure 13: Comparison of measurement results to compact model predictions.

+ VG+

+ Vtune

VCM

VG +

Vtune

Figure 14: Schematic of common-mode cancellation varactor.

impacted. The only requirement imposed in this work is that Cmin exceed 100 fF, which has been satisfied. 4.3.

Composite structures

Besides refining layout, useful varactor customization can be achieved by connecting devices for optimal excitation. An example of this is the work reported in [24] where varactors subject to differential excitation (e.g., in a differential VCO) profit from a virtual ground connection which reduces the effective series losses. Another possibility is the common-mode rejection architecture [25]. In this case, varactors are arranged such that they respond symmetrically to differential excitations, but in an antisymmetrical manner to common-mode excitations thus damping the latter’s influence. This can be useful for both parametric converters (allowing large signal operation) and VCOs (removal of supply disturbances). A discussion of the latter is given in Section 6. A schematic of the proposed varactor circuit is shown in Figure 14. In effect, this arrangement resembles the basic

Howard Chan et al.

11 VDD

+ Vtune

n+

p+

VG+

+ Vtune

p+

VG

+ Vtune

VDD

Vtune

p+

n+

n+

VG+

Vtune

VG

Vtune

n+

p-well

n+

n-well

Deep n-well p-substrate

Figure 15: A sketch of the cross-section of a common-mode-cancellation accumulation mode varactor. Compare this to the schematic of this “device” rendered in Figure 14.

5.

2.8 2.6 2.4 Capacitance (fF/μm)

antiparallel connection (i.e., a pair of two-terminal asymmetrical devices connected in parallel, but with opposite terminal orientations) [26]; in practice, it isolates the differential VG node from the substrate losses. Isolating sensitive nodes from the substrate is much less of a concern in the case of an SOI technology, but it is essential in a CMOS technology where such a load can severely degrade the tank Q in LC-VCOs. A common-mode rejection varactor (CMRV) circuit, consisting of n-type and p-type accumulation-mode varactors, can be realized in any CMOS technology with a deep n-well. The deep n-well doping is used to define an isolated p-well and hence the p-type accumulation mode varactor needed to complement the n-type varactor. Further, it is possible that such a device can be tightly integrated into one composite structure as illustrated in Figure 15. As sketched, the device also takes advantage of a differential excitation layout to help reduce series losses. At present, CMOS processes commonly include n-type accumulation-mode devices, however it is uncommon to find the p-type corollary needed in the CMRV. To approximate the properties of such a pair, the 2D device simulator, MEDICI, is employed. The construction of the hypothetical p-type device is guided by the approximated doping levels of an n-type varactor available in a 0.13 μm-CMOS technology. The doping levels are simply mirrored. The CV characteristics obtained for the n-type and ptype accumulation mode varactors using MEDICI are shown in Figure 16. Apparently, a relatively antisymmetric response is possible if matched doping levels are used in the two devices. Simulator mesh size limits required a separate analysis for each varactor flavour, nonetheless the results are expected to be indicative of the fully integrated device operation. The benefits that such a device brings to VCO phase noise behavior in the presence of extrinsic disturbances are discussed in Section 6.

2.2 2 1.8 1.6 1.4 1.2 1

1

0.8

0.6

0.4

0.2

0 0.2 VGS (V)

0.4

0.6

0.8

1

n-type p-type

Figure 16: Comparison of MEDICI simulated CV characteristics of matched n-type and p-type varactors.

ZG

Filtered and pumped varactor two port

vp

vG

Zo Rs

Figure 17: The upper-sideband upconverter represented as a two port with ideal filters and series loss, Rs only in the varactor.

PARAMETRIC CIRCUIT SIMULATIONS

5.1. USBUC Although useful as a general guide, the predictions of the Manley-Rowe relations apply only to the case of a lossless reactance. Penfiled and Rafuse [19] emphasized the need to account for series varactor losses when evaluating parametric circuit performance. Following this work, the available gain

of an USBUC treated as a two port (see Figure 17) is given by

1 ωs = Ga m1 ωc

2  

2

ZG + Rs − jS0 /ωs  ω R + RG + s s Rs RG ωu RG

(27)

assuming that only (angular) frequencies ωs , ω p , and ωu = ωs + ω p are allowed to exist in the cavity. The influence of

12

EURASIP Journal on Wireless Communications and Networking

the cutoff frequency (in rad/s as ωc ) and the modulation index (m1 ) is clearly seen here. Expecting the USBUC to be used in a millimeter wave communicator transmit chain, we are most interested in the conditions necessary for maximum gain. From (27) we find that maximum available gain is

Ga,max

m1 ωc = ωs

2

⎛ ⎜ · ⎝1 +

   m ω 2 1 c

ωs ωu

⎞−2 ⎟ + 1⎠

(28)

when the jS0 /ωs term is resonated out and the generator resistance is set to RG = Rs

   m ω 2 1 c

ωs ωu

+ 1.

Table 4: Relevant varactor measurements with Vdc = −200 mV and V p = 300 mV (peak). S0 (×109 /F)

S1 (×109 /F)

Rs (Ω)

m1 ωc (×109 rad/s)

Ns = 5, Measured

957.2

211.9

1.1

192.7

Ns = 5, Model

987.7

228.0

1.032

220.9

Ns = 1, Model

4938

1140

2.359

483.3

Design

(29)

The varactor structures described earlier (Figure 13) are now used to get a sense of the performance attainable by the USBUC. The simulated figures of merit for these devices are summarized in Table 4. A DC point (−200 mV) is chosen for the pump signal such that the device is biased evenly between Smax and Smin . Also, the figures are extracted for a sinusoidal pump signal of 300 mV peak amplitude applied directly across the varactor (i.e., −6.5 dBm from a matched 50 Ω pumping source). This prevents the generation of higher-order harmonics which, under the circuit conditions considered here, do not contribute any useful power gain and may actually decrease it. The simulation results for an USBUC that amplifies and converts a 1 GHz signal to a 60 GHz frequency are shown in Table 5. A number of conditions are examined and, for easy reference, compared to theoretical calculations of available gain. The results are determined for no input match ((27) with ZG = 50 Ω), input conjugate match (ZG∗ = Rs − jS0 /ωs ), and gain optimization “match” (28). For the first two varactor simulations (Ns = 5 measured and modeled), we see that the gain is well below that predicted by the Manley-Rowe relations. We can attribute this to the fact that our upper-sideband frequency is greater than 0.427 (m1 ωc )2 /ωs (a design variable for USBUCs, indicating the signal frequency at which the converter’s available power gain begins to saturate [19]), in the case of the five-stripe varactor (i.e., measured and modeled). Therefore, this varactor is an unsuitable choice for the design we have presented, since we are pumping it at too high a frequency. The onestripe varactor, with a composite merit figure (m1 ωc ) more than twice as great does not exceed the above condition and comes within 15% of the Manley-Rowe prediction.

Table 5: Simulated USBUC power gain. Design

Condition

ZG [Ω]

Ga (theory)

Ga (sim)

Ns = 5 Measured —

No match Conjugate Gain opt.

50 50 + j152.3 4.49 + j152.3

1.94 14.81 36.93

1.91 14.65 36.26

Ns = 5 Model —

No match Conjugate Gain opt.

50 50 + j157.2 4.8 + j157.2

2.25 17.29 38.75

2.21 17.08 38.61

Ns = 1 Model —

No match Conjugate Gain opt.

50 50 + j785.9 23.5 + j785.9

1.1 46.77 49.07

1.09 46.57 48.94

it is necessary that ωs ωd < (m1 ωc )2 . In general, as long as ωs < m1 ωc , we will have a negative gain. Assuming that one LSBDC will do the job of an entire receiver front end (i.e., LNA, mixer, oscillator) its noise behavior becomes an important concern. The noise temperature of the LSBDC is given by 

T = Td

Rs ωs + F −1= RG m1 ωc

Once again, following [19], for the LSBDC, considering varactor losses, the exchangeable gain becomes

2  

 2  Z ∗ + Rs + jS0 /ωs 2 G

Rs RG

−

ωs Rs + RG . ωd RG (30)

From this equation, we can see that it is possible for the available gain to be negative. However, for this to be possible,

2 

ZG∗ + Rs + jS0 /ωs  Rs RG

,

(31)

where Td is the varactor temperature. If we are planning on implementing this receiver system with an on-chip antenna, we can expect the antenna and the varactor to be roughly the same temperature. Thus the single-sideband noise factor will be 

5.2. LSBDC

1 ωs = Ga m1 ωc

Rs ωs + RG m1 ωc

2  

2 

ZG∗ + Rs + jS0 /ωs  Rs RG

.

(32)

As in the USBUC, the first step we can do to improve gain and noise performance is to perform a reactance match, which is done by letting XG = S0 /ωs . As a result, the improved noise factor becomes 

Rs ωs F −1= + RG m1 ωc

2 

RG + Rs Rs RG

2 

.

(33)

Howard Chan et al.

13 Table 6: Simulated LSBDC performance.

Condition

ZG (Ω)

Zout (theory)

Zout (sim)

NF (dB)

Ns = 5 Measured

No match Reactive match Noise opt.

50 50 + j2.54 1.24 + j2.54

0.73 − j152.4 0.73 − j152.3 −7.02 − j152.3

0.73 − j144.4 0.73 − j144.4 −6.84 − j143.8

22.63 22.62 12.37

Ns = 5 Model

No match Reactive match Noise opt.

50 50 + j2.62 1.20 + j2.62

0.603 − j157.2 0.602 − j157.2 −8.82 − j157.2

0.609 − j148.3 0.609 − j148.3 −3.03 − j143.5

21.71 21.70 11.33

No match Reactive match Noise opt.

50 50 + j13.1 3.8 + j13.1

−7.5 − j788.4

−7.3 − j737.5

Ns = 1 Model

−8.1 − j785.9

−7.9 − j739.9

−86.22 − j785.9

−84.8 − j740

12.06 11.82 6.23

No match Reactive match 1 Reactive match 2 Reactive match 3 Noise opt.

50 25 + j9.7 20 + j9.7 15 + j9.7 1.7 + j9.7

−2.41 − j582

−2.40 − j563

−5.49 − j581

−5.45 − j563

−6.95 − j581

−6.90 − j563

−9.36 − j581

−9.29 − j563

−69.6 − j581

−68.3 − j563

Design

N f = 15 Ns = 12 Table 1

Furthermore, the source resistance can be tuned to improve the noise factor even more. Setting it to  

  m1 ωc 2 RG = Rs 1 +

(34)

ωs

results in an excess noise factor of ⎡

 

 2ωs ⎢ ωs ωs + 1 + F −1= ⎣ m1 ωc m1 ωc m1 ωc

2

⎤ ⎥ ⎦.

(35)

As for the gain of the LSBDC, when the noise is optimized, the available gain is predicted to be ⎡  

2  m ω ⎢ ωs 1 c ·⎣ Ga = 1 +

ωs

⎡ ⎢ ωs ·⎣

m1 ωc

m1 ωc

⎤−1  

2  ω ⎥ s + 1 + ⎦

m1 ωc

⎤−1  

2  ωs m1 ωc ⎥ + 1 + − ⎦ .

m1 ωc

(36)

ωd

Thus, the available gain can still be negative under optimum noise matching conditions, implying that the LSBDC still has a negative equivalent output resistance and hence the ability to deliver power at the signal and downconversion ports. Note that in this case (optimum noise match), it is possible to increase the gain by changing the pumping frequency and hence ωd ; this option is somewhat limited when the LSBDC serves as a downconverter (as opposed to a straight LNA) since the IF frequency is not commonly a design variable on the circuit level. As done for the USBUC, we examine the (noise) performance of the LSBDC with the same varactor structures and pumping conditions summarized in Table 4 as well as similar operating conditions (60 GHz input signal, 1 GHz downconverted signal). In Table 6, the theoretical and simulated

10.6 5.6 4.3 3.0 2.8

output impedances along with the expected noise figure of each of the LSBDC circuits are given. Note that we present the output impedances as opposed to the available gain from the LSBDC. The reason for this is that the absolute value of gain can be smaller than one, yet gain will still be possible, depending on the load. Thus if we know the output impedance of the LSBDC, we can choose the loads appropriately to give the desired gain. Admittedly this is difficult to do in board-level designs, but certainly is not out of the question in high frequency integrated circuits where designers have much more control over the interface between circuits. In the case of the five stripe varactor (measured and modeled), when the source resistance is 50 Ω, the real part of the output impedance will actually be positive, and thus the LSBDC will operate with a power loss when using these varactors under the conditions in this analysis. As shown in Table 6 the single strip device has a promising noise figure assuming that the source has been tuned for noise optimization. The optimum source noise resistance (3.8 Ω) is quite low for the particular version of the LSBDC studied here. Fortunately, the design is not impractically sensitive to source impedance variations. For example, a 600% increase in source resistance to 25 Ω results in a noise figure of 6.95 dB, a 0.72 dB increase. This compares favourably with the performance achieved using standard IC radio topologies. For instance, one report [27] describes a 60 GHz transceiver implemented in a 200 GHz fT 0.12 μm SiGe technology with a measured 11 mW LNA noise figure of 4.5 dB and a 147 mW mixer (driven by a 30 mW VCO) with a noise figure of 14.8 dB. Importantly, it must be emphasized that the simulated parametric behavior reported here is managed with a simple circuit consisting, aside from an oscillator, entirely of passives. Further, the parametric converter is not heavily reliant on the quality of its IC technology, for instance, the noise performance estimated in Table 6 is built around a CMOS varactor with Lu = 0.42 μm. Granted, this

14

EURASIP Journal on Wireless Communications and Networking

analysis considers only the varactor’s noise contribution, but it should be noted that the device under question is inferior to a number of other available device designs cataloged in Tables 1 to 3. Optimizing around one of the better varactors listed (specifically, the minimum unit area varactor with N f = 15 and Ns = 12 in Table 1) predicts very encouraging results for the operational circumstances under consideration. An optimum noise figure of 2.8 dB is predicted under an optimum RG of 1.7 Ω. This value increases to 3, 4.3, and 5.6 dB at more reasonable source resistances of 15, 20, and 25 Ω, respectively. 6.

vndd M4

M3

M1

vnss

M2

vcm +

FREQUENCY CONTROL

A schematic of a simple cross-coupled CMOS LC-VCO structure is shown in Figure 18. The circuit incorporates the common-mode rejection varactor (CMRV) introduced in Section 4.3. Only one switching core is used to overcome tank losses, a PMOS cross-coupled pair. This allows the circuit to operate with low voltage supply headroom. Also, buried channel PMOS devices are employed for their lower flicker noise contribution. In this case, the purpose of the CMRV is to maintain the large tuning range inherent to MOS varactors while simultaneously desensitizing the VCO to common-mode fluctuations induced by the supply noise. The CMRV allows a dif+ − V − ) to simultaneously excite ferential signal (e.g., Vtune tune the n- and p-type varactors into their depletion or accumulation regimes. Meanwhile, a common-mode excitation (e.g., VCM ) drives the two devices into opposite regimes of operation, thus blunting the overall response of the CMRV to that signal. A substantial source of common-mode noise in modern mixed-signal environments is the rail noise at VDD and VSS . The PMOS current mirror (M3 − M4 ) helps block out VDD noise. However, ordinarily, the phase noise performance of this topology would be severely compromised by variations on VSS . That is, any noise occurring on VSS can be expected to lead to a large increase in the VCO phase noise. A comparison of this increase between a 5 GHz LC-VCO employing an n-type varactor and an identical VCO employing a CMRV over a tuning voltage spanning −1V to 1V is shown in Figure 19. Specifically, the change in spot phase noise at 1 MHz removed from the center frequency is compared using the SpectreRF simulator. In both cases (i.e., normal and CMRV tuned VCO) uniform low-frequency noise (0 to 20 MHz) is placed on VDD and VSS and sized such that the common-mode noise density (in V2 /Hz) induced by each noisy rail at a tank node is 70 dB greater than intrinsic VCO noise effect at that node. High-frequency extrinsic noise is less of a concern in this case as it can be more effectively suppressed by on-chip shunt capacitors. For VSS noise (solid line in Figure 19) the CMRV offers a substantial improvement. At best, the 1 MHz spot phase noise is more than 50 dB less sensitive to VSS fluctuations on the CMRV tuned VCO. This occurs when the varactor is tuned within the CV transition region between accumulation and depletion regimes. Expectedly, as Vtune is changed

+ Vtune

VCM +

Vtune

vnss

Figure 18: A simple CMOS LC-VCO with common-mode cancellation varactor.

and the CMRV biased in one of its saturated domains the common-mode cancellation effect is diminished. For VDD fluctuations (dashed line in Figure 19) the CMRV offers little benefit in this topology. In this case, any noise that enters the common-source terminal of the cross-coupled PMOS pair through M3 is converted to a differential form. As already stated, the CMRV does not filter out such excitations. 7.

DISCUSSION

Customized varactor structures can help standard CMOS technology continue to meet more demanding RFIC challenges. In this paper we discussed the role that these devices can play in assisting millimeter wave signalling and frequency control in a mixed-signal environment. The former is addressed by suggesting the use of MOS varactors in parametric conversion circuits. This circuit approach is always an option when operational frequencies beyond the reach of transistor technology are the goal. The MOS varactor assists the efficacy of this technique with its rich nonlinearity (compared to the junction varactor), broad capacitive range, complementary structure (i.e., n-type and p-type varactor modes), three-terminal operation (not discussed in this paper), and unintrusive biasing. Perhaps the most nagging issues with parametric circuits are their need for high pumping frequencies and copious filtering. A number of proposals were made in this work regarding these, from high-frequency reference generation, to subharmonic pumping, to differential excitation. These

Howard Chan et al.

15

60

Phase noise change (dB)

50

[2]

40

[3] 30

[4] 20

[5] 10

[6]

0 10

1

0.8

0.6

0.4

0.2 0 0.2 0.4 Tuning voltage (V)

0.6

0.8

1

VSS noise VDD noise

[7]

[8]

Figure 19: Simulated change in phase noise for single-ended and common-mode reject varactor structure. [9]

approaches are aided by IC implementations (better matching) and the custom device structures (complementary varactors) which can be fabricated with only a layout rearrangement (i.e., without specific need for thermal budget or doping adjustments during processing). Suggestions were also made for customization of physical MOS varactor characteristics to better suit parametric needs. Given the availability of thick oxide analog devices in mixed-signal CMOS technologies and the presence of multiple threshold implants even this adjustment can be implemented without significant process demands. Attention was also brought to several issues involving accumulation-mode varactors in parametric converters. The importance of elastance-based design was mentioned (e.g., this influences the optimum pump biasing) and a simple elastance model discussed. An outstanding point is the impact of nonequilibrium, deep-depletion effects. RF MOS characterization typically does not elicit this behavior, however it is expected to play a role in parametric circuit performance. An investigation into optimum device layout based on compact models highlighted the need to balance finger and stripe count of the varactor. Ignored were the possible influences of capacitive well parasitics on the frequency response of parametric ICs. The effect of a complementary LC-VCO tuning scheme was also studied in simulation. A significant improvement in the ability of the circuit to block common-mode extrinsic noise was noted. This approach can significantly blunt large low-frequency common-mode noise, but, is compromised by the single-ended-to-differential conversion properties of the cross-coupled pair in differential VCOs. REFERENCES [1] M. Faraday, “On a peculiar class of acoustical figures; and on certain forms assumed by groups of particles upon vibrating

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elastic surfaces,” Philosophical Transactions of the Royal Society of London, vol. 121, pp. 299–340, 1831. H. Suhl, “Proposal for a ferromagnetic amplifier in the microwave range,” Physical Review, vol. 106, no. 2, pp. 384–385, 1957. M. T. Weiss, “A solid-state microwave amplifier and oscillator using ferrites,” Physical Review, vol. 107, no. 1, p. 317, 1957. R. V. L. Hartley, “A wave mechanism of quantum phenomena,” Physical Review, vol. 33, p. 289, 1929. R. V. L. Hartley, “Oscillations in systems with non-linear reactance,” Bell System Technical Journal, vol. 15, pp. 424–440, 1936. W. Barrow, “On the oscillations of a circuit having a periodically varying capacitance,” Proceedings of the Institute of Radio Engineers, vol. 22, pp. 201–212, 1934. J.-P. Raskin, A. R. Brown, B. T. Khuri-Yakub, and G. M. Rebeiz, “A novel parametric-effect MEMS amplifier,” Journal of Microelectromechanical Systems, vol. 9, no. 4, pp. 528–537, 2000. A. Olkhovets, D. W. Carr, J. M. Parpia, and H. G. Craighead, “Non-degenerate nanomechanical parametric amplifier,” in Proceedings of 14th IEEE International Conference on Micro Electro Mechanical Systems (MEMS ’01), pp. 298–300, Interlaken, switzerland, January 2001. S. Ranganathan and Y. Tsividis, “Discrete-time parametric amplification based on a three-terminal MOS varactor: analysis and experimental results,” IEEE Journal of Solid-State Circuits, vol. 38, no. 12, pp. 2087–2093, 2003. S. Knappe, V. Shah, P. D. D. Schwindt, et al., “A microfabricated atomic clock,” Applied Physics Letters, vol. 85, no. 9, pp. 1460–1462, 2004. J. M. Manley and H. E. Rowe, “Some general properties of nonlinear elements—Part I. General energy relations,” Proceedings of the Institute of Radio Engineers, vol. 44, pp. 904–913, 1956. H. E. Rowe, “Some general properties of nonlinear elements. II. Small signal theory,” Proceedings of the Institute of Radio Engineers, vol. 46, pp. 850–860, 1958. B. Kleveland, C. H. Diaz, D. Vock, L. Madden, T. H. Lee, and S. S. Wong, “Monolithic CMOS distributed amplifier and oscillator,” in Proceedings of IEEE International Solid-State Circuits Conference, Digest of Technical Papers (ISSCC ’99), pp. 70–71, San Francisco, Calif, USA, February 1999. B. Hackl and J. Bock, “42 GHz active frequency doubler in SiGe bipolar technology,” in Proceedings of International Conference on Microwave and Millimeter Wave Technology (ICMMT ’02), pp. 54–57, Beijing, China, August 2002. C. Lee, T. Yao, A. Mangan, K. Yau, M. A. Copeland, and S. P. Voinigescu, “SiGe BiCMOS 65-GHz BPSK transmitter and 30 to 122 GHz LC-varactor VCOs with up to 21% tuning range,” in Proceedings of IEEE Compound Semiconductor Integrated Circuit Symposium (CSIC ’04), pp. 179–182, Monterey, Calif, USA, October 2004. H. Chan, “Sub-harmonic pumping in parametric amplifiers,” M.Sc. dissertation, University of Calgary, Calgary, Alberta, Canada, (in preparation). T. Soorapanth, C. P. Yue, D. K. Shaeffer, T. I. Lee, and S. S. Wong, “Analysis and optimization of accumulation-mode varactor for RF ICs,” in Proceedings of IEEE Symposium on VLSI Circuits, Digest of Technical Papers, pp. 32–33, Honolulu, Hawaii, USA, June 1998. R. Castello, P. Erratico, S. Manzini, and F. Svelto, “A ±30% tuning range varactor compatible with future scaled technologies,” in Proceedings of IEEE Symposium on VLSI Circuits,

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EURASIP Journal on Wireless Communications and Networking Digest of Technical Papers, pp. 34–35, Honolulu, Hawaii, USA, June 1998. P. Penfield and R. P. Rafuse, Varactor Applications, MIT Press, Cambridge, Mass, USA, 1962. J. Maget, R. Kraus, and M. Tiebout, “A physical model of a CMOS varactor with high capacitance tuning range and its application to simulate a voltage controlled oscillator,” in International Semiconductor Device Research Symposium (ISDRS ’01), pp. 609–612, Washington, DC, December 2001. J. Victory, Z. Yan, G. Gildenblat, C. McAndrew, and J. Zheng, “A physically based, scalable MOS varactor model and extraction methodology for RF applications,” IEEE Transactions on Electron Devices, vol. 52, no. 7, pp. 1343–1353, 2005. Y. P. Tsividis, Operation and Modeling of the MOS Transistor, McGraw-Hill, New York, NY, USA, 1987. E. H. Nicollian and J. R. Brews, MOS (Metal Oxide Semiconductor) Physics and Technology, Wiley-Interscience, New York, NY, USA, 1982. A.-S. Porret, T. Melly, C. C. Enz, and E. A. Vittoz, “Design of high-Q varactors for low-power wireless applications using a standard CMOS process,” IEEE Journal of Solid-State Circuits, vol. 35, no. 3, pp. 337–345, 2000. S. Magierowski, K. Iniewski, and S. Zukotynski, “Differentially tunable varactor with built-in common-mode rejection,” in Proceedings of 45th Midwest Symposium on Circuits and Systems, vol. 1, pp. 559–562, Tulsa, Okla, USA, August 2002. R. G. Meyer and M. L. Stephens, “Distortion in variablecapacitance diodes,” IEEE Journal of Solid-State Circuits, vol. 10, no. 1, pp. 47–54, 1975. B. A. Floyd, S. K. Reynolds, U. R. Pfeiffer, T. Zwick, T. Beukema, and B. Gaucher, “SiGe bipolar transceiver circuits operating at 60 GHz,” IEEE Journal of Solid-State Circuits, vol. 40, no. 1, pp. 156–167, 2005.

Howard Chan is currently completing his electrical engineering M.S. degree in the Department of Electrical and Computer Engineering at Schulich School of Engineering at the University of Calgary. His research is focused on parametric converter IC design.

Zhongbo Chen received his B.Eng. degree in electrical engineering from Southwest Jiaotong University, Sichuan, China, in 1994. Currently he is pursing the M.S. degree in the Department of Electrical and Computer Engineering at the Schulich School of Engineeing at the University of Calgary, Canada. His research interests include RFIC design with the emphasis on VCO noise analysis and surpression, modeling of passive and active devices in deep-submicron CMOS technologies. He is currently completing his electrical engineering M.S. degree in the Department of Electrical and Computer Engineering at the University of Calgary. His research is focused on the custom varactor designs for system-on-chip VCO ICs.

Sebastian Magierowski received the Ph.D. degree in electrical engineering from the University of Toronto and is currently an Assistant Professor in the Department of Electrical and Computer Engineering in the University of Calgary’s Schulich School of Engineering. His general research program is concerned with the realization of integrated wireless microsystems incorporating a wide variety of physical phenomena. More specifically his group is defining advanced physical layer radio architectures accounting for all components between the antenna and channel coder. His industrial experience includes work at Nortel Technology in Ottawa focusing on RF MOS device modeling and high-speed mixed-signal design at PMC-Sierra, Inc., Burnaby, Canada. He is the cofounder of Protolinx, corp., a high-speed wireless network start-up. Krzysztof (Kris) Iniewski is an Associate Professor at the Electrical Engineering and Computer Engineering Department of University of Alberta. His interests are in advanced CMOS devices and RF circuits for wireless applications. His research program is to build “smart dust,” ultra low power ICs to be used in medical applications, wearable electronics, and ad hoc sensor networks. In addition to his academic duties he is a founder and president of SilicoMOS, a consulting firm in Vancouver, Canada, and serves as an Adjunct Professor at Simon Fraser University, University of Calgary, University of British Columbia (UBC) and is an Adjunct Scientist at TRlabs Inc. He has over 15 years of technical experience in semiconductor and communication IC industry. From 1995 to 2003, he was with PMC-Sierra and held various technical and management positions in Research & Development. Prior to joining PMC-Sierra, from 1990 to 1994 he was an Assistant Professor at the University of Toronto’s Electrical Engineering and Computer Engineering Department. He has published over 80 research papers in international journals and conferences. He holds 18 international patents granted in USA, Canada, France, Germany, and Japan. In 1988 he received his Ph.D. degree in electronics (honors) from the Warsaw University of Technology (Warsaw, Poland). He is the coauthor with Dr. Carl McCrosky of Data Networks-VLSI and Optical Fibre, Wiley, 2006 and the editor of Emerging Wireless Technologies, Elsevier, 2006.

Hindawi Publishing Corporation EURASIP Journal on Wireless Communications and Networking Volume 2006, Article ID 32097, Pages 1–11 DOI 10.1155/WCN/2006/32097

Transient and Steady-State Analysis of Nonlinear RF and Microwave Circuits Lei (Lana) Zhu and Carlos E. Christoffersen Department of Electrical Engineering, Lakehead University, Thunder Bay, ON, Canada P7B 5E1 Received 1 November 2005; Accepted 28 February 2006 This paper offers a review of simulation methods currently available for the transient and steady-state analysis of nonlinear RF and microwave circuits. The most general method continues to be the time-marching approach used in Spice, but more recent methods based on multiple time dimensions are particularly effective for RF and microwave circuits. We derive nodal formulations for the most widely used multiple time dimension methods. We put special emphasis on methods for the analysis of oscillators based in the warped multitime partial differential equations (WaMPDE) approach. Case studies of a Colpitts oscillator and a voltage controlled Clapp-Gouriet oscillator are presented and discussed. The accuracy of the amplitude and phase of these methods is investigated. It is shown that the exploitation of frequency-domain latency reduces the computational effort. Copyright © 2006 L. Zhu and C. E. Christoffersen. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

1.

INTRODUCTION

The most common computer-aided circuit analysis technique is the time-domain transient analysis using the timemarching approach to solve the system of ordinary differential equations (ODEs) that represent the circuit. This approach is used in Spice and many other circuit simulators. Although still very useful, this technique presents a number of shortcomings for the analysis of RF and microwave circuits. Amongst these shortcomings is the huge amount of memory and computation time required for the analysis of circuits with widely separated time scales and/or excitations [1]. This is often the case for mixers, power amplifiers, and oscillators. Several techniques have been developed to overcome this problem. Some of them are available in modern circuit simulators and are widely used. In this paper we present an overview of these methods with special attention to the analysis of oscillators. We consider transient analysis methods first. In Section 3 we focus on methods used to directly calculate the steadystate response of circuits. In Section 4 oscillator analysis is discussed with emphasis on methods based on multiple time dimensions. Case studies of a Colpitts oscillator and a voltage controlled Clapp-Gouriet oscillator are presented and discussed in Section 5.

2.

TRANSIENT ANALYSIS

A generic circuit can be described by the following system of differential-algebraic equations: 

Gu(t) + C



  du(t) dQ u(t) + + I u(t) = S(t), dt dt

(1)

here u(t) is the vector of state variables (nodal voltages and selected branch currents), G is a matrix of conductances, C is the matrix representing the linear charge terms, Q(u(t)) and I(u(t)) are vector functions corresponding to the nonlinear devices, and S(t) is a vector that represents the sources. The traditional time-marching technique consists in replacing the derivatives of the state variables for an approximation using a numerical integration rule. For example, if the backward Euler rule is used, we have 







 

du tn+1 u tn+1 − u tn ≈ . dt tn+1 − tn

(2)

The same procedure is applied to the Q vector and the resulting nonlinear algebraic system of equations is solved using the Newton method for each time step:

2

EURASIP Journal on Wireless Communications and Networking 2









  un+1 − un Q un+1 − Q un + + I un+1 = Sn+1 , h h (3)

1.8

here un+1 = u(tn+1 ), un = u(tn ), Sn+1 = S(tn+1 ), and h = tn+1 − tn for simplicity. This analysis is the most general nonlinear circuit analysis. It is applicable to autonomous or nonautonomous circuits with any kind of excitation. If a circuit presents rapid and slow variations simultaneously, this analysis becomes inefficient because a small timestep is required to follow the fast variations with a long total simulation time. Consider, for example, a simulation to estimate the spectral regrowth in an amplifier driven by a digitally modulated carrier [2]. If the rapid variations are oscillatory, the circuit can be analysed using a more efficient approach. Different implementations of this approach exist (e.g., see [3–5]), but the underlying theory is common to all of them and is presented in [1]. Consider a voltage described by the following function:

1.2





v1 (t) = 1 − exp −

t τa



1 + sin



2π t τb



,

(4)

where τa and τb are time constants. A graphical representation of this function with τa = 5 seconds and τb = 20 ms is shown in Figure 1. Many sample points are required to represent this function. For example, 5000 samples were needed in Figure 1 for a total time of 5 seconds. Envelope-following methods [4, 5] take advantage on the fact that the oscillations do not change much in adjacent periods. They follow the shape of the envelope of signals using a time-step much greater than one period of the rapid oscillation and calculate the full response of the circuit with a small time-step only once in a while. Envelope-following methods have been recognised [6] as the most promising methods for the analysis of radio components such as mixers. It was proved in [1] that the idea in envelope-following methods can be seen as a particular case of a more general approach called multipartial differential equations (MPDE). The main idea in the time domain envelope-following (TD-ENV) method using the MPDE approach is to represent signals in more than one time dimension according to the scale of variation. The signals must be periodic in at least one of the dimensions and the period must be constant and known. Note that this condition excludes autonomous circuits. We consider oscillators in Section 4. For example, v1 (t) is replaced by the following bidimensional function:        t1 2π v1 t1 , t2 = 1 − exp − 1 + sin t2 . (5) τa τb This function is plotted in Figure 2, for the same values of τa and τb used before. Only 100 sample points were necessary to represent the waveform in the same time interval. The original function can be easily recovered by setting t1 = t and t2 = t. Equation (1) must be modified as follows: 

Gu + C



  ∂u ∂u ∂Q(u) ∂Q(u) + + + + I(u) = S t1 , t2 , ∂t1 ∂t2 ∂t1 ∂t2 (6)

1.6 1.4 v1 (V)

Gun+1 + C

1 0.8 0.6 0.4 0.2 0

0

1

2

3

4

5

Time (s)

Figure 1: The voltage v1 as a function of time.

where u and S represent the bivariate versions of the state variables and the source vector, respectively. The time plane with the boundaries is shown in Figure 3. In the figure, T is the period along the t2 axis. It was demonstrated in [1] that a solution of (6) with t1 set equal to t2 (the diagonal lines in Figure 3) is also a solution to (1). To obtain the transient response of the circuit, a steady-state problem in the t2 direction must be solved for every time-step along t1 . The efficiency of the method is better when the size of the timestep along t1 is many times greater than T. Unfortunately this is not always possible because fast variations along t1 occur frequently. This problem can be alleviated using an adaptive time-step in the direction of t1 . A time-step control algorithm for this purpose is presented in [7]. Another factor that has a great effect in the rate of variations along t1 is the choice of boundary conditions. The boundary conditions of the MPDE are determined by the initial conditions of the original ODE only at t1 = 0 and t2 = 0. Work [8] presents a method to choose the boundary conditions in the rest of the t1 = 0 line to avoid fast variations along the t1 dimension. The solution of the steady-state problem along the t2 dimension can be accomplished using several methods described in Section 3. One popular choice is to use harmonic balance. Recently an approach using wavelets in the t2 dimension was presented [9]. The MPDE method was presented here for two time dimensions, but if the problem presents more than two rates, more time dimensions can be used as necessary. Work [10] considers a phase-locked loop (PLL) simulation using three time scales. 3.

STEADY-STATE ANALYSIS

Steady-state methods are of great interest for the analysis of RF and microwave circuits. The most widely used steadystate analysis method is harmonic balance (HB). Some of the advantages of this method are that the solution directly gives the harmonic content of the circuit response and that it is

v1 (V)

L. Zhu and C. E. Christoffersen

3

1.4 1.2 1 0.8 0.6 0.4 0.2 0 5 4 0.02 0.015

2

0.01 t2 (s)

3 t1 (s)

1

0.005

Figure 2: The bidimensional voltage v1 (t1 , t2 ).

very large in the order of several tens of thousands. In these cases the solution can still be found with a reasonable CPU time using inexact Newton methods [12] and Krylov subspace methods [2] (note that for smaller problems the regular Newton method is more efficient). Another relevant development is the exploitation of frequency-domain latency in HB [13–15]. These techniques take advantage of the fact that in most circuits the number of harmonics necessary to represent each variable (voltage, current) is not the same. By using a different number of harmonics in each variable, a significant reduction in the computational effort is achieved. There are many problems of interest where the signals are not strictly periodic but quasiperiodic. For example, consider the following voltage waveform: 







v2 (t) = V2 cos ω1 t cos ω2 t . T

t2

0

T

2T

3T

t1

Figure 3: The time plane used for the MPDE method.

easier to include RF circuit components that are better modelled in frequency domain such as transmission lines, filters, and others. In HB each element of the u(t) vector in (1) is represented by a set of phasors,

un (t) = 

K

k=0



Unk e jkωt ,

(7)

where n is the state variable number, k is the harmonic number, and ω = 2π/T. Equation (1) can now be expressed for each angular frequency (kω) as follows: 



G + CΩk U k + I k + Ωk Qk = Sk .

(8)

In this equation Ωk is a diagonal matrix with nonzero elements equal to jkω. The Sk vector represents the sources at angular frequency kω. The nonlinear devices in the circuit are normally modelled in time domain and the I k and Qk vectors are formed taking the kth harmonic component of the Fourier transform of the respective time-domain vectors. The nonlinear devices could be modelled directly in the frequency domain using Volterra series [11]. For weekly nonlinear circuits Volterra series result in more accurate models and are also useful for analytical calculations for design [6]. The unknowns in (8) are the Fourier coefficients (U k ). The system of algebraic equations formed by applying (8) for all harmonics is normally solved using the Newton method. The number of simultaneous unknowns in this equation is equal to (2K + 1)n. In many cases this number can be

(9)

No period can be defined for this signal if ω1 /ω2 is not a rational number. Even in the case that the signal is strictly periodic, it is frequently more convenient to treat it as quasiperiodic. Two approaches exist to treat this problem in HB. The first of them is called artificial frequency mapping and the second is to use a multidimensional Fourier transform [16]. It is often acknowledged [17–19] that for strongly nonlinear circuits the HB method may not be the best because a large number of harmonics is necessary to represent the signals. The most common alternative to HB is the shooting method [20]. The shooting method works by solving (3) for one period of the excitation and finding what initial conditions result in the same state of the circuit at the end of the period. Other approaches using wavelets [17] and adaptive basis functions [18] are still in the research stage and are not widely used yet. The state variables in these methods are represented as a linear combination of a set of basis functions. Equation (1) can then be transformed into a nonlinear algebraic equation. 3.1.

Steady-state analysis and the MPDE

The MPDE approach is also useful for steady-state analysis of quasiperiodic excitations by considering each period in a different time dimension. Equation (6) is applicable with periodic boundary conditions in both t1 and t2 dimensions. The MPDE approach is thus not only useful to analyse circuits with widely separated excitation frequencies but also for circuits with closely spaced excitation frequencies [19]. The HB with multidimensional Fourier transform approach can be seen as a particular case of the MPDE when both time dimensions are considered in the frequency domain. 4.

ANALYSIS OF OSCILLATORS

Oscillator analysis is a difficult task [20–26]. Except for regular time-marching transient analysis (3), all the methods that were reviewed so far must be modified to analyse oscillators. For transient analysis, an alternative to the traditional time-marching approach called warped multitime partial differential equation (WaMPDE) was presented in [22, 27,

4

EURASIP Journal on Wireless Communications and Networking

28]. This approach deals with the fact that the period (or equivalently, the local frequency) in one of the time dimensions is no longer constant. In the WaMPDE this is solved by warping one of the time scales in MPDE to have a constant normalised period. As a result the local frequency is normalised to a constant value and the warped time becomes a function of time. The t1 time axis in the MPDE is now renamed τ2 (they are otherwise equivalent) and the warped time scale is named τ1 . The relation between τ1 and τ2 is given by τ1 =

t 0

 

ω τ2 dτ2 ,

(10)

where ω(τ2 ) is the unknown local frequency. Substituting t1 and t2 in (6) we obtain the WaMPDE nodal equation: 

  ∂u 

∂u Gu + C ω τ2 + ∂τ1 ∂τ2   ∂Q(u )

+ ω τ2

∂τ1



  ∂Q(u) + + I(u) = S τ1 , τ2 . ∂τ2

(11)

An additional equation is required to balance the introduction of the unknown local frequency. This equation is formed by imposing a smooth phase variation along τ2 [22]. Often the HB method is used in the τ1 dimension. Then each element of the u(t) vector in (1) is represented by 





un τ1 , τ2 = 

K

k=0

 



Unk τ2 e jkτ1 ,

(12)

where again k is the harmonic number and the period in the warped time scale (τ1 ) is normalised to 2π (i.e., ω = 1). We can reformulate now (11) for each harmonic (k): 



G + CΩk U k + C

∂U k ∂Qk + Ωk Qk + + I k − Sk = 0. ∂τ2 ∂τ2

(13)

As stated before, the phase of one of the variables must then be fixed to restore the number of unknowns to be equal to the number of equations. That can be achieved by setting the imaginary part of one of the variables to be zero,    Un1 = 0.

(14)

Equation (13) is discretised in the τ2 direction using the backward Euler (BE) rule, trapezoidal rule, or any other numerical integration method. The resulting algebraic nonlinear system is then solved with the Newton-Raphson method for each value of τ2 . This technique is referred in this work as time-frequency envelope transient (TFET). 4.1. Transient Given initial conditions for (1), the corresponding boundary conditions in the TFET analysis can be obtained from a short section of the transient response of the oscillator obtained from a time-marching simulation [29]. The choice of

accurate boundary conditions is important if a good agreement between time-marching and TFET analyses is desired. To improve the efficiency of the simulation, the number of harmonics for each variable un can be adaptively controlled [15]. This is sometimes referred as frequency-domain latency exploitation. This is achieved as follows. At the end of the calculation for each step of τ2 , the magnitudes of the last two harmonics are considered. If they are greater than some threshold value, then the number of harmonics for that variable (l) is increased by one. If they are smaller than another threshold, then l is decreased by one. Otherwise it is left unchanged. One advantage of this approach is that the number of harmonics is increased or reduced as needed. Each row of (13) (nodal equation at one frequency) is considered at a number of frequencies equal to the number of harmonics of the corresponding nodal voltage. In this way the number of equations is always kept equal to the number of unknowns. An adaptive time-step control algorithm is used in order to minimise the number of time steps [29]. The time-step along τ2 is adaptively changed according to a local truncation error estimation, 

hnew = hold

max 

1/m

,

(15)

where max is the maximum acceptable truncation error,  is the current truncation error, and m is a number that depends on the integration method being used (m = 3 for trapezoidal integration). This substantially reduces the computational cost and improves the accuracy of the TFET. 4.2.

Steady-state

For the steady-state analysis of oscillators, harmonic balance (HB) has been the dominant approach in recent years. Though HB is one of the most important frequency-domain techniques, it still has some limitations. In particular a good initial guess is needed to make HB converge to the desired oscillatory solution. It is especially difficult to get a good initial guess of the oscillator frequency. Several methods have been proposed to improve this limitation. For example, in [25] the HB equations are modified by including the Kurokawa condition to eliminate the DC solution. In [26] a voltage source probe at the fundamental frequency that is an open circuit at all other frequencies is inserted to avoid the DC solution. By means of an iterative process the amplitude and frequency of the probe are adjusted until there is no current through the probe. At this point the autonomous solution is found. A similar probe concept with the addition of a continuation method has been proposed more recently [23] to improve convergence. Accelerated transients have been used [15, 20, 30] to find the steady-state regime. In order to accelerate the finding of the steady-state regime, the transient behaviour of the circuit is artificially reduced in [30]. In [20] an envelope-transient analysis is used to improve the convergence of the shooting method. Another new approach improving the convergence of the HB analysis of oscillators was presented in [15]. This approach is based on an accelerated TFET method and is

L. Zhu and C. E. Christoffersen

5 Vcc

summarised here. A TFET simulation is started with the boundary conditions set to the DC bias point values. An excitation current, if τ2 ≤ ta , otherwise,

(16)

is injected from the ground node into one of the nodes where oscillations are expected. Here, I0 is a small real number (normally a few μA) and ta is set equal to the initial time-step size along τ2 (h). The purpose of iS is to start oscillations by moving the system away from the equilibrium point. The system will then naturally tend to reach the desired oscillatory steady state. The key of this work is to accelerate the TFET simulation to reach a point in τ2 close to the steady state in the minimum possible number of Newton iterations and then use the state at that point as the initial guess of a regular autonomous HB analysis. Since the focus is on the steady state, it is not necessary to calculate the transient evolution with great precision as long as it converges close to the actual steady state of the circuit. Thus the time-step along τ2 and other parameters in the simulation are controlled to minimise the number of Newton iterations [15]. When the local frequency function becomes constant and the difference between two periodic solutions along τ2 becomes small, the accelerated TFET is stopped and a regular oscillator HB analysis is started using the last solution along τ2 as the initial guess. Note that the regular oscillator HB analysis is obtained by setting all derivatives with respect to τ2 to be zero in (13). 5.

Rc

CASE STUDIES AND DISCUSSION

In this section we perform a transient and steady-state analysis of two oscillators: a Colpitts oscillator and voltage controlled oscillator (VCO). In each oscillator, the regular time domain simulation is provided followed by a WaMPDEbased simulation, and then both results are compared. 5.1. Colpitts oscillator The Colpitts oscillator taken from [31] uses a capacitive voltage divider in the LC tank circuit. In the circuit shown in Figure 4, the component values are: C1 = C2 = 2 pF, Cc = 400 pF, Ce = 100 pF, L1 = 1 μH, R1 = 8 kΩ, R2 = 2 kΩ, Rc = 2.4 kΩ, Re = 1.3 kΩ, Vcc = 11 V, BF = 100, and BR = 1. 5.1.1. Transient analysis This oscillator exhibits an extremely long initial transient compared with the oscillation period. Part of the transient simulation is presented in Figure 5. The CPU time in a 1.5 GHz computer using Matlab was 57 seconds for a simulation stop time of 10 μs. Clearly time-marching simulation is very time-consuming for the analysis of this circuit. In order to obtain an accurate result, the acceptable truncation error in this simulation was reduced until no phase difference could be observed with further reductions. In this way

L1

Vout

R1

C1

Cc

C2

Q1 R2

RE

CE

Figure 4: Schematic of a Colpitts oscillator.

10 9 8 Output voltage (V)

⎧     ⎨I0 cos τ1 iS τ1 , τ2 = ⎩ 0

7 6 5 4 3 2 1

0

0.2

0.4

0.6 Time (s)

0.8

1 ×10−4

Figure 5: Transient response of the Colpitts oscillator.

we can take the result of this time-marching simulation as a reference for both magnitude and phase information. We now discuss the simulation results using the TFET approach. The TFET simulation starts from the specified initial conditions and the stop time along τ2 is set to 0.07 seconds. The initial number of harmonics is 11 and the adaptive harmonic balance automatically adjusts this number as required. The adaptive time-step algorithm increases the step size according to the local truncation error. These two provisions largely speed up the simulation. Total CPU time is 199 seconds. A time-marching simulation would require approximately 15 hours to produce the same result. Figure 6 shows the multitime expression of the output voltage. Very good agreement between TFET simulation and the time-marching simulation has been achieved as shown in the top of Figure 7. There is a phase error accumulation along τ2 shown at the bottom of Figure 7. The relative amplitude error and absolute phase error of the first harmonic in TFET and ODE simulations are presented in Figure 8. The amplitude error is very small, but the phase error may be important in

EURASIP Journal on Wireless Communications and Networking The amplitude error (%)

6

Output voltage (V)

15

10

0.8 0.6 0.4 0.2 0

5

0

20

ew 2 ar p ed ti

−5

1

me

0 −15

×10−8

−10

of rithm Loga

the re

e al tim

Figure 6: Bidimensional representation of output voltage.

The phase error (degree)

0

3

Th

100

120

80

100

120

10 5 0

0

20

40

60 Time (μs) (b)

Figure 8: Relative error in the magnitude of the first harmonic.

10 10.55 10.6

10.65 10.7 10.75 10.8 Time (μs)

10.85 10.9

Time marching TFET (a) Proposed WaMPDE solution compared to time-marching simulation 10 9 8 7 6 5 4 3

9 Output voltage (V)

Output voltage

80

15

Proposed WaMPDE solution compared to time-marching simulation

Output voltage

60 Time (μs) (a)

0 4

9 8 7 6 5 4 3 2 10.5

40

8 7 6 5 4 3 9.97

99.5 99.55 99.6

99.65 99.7 99.75 99.8 Time (μs)

99.85

Time marching TFET

9.975

9.98 Time (s)

9.985 ×10−5

Time marching TFET with large LTE (0.01) TFET with small LTE (0.0001)

(b)

Figure 7: TFET solution compared to time-marching solution.

Figure 9: Comparison of time-marching and TFET with a smaller maximum local truncation error.

some cases. It should be noted that a comparable phase error would be obtained with a time-marching simulation if the acceptable truncation error is not set to a very small number. The phase error in the TFET simulation can be reduced if the acceptable local truncation error in the TFET simulation is reduced as the results of Figure 9 indicate. However, the reduction in the acceptable local truncation error increases the number of time steps along τ2 and this results in a

significantly longer simulation time. Finally, Figure 10 shows the size of the Jacobian matrix and the size of the time-step along τ2 for each step in τ2 . The size of the Jacobian matrix is proportional to the total number of harmonics considered in the simulation. As the variations in τ2 become smooth, the time-step is increased and the size of the Jacobian matrix is increased as more harmonics are generated in the nodal voltages.

7

190

0

×107

180

−1

2

170

−2

1.8

160

−3

150

−4

140

−5

130

−6

120

−7

110

−8

100

0

10

20

30 40 50 60 Sample number along τ2

70

1.6 Local frequency (Hz)

Logarithm of time step

Jacobian size

L. Zhu and C. E. Christoffersen

1.4 1.2 1 0.8 0.6

−9

80

0.4 0.2

Jacobian size Time step

0

1

2

3

4

5

6

Figure 10: Size of the Jacobian matrix and the size of the time-step along τ2 for each step in τ2 .

7 ×10−7

Time (s) IC:3f IC:4f

IC:0.5f IC:f IC:2f

Figure 12: Fundamental frequency as a function of τ2 .

9

8 6

8

4 2 0 2 1.5 Th e

0

wa rp

1 0.5 ed t im e

0 −8

×10−7

−6

ri Loga

−4

−2

real f the thm o

t i me

Output voltage (V)

Output voltage (V)

10

7 6 5 4

Figure 11: Bidimensional representation of output voltage.

3

0

0.5

1 Time (s)

2 ×10−7

Steady-state solution Final multitime solution

5.1.2. Steady-state analysis The excitation current (iS ) was applied to the base node with I0 set to 10 μA. The bidimensional plot of the output voltage as a function of τ1 and τ2 is shown in Figure 11. The CPU time of the accelerated TFET and HB analyses combined is 52 seconds. The oscillator frequency determined by the warped function ω(τ2 ) is 5.04 MHz as shown in Figure 12. This figure illustrates the robustness of the proposed method. Different initial frequencies converge to the correct value. In Figure 13 the steady state is compared with the final line of the multitime simulation. This shows how close the result from the accelerated TFET to the steady state is. Figure 14 shows the Jacobian matrix size and the number of Newton iterations at each time-step (sample number).The

1.5

Figure 13: Steady-state solution compared to final line in multitime solution.

adaptive control of the time-step along τ2 keeps the number of Newton iterations small for each value of τ2 . The Jacobian matrix size increases as the number of harmonics increases. 5.2.

Clapp-Gouriet oscillator

In this section, we present the analysis of a VCO circuit based on the Clapp-Gouriet configuration [32]. Figure 15 shows the electrical schematic of the VCO. In this circuit

EURASIP Journal on Wireless Communications and Networking 28

1

120

24

0.5

100

20

80

16

60

12

40

8

20

4

0

0

10

20 30 40 50 Sample number along τ2

Output voltage (V)

140

Newton iterations

Jacobian size

8

−0.5 −1 −1.5 −2

0 70

60

0

−2.5

0

10

20

Jacobian size Newton iterations

30 Time (ms)

40

50

Figure 16: Transient response of the VCO.

Figure 14: Jacobian size and number of Newton iterations.

Vcc 1 Rc C4

R3

Output voltage (V)

R1

Vout

Q1 L1 C1 Vdc

R2

D1

−2

8 6 The

RE

C2

−1

−3

RL

C3

0

4

war p

4 ed t

2 ime

0

0

2 e ( s) al t im e r The

×10−4

Figure 15: A VCO using Clapp-Gouriet configuration.

Figure 17: Bidimensional representation of output voltage of VCO.

C1 = 82 pF, C2 = 220 pF, C3 = 47 pF, C4 = 330 pF, L1 = 102.55 μH, R1 = 220 kΩ, R2 = 22 kΩ, R3 = 47 Ω, Rc = 2.2 kΩ, Re = 220 Ω, Rl = 100 Ω, Vcc = 12 V, BF = 70, and BR = 5. The oscillator frequency is tuned by a diode connected to a control voltage, Vdc . The circuit is analysed with a sinusoidal control voltage,

the time-marching and TFET analyses is shown in Figure 19. As with the previous case study, there is some phase error that can be reduced by reducing the tolerance of the local truncation error. Finally, Figure 20 shows the size of the Jacobian matrix and the size of the time-step along τ2 for each step in τ2 . It can be observed that both quantities follow the variations of the transient and the control voltage.





Vdc = 3 + sin 2π104 t V.

(17)

The initial transient is shown in Figure 16. In TFET analysis, the initial number of harmonics is set to 8 and the adaptive HB algorithm automatically adjusts this number for each node every time-step along τ2 . The bidimensional plot of the output voltage is shown in Figure 17. Good agreement between time-marching and TFET analyses is achieved as shown in Figure 18. A plot showing the first harmonic magnitude and phase difference between

6.

CONCLUSIONS

We have presented a review of simulation methods currently available for the transient and steady-state analysis of nonlinear RF and microwave circuits. Although the timemarching approach used in Spice will continue to be widely used, envelope-following methods are particularly effective for RF and microwave circuits and they are becoming a popular choice. Recent improvements to oscillator analysis were summarised and case studies of a Colpitts oscillator

9

0 Jacobian size

Output voltage (V)

0.5

−0.5 −1 −1.5

122

−5.5

120

−6

118

−6.5

116

−7

114

−7.5

112

−8

110

−8.5

108

−9

106

−9.5

104 −2

2.7

2.8

2.9 3 Time (s)

3.1

3.2 ×10−6

0

50

100 150 200 Sample number along τ2

Logarithm of time step

L. Zhu and C. E. Christoffersen

−10

250

Jacobian size Time step

Time marching TFET

Figure 20: Size of the Jacobian matrix and the size of the time-step along τ2 for each step in τ2 for the VCO.

The amplitude error (%)

Figure 18: Time-marching and TFET results compared.

by reducing the size of the Jacobian matrix in the Newton method. It was shown that an accelerated TFET analysis can be effectively used to improve the convergence of the HB oscillator analysis.

0.8 0.6 0.4 0.2 0

ACKNOWLEDGMENT 2

4

6

8

10

12

Time (μs)

This work was supported by Natural Sciences and Engineering Research Council of Canada (NSERC).

The phase error (degree)

(a) 4

REFERENCES

3 2 1 0

2

4

6

8

10

12

Time (μs) (b)

Figure 19: Comparison of ODE and warped MPDE in first harmonic.

and a voltage controlled Clapp-Gouriet oscillator were presented. In both cases there was good agreement between time-marching and TFET analyses, but it was noted that some phase error may occur if the local truncation error tolerance is not kept small enough. This may be an important consideration for the analysis of PLLs and should be further investigated. The simulations indicated that the adaptive HB technique significantly reduces the computational effort

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L. Zhu and C. E. Christoffersen Carlos E. Christoffersen received the Electronic Engineer degree at the National University of Rosario, Argentina, in 1993. From 1993 to 1995, he was a Research Fellow of the National Research Council of Argentina (CONICET). He received an M.S. degree and a Ph.D. degree in electrical engineering in 1998 and 2000, respectively, from North Carolina State University (NCSU). Currently he is an Assistant Professor in the Department of Electrical Engineering at Lakehead University, Thunder Bay, Canada. He is a Member of the IEEE. His current research interests include analogue and RF circuit computer-aided design including electromagnetic and thermal interactions.

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