Computer Architecture [PDF]

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Computer Architecture Structured Computer Organization by A. Tanenbaum, Prentice Hall, 2005

B. W. Wah ECE 290 Fall 2006

Introductions

1

Languages, Levels, Virtual Machines

A multilevel machine 3 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

Contemporary Multilevel Machines

A six-level computer. The support method for each level is indicated below it .

4

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

2

Computer Generations •

Zero’th Generation Mechanical Computers (1642 – 1945)



First Generation Vacuum Tubes (1945 – 1955)



Second Generation Transistors (1955 – 1965)



Third Generation Integrated Circuits (1965 – 1980)



Fourth Generation Very Large Scale Integration (1980 – ?)

5

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

Von Neumann Machine

The original Von Neumann machine. 6 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

3

PDP-8 Innovation – Single Bus

The PDP-8 omnibus 7 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

Technological and Economic Forces

Moore’s law predicts a 60-percent annual increase in the number of transistors that can be put on a chip. The data points given in this figure are memory sizes, in bits. 8

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

4

Personal Computer 1. Pentium 4 socket 2. 875P Support chip 3. Memory sockets 4. AGP connector 5. Disk interface 6. Gigabit Ethernet 7. Five PCI slots 8. USB 2.0 ports 9. Cooling technology 10. BIOS A printed circuit board is at the heart of every personal computer. This figure is a photograph of the Intel D875PBZ board. The photograph is copyrighted by the Intel Corporation, 2003 and is used by permission. 9 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

Example Computer Families • • •

Pentium 4 by Intel UltraSPARC III by Sun Microsystems The 8051 chip by Intel, used for embedded systems

10 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

5

Intel Computer Family (1)

The Intel CPU family. Clock speeds are measured in MHz (megahertz) where 1 MHZ is 1 million cycles/sec. 11 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

Intel Computer Family (2)

The Pentium 4 chip. The photograph is copyrighted by the Intel Corporation, 2003 and is used by permission. 12

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

6

Intel Computer Family (3)

Moore’s law for (Intel) CPU chips. 13 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

Computer Systems Organization

7

Central Processing Unit

The organization of a simple computer with one CPU and two I/O devices 15 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

CPU Organization

The data path of a typical Von Neumann machine. 16 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

8

Instruction Execution Steps 1. 2. 3. 4. 5. 6.

Fetch next instruction from memory into instr. register Change program counter to point to next instruction Determine type of instruction just fetched If instructions uses word in memory, determine where Fetch word, if needed, into CPU register Execute the instruction Go to step 1 to begin executing following instruction

17 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

RISC versus CISC • 1980: RISC has simple instructions that can be executed in one cycle of a simple data path • Execute frequently used instructions efficiently and less frequently used instructions less efficiently • Wins over CISC that takes multiple and longer cycles to execute a complex instruction • May take 4-5 instructions to accomplish a complex operation

• CISC is still predominant in today’s market • Backward compatibility to early CISC computers • Starting with 486, Intel CPUs contain a RISC core that executes the simplest (and typically most common) instructions in a single data path cycle, while interpreting the more complicated instructions in the usual CISC way 18 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

9

Design Principles for Modern Computers • • • • •

All instructions directly executed by hardware Maximize rate at which instructions are issued Instructions should be easy to decode Only loads, stores should reference memory Provide plenty of registers

19 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

Instruction-Level Parallelism

a) b)

A five-stage pipeline The state of each stage as a function of time. Nine clock cycles are illustrated 20 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

10

Superscalar Architectures (1)

Dual five-stage pipelines with a common instruction fetch unit. 21 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

Superscalar Architectures (2)

A superscalar processor with five functional units. 22 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

11

Processor-Level Parallelism (1)

An array of processor of the ILLIAC IV type. (ILLIAC I in Sept. 1952) 23 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

Processor-Level Parallelism (2)

a) b)

A single-bus multiprocessor. A multicomputer with local memories. 24

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12

Cache Memory

The cache is logically between the CPU and main memory. Physically, there are several possible places it could be located. 25 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

Memory Hierarchies

A five-level memory hierarchy. 26 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

13

Magnetic Disks (1)

A portion of a disk track. Two sectors are illustrated. 27 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

Magnetic Disks (2)

A disk with four platters. 28 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

14

Magnetic Disks (3)

A disk with five zones. Each zone has many tracks and has uneven number of tracks across zones. 29 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

RAID (1) Redundant Array of Inexpensive Disks (1988)

4 bit with error correction in CM2

RAID levels 0 through 2. Backup and parity disks are shown shaded. 30 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

15

RAID (1) Redundant Array of Inexpensive Disks

RAID levels 3 through 5. Backup and parity disks are shown shaded. 31 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

The Processor Level

16

CPU Chips

The logical pinout of a generic CPU. The arrows indicate input signals and output signals. The short diagonal lines indicate that multiple pins are used. For a specific CPU, a number will be given to tell how many. 33

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Computer Buses (1)

A computer system with multiple buses. 34 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

17

Computer Buses (2)

Examples of bus masters and slaves. 35 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

Bus Width

Growth of an Address bus over time. 36 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

18

Bus Clocking

Read timing on a synchronous bus. 37 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

Asynchronous Buses

Operation of an asynchronous bus. 38 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

19

Bus Arbitration (1)

(a) A centralized one-level bus arbiter using daisy chaining. (b) The same arbiter, but with two levels. 39 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

Bus Arbitration (2)

Decentralized bus arbitration. 40 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

20

Bus Operations (1)

A block transfer. 41 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

Bus Operations (2)

Use of the 8259A interrupt controller. 42 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

21

The Pentium 4

The Pentium 4 physical pinout. 43 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

The Pentium 4’s Logical Pinout Logical pinout of the Pentium 4. Names in upper case are the office are the official Intel names for individual signals. Names in mixed case are groups of related signals or signal descriptions. 44 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

22

Pipelining on the Pentium 4’s Memory Bus

Pipelining requests on the Pentium 4’s memory bus. 45 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

The UltraSPARC III (1)

The UltraSPARC III CPU chip. 46 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

23

The UltraSPARC III (2)

The main features of the core of an UltraSPARC III system. 47 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

The PCI Bus (1)

Architecture of an early Pentium system. The thicker buses have more bandwidth than the thinner ones but the figure is not to scale. 48 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

24

The PCI Bus (2)

The bus structure of a modern Pentium 4. 49 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

PCI Bus Arbitration

The PCI bus uses a centralized bus arbiter. 50 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

25

PCI Express

A typical PCI Express system. 51 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

PCI Express Protocol Stack

(a) The PCI Express protocol stack. (b) The format of a packet. 52 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

26

The Microarchitecture Level

Speed Versus Cost

1. Reduce the number of clock cycles needed to execute an instruction. 2. Simplify the organization so that the clock cycle can be shorter. 3. Overlap the execution of instructions.

54 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

27

Merging the Interpreter Loop with the Microcode (1)

Original microprogram sequence for executing POP. 55 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

Merging the Interpreter Loop with the Microcode (2)

Enhanced microprogram sequence for executing POP.

56 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

28

Pipelining

Graphical illustration of how a pipeline works.

57 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

A Seven-Stage Pipeline

The Mic-4 pipeline. 58 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

29

Cache Memory

A system with three levels of cache. 59 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

Direct-Mapped Caches

(a) A direct-mapped cache. (b) A 32-bit virtual address. 60 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

30

Set-Associative Caches

A four-way set-associative cache. 61 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

Branch Prediction

(a) A program fragment. (b) Its translation to a generic assembly language. 62 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

31

Dynamic Branch Prediction (1)

(a) A 1-bit branch history. (b) A 2-bit branch history. (c) A mapping between branch instruction address and target address.63 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

Dynamic Branch Prediction (2)

A 2-bit finite-state machine for branch prediction. 64 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

32

Speculative Execution

a) b)

A program fragment. The corresponding basic block graph.

65

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Overview of the NetBurst Microarchitecture

The block diagram of the Pentium 4. 66 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

33

The NetBurst Pipeline

A simplified view of the Pentium 4 data path.

67 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

The Operating System Machine Level

34

Operating System Machine

Positioning of the operating system machine level. 69 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

Paging

A mapping in which virtual addresses 4096 to 8191 are mapped onto main memory addresses 0 to 4095. 70 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

35

Implementation of Paging (1) The first 64 KB of virtual address space divided into 16 pages, with each page being 4K.

71 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

Implementation of Paging (2)

A 32 KB main memory divided up into eight page frames of 4 KB each.

72 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

36

Implementation of Paging (3)

Formation of a main memory address from a virtual address.

73 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

Demand Paging and the Working Set Model

A possible mapping of the first 16 virtual pages onto a main memory with eight page frames.

74 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

37

Page Replacement Policy

Failure of the LRU algorithm. 75 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

Segmentation (1)

In a one-dimensional address space with growing tables, one table may bump into another. 76 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

38

Segmentation (2)

A segmented memory allows each table to grow or shrink independently of the other tables.

77

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Segmentation (3)

Comparison of paging and segmentation. 78 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

39

Implementation of Segmentation (1)

(a)-(d) Development of external fragmentation. (e) Removal of the external fragmentation by compaction. 79 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

Implementation of Segmentation (2)

Conversion of a two-part MULTICS address into a main memory address. 80 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

40

Parallel Computer Architectures

Parallel Computer Architectures

(a) On-chip parallelism. (b) A coprocessor. (c) A multiprocessor. (d) A multicomputer. (e) A grid. 82 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

41

Instruction-Level Parallelism

(a) A CPU pipeline. (b) A sequence of VLIW instructions. 83 (c) An instruction stream with bundles marked. Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

The TriMedia VLIW CPU

A typical TriMedia instruction, showing five possible operations. 84 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

42

On-Chip Multithreading (1)

(a) – (c) Three threads. The empty boxes indicated that the thread has stalled waiting for memory. (d) Fine-grained multithreading. (e) Coarse-grained multithreading. 85 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

On-Chip Multithreading (2)

Multithreading with a dual-issue superscalar CPU. (a) Fine-grained multithreading. (b) Coarse-grained multithreading. (c) Simultaneous multithreading.

86

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43

Hyperthreading on the Pentium 4

Resource sharing between threads in the Pentium 4 NetBurst microarchitecture. 87 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

Homogeneous Multiprocessors on a Chip

Single-chip multiprocessors. (a) A dual-pipeline chip. (b) A chip with two cores. 88 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

44

Heterogeneous Multiprocessors on a Chip (1)

The logical structure of a simple DVD player contains a heterogeneous multiprocessor containing multiple cores for different functions. 89 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

Heterogeneous Multiprocessors on a Chip (2)

An example of the IBM CoreConnect architecture. 90 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

45

Introduction to Network Processors

A typical network processor board and chip. 91 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

The Nexperia Media Processor

The Nexperia heterogeneous multiprocessor on a chip. 92 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

46

Multiprocessors

(a) A multiprocessor with 16 CPUs sharing a common memory. (b) An image partitioned into 16 sections, each being analyzed by a different CPU. 93

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Multicomputers (1)

(a) A multicomputer with 16 CPUs, each with its own private memory. (b) The bit-map image of Fig. 8-17 split up among the 16 memories. 94

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47

Multicomputers (2)

Various layers where shared memory can be implemented. (a) The hardware. (b) The operating system. (c) The language runtime system. 95 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

Taxonomy of Parallel Computers (1)

Flynn’s taxonomy of parallel computers. 96 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

48

Taxonomy of Parallel Computers (2)

A taxonomy of parallel computers. 97 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

UMA Symmetric Multiprocessor Architectures

Three bus-based multiprocessors. (a) Without caching. (b) With caching. (c) With caching and private memories. 98 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

49

UMA Multiprocessors Using Crossbar Switches

(a) An 8 × 8 crossbar switch. (b) An open crosspoint. (c) A closed crosspoint.

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UMA Multiprocessors Using Multistage Switching Networks

An omega switching network. 100 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

50

NUMA Multiprocessors

A NUMA machine based on two levels of buses. The Cm* was the first multiprocessor to use this design. 101 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

Cache Coherent NUMA Multiprocessors

(a) A 256-node directory-based multiprocessor. (b) Division of a 32-bit memory address into fields. (c) The directory at node 36. 102 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

51

The Sun Fire E25K NUMA Multiprocessor (1)

The Sun Microsystems E25K multiprocessor. 103 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

BlueGene (1)

The BlueGene/L custom processor chip. 104 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

52

BlueGene (2)

The BlueGene/L. (a) Chip. (b) Card. (c) Board. (d) Cabinet. (e) System. 105 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

Red Storm (1)

Packaging of the Red Storm components. 106 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

53

Red Storm (2)

The Red Storm system as viewed from above. 107 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

A Comparison of BlueGene/L and Red Storm

A comparison of BlueGene/L and Red Storm.

108 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

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Google (1)

Processing of a Google query. 109 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

Google (2)

A typical Google cluster.

110 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

55

Grid Computing

The grid layers. 111 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

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