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146. Chapter 5: Basic Peripherals and their Interfacing with 8086/88. 149. 5.1 Semiconductor Memory Interfacing. 149. 5.

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Contents Preface

xiii

Acknowledgements

xix

Chapter 1: The Processors: 8086/8088— Architectures, Pin Diagrams and Timing Diagrams   1.1    1.2    1.3    1.4    1.5    1.6    1.7    1.8    1.9  1.10 

Register Organisation of 8086 Architecture Signal Descriptions of 8086 Physical Memory Organisation General Bus Operation I/O Addressing Capability Special Processor Activities Minimum Mode 8086 System and Timings Maximum Mode 8086 System and Timings The Processor 8088 Summary  Exercises

1 1 3 8 13 15 16 17 19

23

25 33 33

Chapter 2:  8086/8088 Instruction Set and Assembler Directives

35

2.1  2.2  2.3  2.4  2.5 

35 38 43 68 76 77 77

Machine Language Instruction Formats Addressing Modes of 8086 Instruction Set of 8086/8088 Assembler Directives and Operators Do’s and Don’ts While Using Instructions  Summary  Exercises

Chapter 3:  The Art of Assembly Language Programming with 8086/8088 3.1  3.2  3.3  3.4 

A Few Machine Level Programs Machine Coding the Programs Programming with an assembler Assembly Language Example Programs Summary  Exercises

Chapter 4:  Special Architectural Features and Related Programming 4.1  Introduction to Stack 4.2  Stack Structure of 8086/88

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79 80 85 90 96 121 121 81 123 124

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Contents

  4.3    4.4    4.5    4.6    4.7    4.8    4.9  4.10  4.11 

Interrupts and Interrupt Service Routines Interrupt Cycle of 8086/8088 Non Maskable Interrupt Maskable Interrupt (Intr) Interrupt Programming Passing Parameters To Procedures Handling Programs of Size More than 64 K Macros Timings and Delays Summary  Exercises

Chapter 5:  Basic Peripherals and their Interfacing with 8086/88 5.1  5.2  5.3  5.4  5.5  5.6  5.7  5.8  5.9 

Semiconductor Memory Interfacing Dynamic Ram Interfacing Interfacing I/O Ports Pio 8255 [Programmable Input-Output Port] Modes of Operation of 8255 Interfacing Analog to Digital Data Converters Interfacing Digital to Analog Converters Stepper Motor Interfacing Control of High Power Devices Using 8255 Summary  Exercises

Chapter 6: Special Purpose Programmable Peripheral Devices and Their Interfacing 6.1  6.2  6.3  6.4 

Programmable Interval Timer 8254 Programmable Interrupt Controller 8259A The Keyboard/Display Controller 8279 Programmable Communication Interface 8251 Usart Summary  Exercises

Chapter 7:  Dma, & High Storage Capacity Memory Devices 7.1  7.2  7.3  7.4 

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Dma Controller 8257 Dma Transfers and Operations Programmable Dma Interface 8237 High Storage Capacity Memory Devices Summary  Exercises

129 130 132 132 133 136 140 141 143 146 146 149 149 158 166 174 177 200 213 216 220 220 221

223 223 236 253 264 311 311 283 283 290 295 307 311 311

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Chapter 8: Multimicroprocessor Systems 8.1  8.2  8.3  8.4  8.5  8.6  8.7 

Interconnection Topologies Software Aspects of Multimicroprocessor Systems Numeric Processor 8087 I/O Processor 8089 Bus Arbitration and Control Tightly Coupled and Loosely Coupled Systems Design of a PC Based Multimicroprocessor System Summary  Exercises

Chapter 9: 80286–80287—A Microprocessor with Memory Management and Protection   9.1    9.2    9.3    9.4    9.5    9.6    9.7    9.8    9.9  9.10  9.11  9.12  9.13  9.14  9.15  9.16  9.17  9.18 

Salient Features of 80286 Internal Architecture of 80286 Signal Descriptions of 80286 Real Addressing Mode Protected Virtual Address Mode (Pvam) Privilege Protection Special Operations 80286 Bus Interface Basic Bus Operations Fetch Cycles of 80286 80286 Minimum System Configuration Interfacing Memory and I/O Devices with 80286 Priority of Bus Use by 80286 Bus Hold and Hlda Sequence Interrupt Acknowledge Sequence Instruction Set Features 80287 Math Coprocessor Summary  Exercises

ix

313 314 318 320 338 341 347 348 359 359

361 361 362 367 370 371 379 383 385 387 388 389 391 394 394 397 398 398 405 415 415

Chapter 10:  80386–80387 and 80486—The 32-Bit Processors

417

10.1  10.2  10.3  10.4  10.5  10.6 

417 418 421 424 425 425

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Salient Features of 80386dx Architecture and Signal Descriptions of 80386 Register Organization of 80386 Addressing Modes Data Types of 80386 Real Address Mode of 80386

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  10.7    10.8    10.9  10.10  10.11  10.12  10.13 

Protected Mode of 80386 Segmentation Paging Virtual 8086 Mode Enhanced Instruction Set of 80386 The Coprocessor 80387 The Cpu With a Numeric Coprocessor—80486dx Summary  Exercises

426 427 430 432 434 436 439 450 451

Chapter 11: Recent Advances in Microprocessor Architectures—A Journey from Pentium Onwards 453 11.1  11.2  11.3  11.4  11.5  11.6  11.7  11.8  11.9  11.10  11.11  11.12  11.13 

Salient Features of 80586 (Pentium) A Few Relevant Concepts of Computer Architecture System Architecture Branch Prediction Enhanced Instruction Set of Pentium What is Mmx? Intel Mmx Architecture Mmx Data Types Wraparound and Saturation Arithmetic Mmx Instruction Set Salient Points about Multimedia Application Programming Journey to Pentium-Pro and Pentium-II Pentium III (P-III)—The Cpu of the Next Millennium Summary  Exercises

454 454 455 458 458 458 459 459 460 460 461 462 463 464 464

Chapter 12:  Pentium 4—Processor of the New Millennium   465 12.1  Genesis of Birth of Pentium 4 12.2  Salient Features of Pentium 4 12.3  Netburst Microarchitecture for Pentium 4 12.4 Instruction Translation Lookaside Buffer (Itlb) and Branch Prediction 12.5  Why out of order Execution 12.6  Rapid Execution Module 12.7  Memory Subsystem 12.8  Hyperthreading Technology 12.9  Hyperthreading in Pentium 12.10  Extended Instruction Set in Advanced Pentium Processors 12.11  Instruction Set Summary 12.12  Need for Formal Verification Summary  Exercises

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465 466 466 470 471 472 472 473 474 476 480 489 490 490

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xi

Chapter 13:  Risc Architecture—An Overview   491 13.1  13.2  13.3  13.4  13.5  13.6  13.7  13.8 

A Short History of Risc Processors Hybrid Architecture—Risc and Cisc Convergence The Advantages of Risc Basic Features of Risc Processors Design Issues of Risc Processors Performance Issues in Pipelined Systems Architecture of Some Risc Processors Discussion on Some Risc Architectures Summary  Exercises

491 492 492 493 493 495 497 506 506 507

Chapter 14:  Microprocessor-Based Aluminium Smelter Control   509 14.1  General Process Description of an Aluminium Smelter 14.2  Normal Control of Electrolysis Cell 14.3  Cell Abnormalities on an Aluminium Smelter 14.4 Brief Description of the Control Laws for Abnormal Cells 14.5  Salient Issues in Design 14.6  Smelter Controller Hardware 14.7  Control Algorithm Summary  Chapter 15:  Design of a Microprocessor Based Pattern Scanner System 15.1  15.2  15.3  15.4  15.5 

Organization of the Scanner System Description of the Scanning System Programmed Mode of Operation Memory Read/Write System and Start-Up Procedures Result and Discussion Summary 

Chapter 16:  Design of an Electronic Weighing Bridge 16.1  Design Issues 16.2  Software Development Summary 

509 510 511 511 512 512 513 517 519  520 520 522 526 526  528 529  529 544 553

Chapter 17:  An Introduction to Architecture and Programming 8051 and 80196 555  17.1  Intel’s Family of 8-Bit Microcontrollers 17.2  Architecture of 8051 17.3  Signal Descriptions of 8051 17.4  Register Set of 8051 17.5 Important Operational Features of 8051—Programme Status Word (Psw)

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556 557 559 561 562

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17.6  17.7  17.8  17.9  17.10  17.11 

Memory and I/O Addressing by 8051 Interrupts and Stack of 8051 Addressing Modes of 8051 8051 Instruction Set Programming Examples Intel’s16-Bit Microcontroller Family Mcs-96 Summary  Exercises

Chapter 18:  8051 Peripherals Interfacing 18.1  Interfacing with 8051 Ports 18.2  Designing with on Chip Timers 18.3  Interrupt Structure of 8051 18.4  Serial Communication Unit 18.5  Power Control Register (Pcon–Sfr Add 87h) 18.6 Design of a Microcontroller 8051 Based Length Measurement System for Continuously Rollingcloth or Paper Summary  Exercises Appendix A Appendix B Index

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563 566 567 569 578 582 590 591 593  593 621 632 641 650 651 656 656 659 669 685

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