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Idea Transcript
Data Pack
1502322217
Issued November 2005
IC timers 555 and 556
Data Sheet A range of IC timers suitable for monostable or astable operation. In the monostable mode these timers are capable of producing accurate delays over a very wide range. In the astable mode a wide frequency coverage is coupled with variable duty cycle capability. These versatile devices provide effective solutions for many timing and pulse circuit applications. The 556 timer is a dual version of the 555 single timer. The C-MOS versions offer improved characteristics for particular applications. For further information on 555 timers and their applications, please refer to the Technical Library section of the current RS catalogue for suitable reference books.
Typical Absolute maximum ratings bipolar Supply voltage _____________________________+18V Output current ____________________________200mA Power dissipation_________________________600mW Operating temperature _________________0 to +70°C Storage temperature ________________–65 to +150°C Lead temperature (60 sec)_________________+300°C
Trigger 2 Output 3
8 VCC
555
Reset 4
● ● ● ●
Bipolar and C-MOS versions Low external component count Wide operating voltage range Low power and supply current.
Typical Absolute maximum ratings C-MOS
Supply voltage _____________________________+18V Output current ____________________________100mA Power dissipation, 555 ______________________200m W556 __________________300mW Operating temperature _________________0 to +70°C Storage temperature ________________-65 to +150°C Lead temperature (60 sec)_________________+300°C Note:
Due to the SCR structure inherent in the C–MOS process used to fabricate these devices, connecting any terminal to a voltage greater than V+ +0.3V or less than V– -0.3V may cause destructive latchup. For this reason it is recommended that no inputs from external sources not operating from the same power supply be applied to the device before its power supply is established. In multiple systems, the supply of the C-MOSIC must be turned on first.
C-MOS pin out diagrams
Bipolar pin out diagrams
Ground 1.
Features
V - 1.
7 Discharge
Trigger 2
6 Threshold
Output 3
5 Control voltage
555
Reset 4
TOP VIEW
7 Discharge 6 Threshold 5 Control voltage
TOP VIEW
14 VCC
Discharge 1.
8 V+
14 V +
Discharge 1.
Threshold 2
13 Discharge
Threshold 2
13 Discharge
Control voltage 3
12 Threshold
Control voltage 3
12 Threshold
Reset 4
556
11 Control voltage
Reset 4
556
11 Control voltage
Output 5
10 Reset
Output 5
10 Reset
Trigger 6
9 Output
Trigger 6
9 Output
Ground 7
8 Trigger
V- 7
8 Trigger
TOP VIEW
TOP VIEW
1502322217 Figure 1 Schematic diagrams
V
Control voltage
CC
V R Comparator
Threshold
Ref Reset
Threshold
R
+ -
R Comparator
Trigger
R
Output Drivers
Comparator Reset A
Control voltage
Output Discharge
R
n
+ -
Flip - Flop
Comparator B
R
V-
Output Stage
CMOS Ground
Output Bi polar
Figure 2 Basic modes of operation Astable
Monostable
R
V A
CC or V
Reset 8 4 7 Threshold 2 Discharge 3 Trigger
6 Trigger
5 C
+ Pin numbers shown for 555 timers
R
V
CC or V
A 8 7 Discharge Trigger 6 Threshold
Output
Reset 4 3 Output
2
R
B 5
1
1
10n C
OV or V -
10n OV or V -
Figure 3 Load connection options Current Sink:
Current Source:
V
CC or V
V
+
CC or V
Load Output
I Sink I Source Output
Load OV or V -
2
OV or V -
+
+
1502322217 Operation Trigger input This input is used to initiate a monostable timing period. Triggering occurs on the negative going edge AB of the pulse shown in the diagram below, at a voltage level less that 1⁄3 of the VCC or V+ supply rail. The trigger pin must be returned to a level above 1⁄3 of the OV or V– supply rail before the end of the set timing period ‘T’. Should the trigger pulse interval ‘t’ be greater than the timing period ‘T’ then the output will remain in the active state (output high) for time ‘t’. Once triggered the trigger input is disabled and any trigger pulses occurring during the timing period ‘T’ have no effect on the set time. The necessity to return the trigger input to a voltage above 1⁄3 of the OV or V– rail and because the trigger input impedance is very high and hence susceptible to external noise, a.c. coupling of this pin is desirable. The figure below shows an arrangement for a.c. coupling of the trigger input. Figure 4a
VCC or V + 1/ VCC or V + 2
OV or V
A
-
B
t Edge AB triggers circuit
Figure 4b VCC or V +
Figure 5 Reset input VCC or V +
Reset
OV or V Normally biased to Vss or V + Connection to OV or V - causes reset operation
Control voltage As can be seen from the timer schematics on Page 2 the open circuit voltage at the control pin is set at 2⁄3 VCC or V+ by the internal resistors R. This resistor network sets the threshold comparator trip level at 2⁄3 supply and the trigger comparator at 1⁄3 supply. By imposing an external voltage on this pin the comparator reference levels may be shifted above or below the nominal levels hence affecting the timing in both the monostable and astable modes. In the monostable mode this pin can be swung between 45% to 90% of VCC or V+. In the astable mode a variation of 33% to 100% of the supply rail is possible. This feature extends the versatility of the timer to voltage controlled oscillators, pulse width modulators etc. For applications where this facility is not required the control voltage terminal should be decoupled to OV by a 10nF capacitor. The C-MOS IC’s, in most applications, will not require the control voltage terminal to be decoupled and should be left unconnected. Output The output voltage dependence on load current in sink and source modes is shown in Figure 2.
10k
10k
Reset input The reset function is used to return the timer out-put to the steady state (output low) when interruption of a monostable timing period is required. When not required the reset should be connected to VCC or V+. This avoids a false reset occurring.
trigger I/P 1n OV or V
-
a.c.coupling of trigger input
The minimum pulse width required for triggering and propagation delay versus voltage of trigger pulse are shown in Figure 6 for both the bipolar and C-Mos timers.
Timing capacitor - Important The capacitor employed must have a leakage current less than 0.1 Ith for satisfactory operation. Suitable types are silvered mica, polycarbonate, polystyrene, polypropylene, but not ceramic disc which are unstable in capacitance for RC network applications, or electrolytics due to high leakage current.
Technical hints The bipolar timers have a ‘totem pole’ type outputstage and during switching, large current spikes can appear on the supply line. Effective by-passing is necessary to eliminate noise retriggering the input and a 47µF tantalum capacitor mounted close to the device supply pins is suggested.To prevent the possibility of double triggering when driving TTL loads a 1nF capacitor connected between the timer output and ground should be found suitable.
Figure 6 Timing modes
Monostable mode
TIME
T
Applications Figure 8 Time delay Astable mode VCC or V +
47 μ T1
TIME
T2
OV or V -
The minimum recommended values for the timing resistors are RA= 5kΩ & RB = 3kΩ. These values are consistent with reliable operation at extremes of supply voltage, however, at inter-mediate levels lower value resistors may prove satisfactory. The maximum value of these resistors is governed by the typical value of threshold current and varies for each of the timers. Ω RAmax. or (RA+ RB)max. = 0.33Vs
8 RESET
START
4
2
555 OR C-MOS 555
OV or V -
TO LOAD
3
6 7 5
1
10n
OV or V -
1th x 10–9 where Vs = VCC or V+ to V– in volts Ith= Threshold current in nA for the timer IC. The duty cycle in the astable mode is: T1 RA+ RB = x100% T1+ T2 RA+ 2RB The minimum duty cycle using the recommended values is approximately 62%. By adding a diode across RB the charging path for the timing capacitor C changes from (RA+ RB) to (RA+ D1) hence t1 1ms.
Rpm 600 1200 2400 3600 6000
RA
RL
To calibrate: adjust VR1 for known reading against signal generator using circuit shown and values in table.
Figure 18a Interface with inductive proximity detector
C OV or V -
MODULATION INPUT
Disc (non Metalic)
Figure 17a Tachometer circuit
VS = + 24V
Metal foil VS
RS = 470R + VS
RS +VS
+ 9V1 1μ 12k
8
9V1 400mW
4
10k + 9V1
7 1k
6 2 1
Grey
4k7
A
5
47n +
4V3 400mW
100n
1N4148
VR1
1N4148 A
10k
Red
3
555
470n
Black
100n
Proximity detector 305-973
0 to 1mA
OV
0V
OV
Figure 17b Calibration interface + 9V1 10k
22k
1N4148
Figure 18b Interface for use with slotted opto switch
A
47n From sig gen 10V peak to peak
Disc VS = + 12V RS = 82R +VS 10k
10μ
+ 9V1
BC107
IN4148
270B Slot
10k
Disc
12k
10k
OV
1N4148
A 47n
Slotted opto switch 306-061
OV
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