MODULE PROFORMA Full module title: Digital System Design and Implementation Module code: 5ELEN002W
Credit level: 5
UK credit value: 20
ECTS value: 10
Length: Year Long
Faculty and Department: Science and Technology, Department of Engineering Module Leader(s): Extension:
Izzet kale
65157
Email:
[email protected]
Host course and course leader: BEng Electronic Engineering BEng Electronic and Electrical Engineering BEng Computer Systems and Robotics BSc Electronic Engineering BSc Computer Systems Engineering Biomedical Electronic and Instrumentation Engineering Status: BEng Electronic Engineering (Core) BEng Electronic and Electrical Engineering (Core) BEng Computer Systems and Robotics (Core) BSc Electronic Engineering (Core) BSc Computer Systems Engineering (Core) Biomedical Electronic and Instrumentation Engineering (Core) Subject Board: Engineering Level 5 Pre-requisites: Pass in: 4ELEN002W Digital Systems, or 4NTCM001W Digital Principles
Co-requisites: None
Study abroad: N/A Special features: None Access restrictions: Not suitable for study abroad students. Are the module learning outcomes delivered, assessed or supported through an arrangement with an organisation(s) other than the University of Westminster.
No
Summary of module content Students on this module will be introduced to simple custom and semicustom CMOS design building blocks leading to advanced programmable digital design through VHDL on FPGAs providing the participants with a full design cycle experience from initial specification to design capture in VHDL, simulation, synthesis and test of the synthesized net-list on FPGA development boards in real-time with simple custom and core processors.
Learning outcomes By the end of the module the successful student will be able to: LO1.
design digital full-custom CMOS building block circuits at the transistor level including static CMOS logic circuits, memory elements (such as latches, flip flops and registers) and arithmetic circuits;
LO2.
analyse, design, simulate, implement and evaluate FPGA based digital circuits, sub-systems and systems at the behavioural and structural RTL levels deploying VHDL;
LO3.
apply concepts of synthesisable VHDL coding with test benches to the design and evaluation of digital systems and write VHDL code to undertake conformance testing to specification via simulation;
LO4.
assess, design, simulate and implement digital processing systems with custom and core based building blocks employing high-level VHDL based tools targeting to FPGAs and FPGA prototyping, examination, evaluation and testing of a hardware processor project;
LO5.
work with others in a team, make informed choices regarding specification of sub-systems within an integrated electronic system; question and communicate technical ideas individually and as a group, orally and in writing;
Course outcomes the module contributes to: BEng Electronic Engineering
LE5.1 LE5.2 LE5.4 LE5.5 LE5.6
BEng Electronic and Electrical Engineering
LL5.1
BEng Computer Systems and Robotics
LR5.1 LR5.2 LR5.4 LR5.5 LR5.6
BSc Electronic Engineering
LS5.1 LS5.2 LS5.4 LS5.5 LS5.6
BSc Computer Systems Engineering
LC5.1 LC5.3 LC5.4 LC5.5 LC5.6
LL5.2
Biomedical Electronic and Instrumentation Engineering LB5.1
LL5.4
LL5.5
LL5.6
LB5.2 LB5.4 LB5.5
Indicative syllabus content As this is a project based module it will be delivered through the complete design and implementation of a digital system targeting to an FPGA. The design exercise will normally consist of three phases. In order to balance the effort needed for each of the three stages the complexity of the designs will increase in accordance with the design entry level and tools used. In each of these phases students will work in a team of three to produce a sub-block of a digital integrated circuits (typically a digital signal processing block) targeting to an FPGA implementation at the HDL level using a VHDL based design capture environment and design tools, capturing the design using the schematic based as well as the text based VHDL approaches and finalising the overall system design by assembling the individual sub-system blocks designed in the previous stages respectively. Once the complete design is assembled, thorough simulation testing/verification and synthesis and downloading onto an FPGA will follow. This will give the students the experience of going through the whole design cycle from specification to implementation and to simulation testing/verification and real world testing. The primary objectives of this project are the design and implementation of a digital system, comprising of sub-systems targeted to an FPGA and the introduction of VHDL and VHDL based design capture and FPGA based prototyping approaches/environments. The sub-systems to be implemented include adders, memories (FIFO, LIFO, RAM, ROM), registers, counters (PRBS generators, ring counters, up/down counters), arithmetic units and serial to parallel converters. The VHDL language and its constructs for basic design capture at the behavioural as well as the synthesisable structural RTL levels will be introduced.
The design seminars will cover the following topics:The MOS transistor: PMOS and NMOS devices; device structure; and operation, digital logic design in CMOS and VHDL: static logic; Programmable Logic Arrays (PLA), Field Programmable Gate Arrays (FPGAs). Sequential Circuits: two-phase clocks; transparent latches; non-transparent flip-flops; preset and clear;. Physical implementation and simulation: design tools; FPGA Advantage; VHDL; Modelsim; Precision; Xilinx FPGA device families and their constraints and uses. The VHDL language: introduction to the concept of hardware description languages specialising in VHDL; behavioural and structural RTL synthesizable VHDL; test-benches in VHDL; use of on-chip embedded core blocks such as memories, multipliers, ADCs and DACs; synthesizing digital designs ready for prototyping on FPGA development boards. Functional blocks in VHDL: transparent and non-transparent latches, flip-flops and registers, shift registers, SIPO, PISO, up/down counters, comparators, multiplexers, decoders, demultiplexers, ROMs, RAMs, VHDL based simple FSM design simulation and implementation targeting to FPGAs;
Teaching and learning methods Students attend a weekly 2 hour design lecture or seminar and a supervised 3-hour design/laboratory workshop to help you learn skills needed for the project. In addition to these timetabled hours, there is a considerable amount of contact between staff and students while project work is undertaken. For the project work, the class is divided into small teams (typically three members), which have to design, simulate and real-time test on an FPGA Development System, a non-trivial digital-electronic system. The teams are given a design brief and specification, to which they add their own intellectual property. Design work progresses with support from face-to-face surgeries, lectures and seminars. Activity type
Category
Student learning and teaching hours*
Lecture Seminar Tutorial Project supervisor Demonstration Practical Classes and workshops Supervised time in studio/workshop Fieldwork External visits Work based learning Total Scheduled
Scheduled Scheduled Scheduled Scheduled Scheduled Scheduled Scheduled Scheduled Scheduled Scheduled
38 8
Placement Independent study Total student learning and teaching hours
Placement Independent
18
64
136 200
*the hours per activity type are indicative and subject to change. During independent study time, the student will typically be expected to undertake extra study reading the lecture material provided and referred to during the lectures (35 hours); and within a group, allocate tasks, specify, design, model, simulate, build and test the hardware (70 hours) much of this time to be spent in the open-access laboratories. It is envisaged that the remaining time is used preparing for face to face sessions, software/hardware demonstrations, revising for tests and documentation of their design.
Assessment rationale Assessment covers both group and individual aspects, so students must demonstrate individual competence as well as being assessed as part of an effective team. The group assessment is based on the project construction and performance, the organisation and functioning of the team during the project, the written presentation of the results and responses to questioning. In Class tests are taken under exam conditions assess understanding and knowledge of the syllabus as the module progresses. Scripts are marked with feedback provided to assist learning. Assessment of the project work measures students’ collective ability to work together to design, model, simulate, build and debug digital electronic circuits. Formative assessment will be implemented by students taking practice tests, laboratory sessions and documented demonstrations whose marking will not contribute to their module marks but which will provide feedback on their strengths and weaknesses in preparation for the later summative assessments.
Assessment criteria To pass the module, the student must demonstrate basic competence in using the skills and methods taught. To achieve higher marks, the student must be able to select and apply these skills more widely and in different ways. The extent to which the student has demonstrated achievement in LOs 1 and 2 is evaluated through written test assessments including formative tests. The extent to which the student has demonstrated achievement of LOs 3, 4 and 5 is evaluated in the laboratory through demonstrations of their project work and their submitted report documenting the design decisions and achievements of the group.
Assessment methods and weightings
Assessment name
Weighting %
Qualifying mark %
Qualifying set
Assessment type (e.g. essay, presentation, open exam or closed exam)
Final Report (group aspect)
12
35
C
Coursework
Laboratory Demonstration (group aspect)
28
35
C
Practical
Test (Individual aspect)
60
35
In Class Test
In addition to the summative assessments, a number of formative tasks are provided. These provide practice and feedback of test performance (two formative tests and phase demonstrations as above) as well as opportunities for face to face software/hardware discussions for critical and constructive appraisal of the group’s work.
Synoptic assessment This module draws upon technical skills in digital electronics and applications of mathematical analysis as well as group-working skills being learned elsewhere in the course. By building on and applying these, the important links between analytical modelling, teamwork and transferable skills and their application to a significant piece of technical project work is emphasised. This module therefore engenders synoptic learning and its assessment is inherently synoptic.
Sources Essential reading list Grout, I., Digital Systems Design with FPGAs and CPLDs, Newens, 2011, ISBN: 008055850X, 9780080558509. Mano, M. M. and M. D. Ciletti, Digital Design, Pearson Higher Education, 5th Edition, 2012, ISBN: 0133072703, 9780133072709. Meyer-Baese, U., Digital Signal Processing with Field Programmable Gate Arrays, Springer, 3rd Edition, ISBN 3540211195, ISBN-10: 3540726128, ISBN-13: 978-3540726128, 2007. Pedroni, V. A., Circuit Design With VHDL, MIT Press, ISBN 0-262-16224-5, 2004. Weste, N. and K. Eshraghian, Principles of CMOS VLSI Design, A Systems Perspective, Addison Wesley, 2nd Edition, 1994. Weste, N. and D. Harris, CMOS VLSI Design, A Circuits and Systems Perspective, Pearson Higher Education, 4th Edition, 2011, ISBN: 0133001474, 9780133001471. Zwolinski, M., Digital System Design With VHDL, 2nd Ed. Illustrated, Pearson Education, 2003, ISBN: 013039985X, 9780130399854.
On-line References Course notes available from module Blackboard site. Up-to-date information about this module, including the module schedule, can be found on Blackboard (under this module's code). The site will contain additional material and/or links to further information. Mentor Graphics, FPGA Advantage and Modelsim Software Environment
Date of initial validation: Dates of approved modifications: Date of re-validation/review: