ELE432 - Hacettepe University [PDF]

Hardware Design with RTL VHDL. Pseudocode. Datapath. Controller. Block diagram. Block diagram. State diagram or ASM char

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ELE432 ADVANCED DIGITAL DESIGN HACETTEPE UNIVERSITY Controller Design - Finite State Machines Based on Lectures from George Mason and CMU

Suggested Readings • P. Chu, FPGA Prototyping by VHDL Examples • Chapter 5, FSM • S. Brown and Z. Vranesic, Fundamentals of Digital Logic with VHDL Design • Chapter 8, Synchronous Sequential Circuits • Sections 8.1-8.5 • Chapter 8.10, Algorithmic State Machine

Datapath vs. Controller

Structure of a Typical Digital System Data Inputs

Control Inputs Control Signals

Datapath (Execution Unit)

Controller (Control Unit) Status Signals

Data Outputs

Status Outputs

Datapath (Execution Unit) • Manipulates and processes data • Performs arithmetic and logic operations, shifting, and other data-processing tasks • Composed of registers, gates, multiplexers, decoders, adders, comparators, ALUs, etc. • Provides all necessary resources and interconnects among them to perform specified task • Interprets control signals from the Controller and generates status signals for the Controller

Controller (Control Unit) • Controls data movements in the Datapath by switching multiplexers and enabling or disabling resources Example: enable signals for registers Example: control signals for muxes • Provides signals to activate various processing tasks in the Datapath • Determines the sequence the operations performed by Datapath • Follows Some ‘Program’ or Schedule

Controller • Controller can be programmable or non-programmable • Programmable • Has a program counter which points to next instruction • Instructions are held in a RAM or ROM externally • Microprocessor is an example of programmable controller • Non-Programmable • Once designed, implements the same functionality • Another term is a “hardwired state machine” or “hardwired instructions” (THIS WEEK)

Finite State Machines • Digital Systems and especially their Controllers can be described as Finite State Machines (FSMs) • FSM is a mathematical model of an entity that describes its behavior as a result of its past history and current inputs. • Finite State Machines can be represented using • State Diagrams and State Tables - suitable for simple digital systems with a relatively few inputs and outputs • Algorithmic State Machine (ASM) Charts - suitable for complex digital systems with a large number of inputs and outputs

• All these descriptions can be easily translated to the corresponding synthesizable VHDL code

Hardware Design with RTL VHDL Interface

Pseudocode

Controller

Datapath Block diagram

VHDL code

Block diagram

VHDL code

State diagram or ASM chart

VHDL code

Finite State Machines Refresher

Finite State Machines (FSMs) • Any Circuit with Memory Is a Finite State Machine • Even computers can be viewed as huge FSMs

• Design of an FSM Involves • Defining states • Defining transitions between states • Optimization / minimization

• Manual Optimization/Minimization Is Practical for Small FSMs Only

Moore FSM • Output Is a Function of a Present State Only

Inputs

Next State function Next State

clock reset

Present State

Present State register

Output function

Outputs

Moore Machine : state diagram transition condition 1 state 1 / output 1

transition condition 2

state 2 / output 2

Mealy FSM • Output Is a Function of a Present State and Inputs

Inputs

Next State function Next State

clock reset

Present State

Present State register

Output function

Outputs

Mealy Machine :state diagram transition condition 1 / output 1 state 2

state 1 transition condition 2 / output 2

Moore vs. Mealy FSM • Moore and Mealy FSMs Can Be Functionally Equivalent • Equivalent Mealy FSM can be derived from Moore FSM and vice versa

• Mealy FSM Has Richer Description and Usually Requires Smaller Number of States • Smaller circuit area

• Mealy FSM Computes Outputs as soon as Inputs Change • Mealy FSM responds one clock cycle sooner than equivalent Moore FSM

• Moore FSM Has No Combinational Path Between Inputs and Outputs • Moore FSM is more likely to have a shorter critical path

Which Way to Go? Mealy FSM

Moore FSM

Fewer states Lower Area Responds one clock cycle earlier

Safer. Less likely to affect the critical path.

Moore FSM - Sequence “10” • Moore FSM that Recognizes Sequence “10” 0

1 S0 / 0

1

reset Meaning of states:

S0: No elements of the sequence observed

0 S1 / 0

0 S1: “1” observed

1

S2 / 1

S2: “10” observed

Mealy FSM - Sequence “10” • Mealy FSM that Recognizes Sequence “10” 0/0

1/0

S0 reset

1/0 S1

0/1

Moore & Mealy FSMs – Sequence “10” clock 0

1

0

0

0

S0

S1

S2

S0

S0

S0

S1

S0

S0

S0

input Moore Mealy

Ex:Moore Machine State Graph and Table • Easy to convert state graph to state table • Moore machine note output is function of the state

9/2/2012 – ECE 3561 Lect 7

Copyright 2012 - Joanne DeGroat, ECE, OSU

21

Ex:Mealy Machine State Graph and Table • Mealy machine state graph and state table • In Mealy machine the output is a function of the state and the current input

9/2/2012 – ECE 3561 Lect 7

Copyright 2012 - Joanne DeGroat, ECE, OSU

22

FSMs in VHDL • Finite State Machines can be easily described with processes • Synthesis Tools Understand FSM Description if Certain Rules Are Followed • State transitions should be described in a process sensitive to clock and asynchronous reset signals only • Output function described using rules for combinational logic, i.e. as concurrent statements or a process with all inputs in the sensitivity list

Moore FSM – coding style 1 process(clock, reset) Inputs

Next State function Next State

clock reset

concurrent statements

Present State Register

Present State

Output function

Outputs

Mealy FSM – coding style 1 process(clock, reset) Inputs

Next State function Next State

clock reset

concurrent statements

Present State

Present State Register

Output function

Outputs

Moore FSM in VHDL Sequence “10” • Moore FSM that Recognizes Sequence “10” TYPE state IS (S0, S1, S2); SIGNAL Moore_state: state;

0

1 S0 / 0

reset

1

0 S1 / 0

0

1

S2 /

U_Moore: PROCESS (clock, reset) BEGIN IF(reset = ‘1’) THEN Moore_state IF input = ‘1’ THEN Moore_state IF w = '0' THEN y

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