ETS 2013 - IEEE European Test Symposium

Loading...
Corporate Sponsors

Corporate Sponsors

General Info Technical Program Papers Vendor Sessions Fringe Workshops

Tutorial I: Effective post-silicon validation

Test Spring School Monday, May 27: 14:00-16:00, 16:20-18:30 Conference center of the Pope’s Palace of Avignon Speaker: Prof. Subhasish Mitra

Fringe Meetings Social Activities

Dept. of Electrical Engineering and Dept. of Computer Science Stanford University Gates 334, 353 Serra Mall, Stanford, CA, 94305 Email: [email protected] Phone: 650-724-1915 http://www.stanford.edu/~subh

Local Information Registration

Latest News Symposium avalaible

booklet

is

now

Invited Distinguished Speaker from Group of Dr. Albert FERT, Nobel Prize Laureate in Physics, 2007. See the DETMET program here

ETS on-line registration is now closed. Only on-site registration will be possible, starting from Monday, May 27th, at 13h00.

Abstract Hardware failures are a growing concern as electronic systems become more complex, interconnected, and pervasive. The complexity challenge is further exacerbated by new ways of improving energy efficiency of electronic systems in the absence of CMOS (Dennard) scaling: increasing amounts of cores, uncore components, and accelerators; increasing degrees of adaptivity; and, increasing levels of heterogeneous integration. All these features and their complex interactions make future systems highly vulnerable to design flaws (bugs) that can jeopardize correct system operation and/or introduce security vulnerabilities. Existing validation methods barely cope with today’s complexity. Traditional pre-silicon verification alone is no longer adequate because it is nearly impossible to detect and fix all bugs before manufacture. Postsilicon validation involves operating manufactured ICs in actual application environments to detect and fix bugs. Existing post-silicon practices are ad-hoc, and their costs are rising faster than design cost. Post-silicon validation involves four major steps: 1. Detecting a problem by running test programs, such as OS, games or functional tests, until a system malfunction is observed. 2. Localizing the problem to a small region from the observed system malfunction. 3. Identifying the root cause of the problem. 4. Fixing or bypassing the problem.

Presentation slides in ppt format must be uploaded though the MOLE System web site before May 20, 2013

Effective post-silicon validation requires a radical departure from today’s ad-hoc practices to structured techniques that are inspired by advances in design verification, formal methods, manufacturing testing, and robust system design with built-in resilience to failures. Another highly important aspect is the creation of benchmarks that can drive quantitative evaluation of new postsilicon validation techniques.

Bio Professor Subhasish Mitra directs the Robust Systems Group in the Department of Electrical Engineering and the Department of Computer Science of Stanford University, where he is the Chambers Faculty Scholar of Engineering. Prior to joining Stanford, he was a Principal Engineer at Intel Corporation. Prof. Mitra’s research interests include robust system design, VLSI design, CAD, validation and test, and emerging nanotechnologies. His X-Compact technique for test compression has been used in more than 50 Intel products, and has influenced major Electronic Design Automation tools. The IFRA technology for post-silicon validation, created jointly with his student, was characterized as “a breakthrough” in a Research Highlight in the Communications of the ACM. His work on the first demonstration of carbon nanotube imperfection-immune digital VLSI, jointly with his students and collaborators, was selected by the NSF as a Research Highlight to the US Congress, and was highlighted as “a significant breakthrough” by the Semiconductor Research Corporation, the MIT Technology Review, the New York Times, and several others. Prof. Mitra's major honors include the Presidential Early Career Award for Scientists and Engineers from the White House, the highest US honor for early-career outstanding scientists and engineers, Terman Fellowship, IEEE CAS/CEDA Pederson Award for the IEEE Trans. CAD Best Paper, and the Intel Achievement Award, Intel’s highest corporate honor. He and his students presented award-winning papers at several major conferences: IEEE/ACM Design Automation Conference, IEEE International Test Conference, IEEE VLSI Test Symposium, and the Symposium on VLSI Technology. Prof. Mitra has served on numerous conference committees and journal editorial boards. He recently served on DARPA’s Information Science and Technology Board as an invited member.

Tutorial II: Design, Test and Debug of Printed Circuit Assemblies Monday, May 27: 14:00-16:00, 16:20-18:30 Conference center of the Pope’s Palace of Avignon Speaker: Bill Eklow

Distinguished Engineer Cisco Systems, Inc. 80 W. Tasman Drive San Jose, CA,95124 USA Email: [email protected] Phone: +1 408 527 0512 Fax: +1 408 527 0512

Speaker: Brice Achkir

Distinguished Engineer Cisco Systems, Inc. 80 W. Tasman Drive San Jose, CA 95124 USA Email: [email protected] Phone: +1 408 525 6278 Fax: +1 408 525 6278

Abstract While integration is forcing more and more logic into the components, being able to extract all of the data that is being generated inside the component and delivering it to another component, board or system is critical to the operation of the system/network. The bandwidth at which data is generated or required is challenging board and system designers. Data is being driven across networks at tens of Gigabits per second. These speeds will increase to hundreds of Gigabits per second in the next 3 – 5 years. In addition, the massive amounts of logic integration, enabled by technology scaling, is creating unmanageable complexity at the component level. Verifying that components meet their specifications is becoming more and more difficult. Testing these components in a board or system environment is even more challenging. Given that much of the logic/memory integration will be incorporated into the components, the design aspect of this lecture will focus primarily on delivering high speed signals on board from component to component and from component to external interfaces. Significant attention will be given to signal and power integrity and their impact on performance. In addition, new advances such as silicon photonics and optical interconnects will also be discussed along with their ramifications to board level design and system level performance. From a test perspective, the lecture will cover defects and failures in both digital (logic) and analog (high speed signalling) circuits. The lecture will discuss how defects are manifested into failures and what can be done to detect failures and isolate them to the corresponding defect. The lecture will look at an “Industry Best Practices” test flow and talk about test challenges which are a result of logic complexity and ultra-high data rates. The lecture will consider challenges in defect detection, localization and isolation from a system level to a component level (all of these impact the quality and reliability of the printed circuit assembly). Innovative approaches to debug and diagnosis will also be covered.

Bio Bill Eklow is a Distinguished Engineer at Cisco Systems, Inc. Bill’s areas of interest are: component test, board and system test and correlating board and system level failures to component defects. Bill is Chair of the IEEE 1149.6 Working Group and is an active member on the IEEE 1149.1 (Boundary-scan), P1687 (IJTAG), P1838 (3D Test Access) working groups. Bill is also the sub-group leader for the ITRS 3D Test Sub-group. Bill is a committee member for several conferences, workshops and symposia, including: International Test Conference, Board Test Workshop, 3D Test Workshop, Silicon Debug and Diagnosis Workshop, VLSI Test Symposium and ATE Vision Conference. Bill is an Eta Kappa Nu member, an IEEE Golden Core member and an IEEE Fellow. Brice Achkir is a Distinguished Engineer at Cisco Systems, focusing on high-speed architecture/design and signal integrity. His research interests include high-speed digital and mixed-signal designs, active and adaptive optics, and networking. He has also done research and development in optics design. With Cisco since 1999, he has previous experience with many companies such : ITF optical technologies, Beltron, SCI, IRH …. He holds BS, MS, and PhD degrees in applied physics, physics, and Electrical engineering.

For information about the website, please contact the webmaster Alberto Bosio

Loading...

ETS 2013 - IEEE European Test Symposium

Corporate Sponsors Corporate Sponsors General Info Technical Program Papers Vendor Sessions Fringe Workshops Tutorial I: Effective post-silicon val...

206KB Sizes 4 Downloads 10 Views

Recommend Documents

2013 IEEE International Symposium on Antennas - Proceedings.com
M. Tentzeris, Georgia Institute of Technology, United States. 103.6: A ...... Giselle M. Galvan-Tejada, Emmanuel Q. Duar

Postmodern Test Theory - ETS
Postmodern Test Theory. Robert J. Mislevy. The Gordon Commission on the Future of Assessment in Education — http://www

[IEEE 2006 IEEE MTT-S International Microwave Symposium Digest
Dec 14, 2016 - Finite Element Method Conformal Mapping 2D Quasi-static 2D FEM 3D FEM Quasi-static (QS) Eigenanalysis (EA

2016 IEEE International Symposium on Technologies for - IEEE-HST
May 10, 2016 - A MULTI-BIOMETRIC FEATURE-FUSION FRAMEWORK FOR IMPROVED UNI-MODAL AND MULTI-MODAL HUMAN IDENTIFICATION Da

Reducing Test Anxiety (PDF) - ETS
It sounds obvious enough, but a lot of people who have test anxiety deal with it by avoidance. They hope that if they av

HiSETTM Science Practice Test - ETS
This is a test of your skills in analyzing science information. Read each question and decide which of the four alternat

GRE Biology Practice Test - ETS
alternate format should contact the ETS Office of Disability Services at [email protected] For additional .... Fundamental

HiSET Test Taker Brochure - ETS
Study Companion — Use the Study Companion to familiarize yourself with the test content, test question formats and ava

[IEEE 2012 IEEE 20th International Symposium on Modelling, Analysis
Feb 19, 2017 - ... Technology Rochester, New York 14623 Email: [email protected] Shuaiwen Song SCAPE laboratory Virginia T

HiSET Mathematics Practice Test - ETS
Be sure that the number of the question you are answering matches the number of the row of answer choices you ... is $80