Frequency Response Controller Design M. Sami Fadali Professor of Electrical Engineering UNR 1
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Design Procedure
Frequency Response Design 1. Select
Advantage: Familiar design procedure.
and obtain the transfer function .
Disadvantages:
2. Bilinearly transform
1. Indirect design: controller distortion.
into
using
2. Requires experience. 3. Familiar criteria (PM, GM) have different values from their analog counterparts for the same performance.
MATLAB >> gd=c2d(g,T) >> d2c(gd,'tustin')
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Design Procedure (Cont.)
Design Specifications
3. Draw the Bode plot of , and use analog frequency response methods to design a controller that satisfies the frequency domain specifications
• PM, GM , BW • Use frequency response design procedures for analog systems (e.g. lag, lead, lag-lead).
4. Transform the controller back into the zplane using
= gain crossover (0 dB magnitude) frequency • BW increases with
5. Verify that the performance obtained is satisfactory. 5
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Solution
Example 6.15
• T = 0.1 s, obtain z-transfer function
Consider the cruise control system of Example 3.2, where the analog process is
Z • Bilinear transformation
Transform the corresponding to the -plane by considering both and . Evaluate the role of the sampling period by analyzing the corresponding Bode plots.
•
s, obtain z-transfer function
• Bilinear transformation 7
.
. 8
Bode Plots
,
&
Discussion For 2 • Pole in -plane at like the pole in the s-plane. does not (different • Have TF zero while frequency response from the analog system • Greater influence of the zero on the system dynamics when the sampling period is larger. • Distortion in the low frequency range is negligible. • Gain as goes to zero is unity as is the DC gain of the analog system.
1 2
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Example 6.16
Solution • For 10% overshoot,
DC motor speed control system: (type 0) analog plant has the transfer function
Design a digital controller by using frequency response methods to obtain: (i) zero steady-state error due to a unit step, (ii) an overshoot less than 10%, (iii) a settling time of about 1
Example 6.17 DC motor speed control system: (type 0) analog plant has the transfer function
Step Response System: Gcl Peak amplitude: 1.07 Overshoot (%): 7.17 At time (sec): 0.56
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System: Gcl Settling Time (sec): 0.818
Amplitude
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0
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Time (sec)
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Design a digital controller by using frequency response methods to obtain: (i) zero steady-state error due to a unit step, (ii) an overshoot less than 10%, (iii) a settling time of about 1 s Use
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Solution
Design
• TF of analog system, ADC and DAC
• Cancel two poles with zeros.
Z
• Add poles at zero and
. .
.
• Poles almost in the same locations as poles of . • Consider RHP zero at to make the gain crossover frequency about 5 rad/s.