Idea Transcript
US006115763A
United States Patent [19]
[11] Patent Number:
6,115,763
Douskey et al.
[45]
Sep. 5, 2000
[54]
Date of Patent:
MULTI-CORE CHIP PROVIDING EXTERNAL
5,969,538 10/1999 Whetsel ................................ .. 324/763
CORE ACCESS WITH REGULAR OPERATION FUNCTION INTERFACE AND PREDETERMINED SERVICE OPERATION SERVICES INTERFACE COMPRISING CORE INTERFACE UNITS AND MASTERS INTERFACE UNIT
5,974,578
10/1999
MiZokaWa et al. .
5,991,898
11/1999
Rajski
6,000,051
12/1999
Nadeau-Dostie et al. ............ .. 714/727
et
al.
...............
. 714/727 . . . . . ..
714/30
OTHER PUBLICATIONS
Chandramouu, R. et al., “Testing systems on a chip”, IEEE
Spectrum, (Nov., 1996), pp. 42—47. [75]
Day, L.L. et al., “Micro Token Ring”, IBM® Technical
Inventors: Steven Michael Douskey; Michael
Charles Cogswell; Guy Richard Currier; John Robert Elliott; Sharon Denos Vincent; James Maurice Wallin, all of Rochester; Paul Leonard Wiltgen, Kasson, all of Minn.
[73] Assignee: International Business Machines Corporation, Armonk, NY.
Filed:
(List continued on next page.) Primary Examiner—Thomas C. Lee Assistant Examiner—Tanh Nguyen Attorney, Agent, or Firm—Scott Stinebruner; Wood, Herron
[57]
ABSTRACT
Adata processing system, integrated circuit device, program
Mar. 5, 1998
[51]
Int. Cl.7 .......................... .. G06F 13/00; G06F 11/00;
[52]
US. Cl. ............................... .. 710/72; 710/20; 710/62;
[58]
Field of Search ....................... .. 395/183.06, 500.49;
G01R 31/28
714/30; 714/726; 714/727; 714/733; 714/734
714/726, 727, 733, 734, 30; 710/20, 21, 62, 72, 240, 244 [56]
485—486.
& Evans
[21] Appl. No.: 09/035,490 [22]
Disclosure Bulletin, vol. 37, No. 9, (Sep., 1994), pp.
References Cited U.S. PATENT DOCUMENTS
product, and method thereof utiliZe a service interface to provide external access to a plurality of cores integrated into an integrated circuit device. The service interface, Which may be utilized to perform external data transfer through a service access port in connection With a predetermined
service operation, is separate from any function interface that is utilized during regular operation of the device. The service interface includes a plurality of core interface units integrated With selected cores on the device and coupled to the service access port through a master interface unit that is con?gured to request at least one of the core interface units to initiate execution of a predetermined service operation. As such, a multitude of service operations may be initiated
4,639,919
1/1987 Chang et al. ........................... .. 371/27
5,640,337
6/1997 Huang et al. .
364/578
in any number of the cores through a common service access
5,668,817
9/1997 Adham ...................... .. 371/224
port Without occupying a large number of I/O pins and
5,724,502 5,768,152
3/1998 Cherichetti et al. 6/1998 Battaline et al.
Without necessitating interruption of the regular operation of
5,809,036
9/1998
Champlin
.........
.. 395/183.04 .. 364/551.01 . . . ..
5,848,264 12/1998 Baird et al. 5,862,152
the device.
371/2231
395/500
1/1999 Handly et al. ..................... .. 371/2232
67 Claims, 16 Drawing Sheets
5
15 Service
FSBa
\
Bus
6,115,763 Page 2 OTHER PUBLICATIONS
TeXas Instruments Incorporated, IEEE1149.1 (JTAG)
Boundary—Scan Logic Products Literature, SCTB042, Whetsel, Lee, Built—in Self—Test (BIST) Using Boundary Scan, Texas Instruments Incorporated, SCTA043A, (Dec.
(1996).
1996).
SN74ABT8996 10—Bit Addressable Scan Ports Multidro
Whetsel, Lee, Hierarchically Accessing 1149.1 Applications in a System Environment, Texas Instruments Incorporated,
SCTA033, Proceedings of International Test Conference,
TeXas
Instruments
Incorporated,
SN54ABT8996,
p—Addressable IEEE STD 1149.1 (JTAG) TAP Transceivers
Product Information, SCBS489B—Aug. 1994 (Rev. Dec. 1996), pp. 1—40. TeXas Intruments Incorporated, Data Formats, http://WW
Baltimore, MD (Oct. 17—21, 1993), IEEE reprinted With permission (1993), pp. 1—12.
W.ti.com/sc/docs/jtag/format.htm (doWnloaded Nov. 21,
TeXas Instrument Incorporated, ’ABT8996 Addressable
TeXas Instruments Incorporated, IEEE Std 1149.1 (JTAG)
Scan Port (ASP) Product Literature, (1996).
Testability Primer, Semiconductor Group (1997).
1997).
U.S. Patent
Sep. 5,2000
Sheet 1 0f 16
-
10
25
?goifessmg
\
Processor 4 \ ~
27
HO
‘
HO
4
Processor
'
4
7
System
Processor
Service '
/
16
Chip Set
14
20
Processor
26 ../
Chip Set
System
Chip Set
28
Bus
6,115,763
/15
Processor
18
12
19 /
Storage
3o
/
Memory
Unit
Controller
M36 32
‘ _
Mam
34’
Core
Memory
Core
e2
Core
e2
CIU /
e2
CIU /
//// // ///////
\ \ 51\
////// ////////
‘1g 55\ C'U \
CIU /
a
56
62
52
\
\
C 0 re
58
54
V MIU 15
SIU 58a
\
Service Processor '
54a
——>System '\\
Bus
2 9
U.S. Patent
Sep. 5,2000
6,115,763
Sheet 2 0f 16 8O
_
74\M
FlgI 3
\
:
:
“_. base addr
79
82
RESET
= base addr 1
Master Interface
EXIST _ ATTN
Unit
J
ER
CS‘ ‘
72
79
84
H
1
/
ABIST
:
C
'
3l
@5519
70/
:
:
Technofunc
86 CLKINTF
/76 ‘
‘
91:
WRITE
93\ 92\
ADDR
DATAGOOD
8/0
I
DATAIN
:
I
E
5
E
,
'
f
i
a
a
5
j
j
‘
/
Core
~ Interface
7
I
valid
9t
L
76/
IDLE
READ
= base addr 88
78
8/0
11
90:
' base addr
Unit
U.S. Patent
Sep. 5,2000
Sheet 3 0f 16
90: IDLE
READ
91\
WRITE
92:
f
93
I
ADDR
'
E
X 96
DATAOUT
fvalid :
1
IL.
\
valid
94
DATAGOOD
:
Fig.5
gfli IDLE
READ 91: E WRITE 9“ E 93 ADDR
5 \
'
96
f
DATAOUT
DATAGOOD 9E) 1, 95
DATAIN
I
Evalid
Fig. 6
6,115,763
U.S. Patent
Sep. 5,2000 I;
_
‘
'
Master
7- Interface
v
‘
LB'ST
UM‘
JTAG
Sheet 4 0f 16
4 /
\
BLOCKRESET
RUNTESTZI
1 0
System
»-
6,115,763
1
Bus
170 ABIST
Flg- 7 102
200
/
170/’
RUNTEST3
1
100/
MODE NT T1 RU ES
-
CLKINTF
RESET
106 “———_- PGOOD
H‘
|PLMODE(0:2) J Function
_
102
Flg. 9 System
\
110
DATAIN/ DATAOUT
JTAF"
CSI
L/og‘c
ljogic
Csl
7'
Bus
/
4
115
System
CSI Addr
CSI R/W
Decode
Controller \136
110
Bus
MMaddr
= TCK JTAG
SCaddr
- TMS Logic /
MMdatai
118
\\ 7 at"): ~> gidr
‘ Data
122
--—>
MUX
Bus
TDI
=
126 m
"
SCscanReg>-—l
-
Flg. 10 :ADDR
99 MMdatao
116 l
SCwrnte
130
=DATA'N
< TDO
SCread
100
Datga // 124 R >DATAOUT
I
MMwrite
\
120
,f
112 JTAG
132
‘ MUX -> |CReg#N
Bus REsEToPDoNE CLKOPDONE
144.2s\\ DONE
—~—> RETURN TO MAIN SEQ.
_
DATAOUT
MUX
180
ptlons
.
R99
DATA GOOD
182 cs1 R/W
READ
WRITE
Sequencer
MUX
Status
Reg
ADDR 186 FAIL BITS
DONE BITS
ABIST Control equence
IDLE RUNTEST2
MODE 178
DATAIN cs1 Bus
RUNTESTS
F|g_ 20
Core
U.S. Patent
Sep. 5,2000
174.1
\
Sheet 12 0f 16
6,115,763
IDLE 174
WRITE & RUNABIST
/
174.2
\
START
1743
_>DATAGOOD
WRITE
\
POLL1
Fig 21
READ&BOUNCE 174.4
\
CLKSON
————-——>DATAGOOD
READ 174.5 RUNBIST
ALLDONE & READ 174.6
\
POLL2 READ81BOUNCE
174.7
\
CLKSOFF
174.8
————>DATAGOOD
READ DONE
CLKSOFF
19o I
I
19o\ \
LABIST1
ABIST2
DONE1
170
I
ooo
DONE2
Fig. 22
ABISTn DONEn
187
I
l
l
a " °
DONE MASK
188
E
1 1
1875 182a
/
ALLDONE
U.S. Patent
DATAOUT =
Sep. 5,2000
209
Sheet 13 0f 16
214\ M
202
@
DATA
6,115,763
Options/21o Uxa Reg A
GOOD *~ 0R