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Idea Transcript
Objectives: 1. Multipliers: 1.1 Multiplication of two 2-bit numbers. 1.2 Combinational circuit of binary multiplier with more bits. 2. Decoders: 2.1) 2x4 decoder (Active-high). 2.2) Active-low decoders. 2.3) Decoders with enable inputs. 2.4) Three-to-eight-line decoder circuit. 2.5) Larger decoder circuit. 2.6) Combinational logic implementation.
1) Multipliers: Multiplication of binary numbers is performed in the same way as multiplication of decimal numbers: 1.1 Multiplication of two 2-bit numbers.
B1 A1 A0 B 1
A1 B 1 Possible Carry
C
3
B0
(Multiplicand)
A0
(Multiplier)
A0 B 0
Partial Product
A1 B 0 A0 B 1
A1 B 1
A B
C2
C1
1
A0 B 0
0
C
0
Final Product (the sum of the partial products)
Combinational circuit The multiplication of two bits such as and produces a 1 if both bits are 1; otherwise, it produces a 0, this is identical to an AND operation. The two partial products are added with two half-adder (HA) circuits (if there are more than two bits, we must use full adder (FA)). B0
A0
A 1 B1
HA
C
HA
C1
C2
3
C
0
Two-bit by Two-bit binary multilplier 1.2 Combinational circuit of binary multiplier with more bits. For bits multiplier and bits multiplicand, we need: AND gates. -bits adders to produce a product of bits. Example: - Create a logic circuit for
B
C
6
C
5
C 4C
3
3
A
C
B
2
B
2
A
2
C
1
B
0
1
A
0
1
C
0
Answer
Solution:
So: We need 12 AND gates and 2 four-bit adders to produce a product of seven bits: .
A2 B 3
0
A0 B 3
A0 B2
A0B1
A1 B 3
A1 B 2
A1B1
A1B 0
A2B 2
A2 B1
A2B 0
0
A B A B A 1
A B0 A 2
4-bit adder (Second adder)
C6
C5
3
A0 B 3
3
X3 2B2
1
2
A0 B2
A XB A
C4
2
2
X1
1
2
A0 B 0
4-bit adder (First adder)
B0
B0
1
C2
C3
A0
A0B1
B1
1
A
B0
Possible Carry
12 AND Gates
A2
B1 A1
B2
B3
C1
C0
Circuit Implementation: B0
1
A2
0
4-bit adder Sum and output carry
A0 A
B1 B2 B3
4-bit adder
C6
C5
C4
C
3
C2
C1
C
0
Select Lines (Control Word)
D0
S0
D1
2x4 Decoder
S1
D
2
D
3
Inputs Select Lines 0 0 1 1
0 1 0 1
Output Lines
2) Decoders Information is represented in digital system by binary codes. A binary code of bits is capable of representing up to distinct elements of coded information. A decoder is a combinational circuit that covers binary information from input lines to a maximum of unique output lines. The decoders are called line decoders, where (for example BCD-to-seven-segment decoder, decoder). The purpose of the decoders is to generate the (or fewer) minterms of input variables. Decoder is a circuit that allows us to activate an output line by specifying a control word; it is either active-high or active-low. o Active-high sets a particular output to logic 1. While remaining other outputs to logic 0. o Active-low sets a particular output to logic 0, other outputs to logic 1. 2.1) 2x4 decoder (Active-high) 1. 2. 3. 4.
Output Output Lines
0 0 0 0 0 1 1 0 Truth table
0 1 0 0
1 0 0 0
From truth table: Two inputs are decoded to 4 outputs. Each output represents one of the minterms of the three input variables. For each possible combination (input), there are 3 outputs that are equal to 0 and only one that is equal to 1.
S1
s0
s1
s0
D0
D1 D2 D3 Decoder Logic Circuit
2.2) Active-low decoders S1
s 1 s0
s0 Inputs Select Lines
D0
D1 D2 D3 Active-Low Decoder Logic Circuit
AND becomes NAND Complement
= = =
= + +
;
+
;
0 0 1 1
0 1 0 1
Output Output Lines 1 1 1 1 1 0 0 1 Truth table
1 0 1 1
0 1 1 1
2.3) Decoders with enable inputs Some decoders include one or more enable inputs to control the circuit operation. A two-to-four line decoder with an enable input constructed with NAND gate is the following: S1
Inputs
1 0 0 0 0
X 0 0 1 1
s1
s0
s0
D0
Output Output Lines X 1 1 0 1 1 1 1 1 0 1 0 1 0 1 Truth table
1 1 0 1 1
D1 1 0 1 1 1
D2 D3 E Active-Low Decoder Logic Circuit with enable input
The circuit operates with complemented output and a complemented enable input (Active-Low Enable): then the decoder is enabled. then the decoder is disabled. The enable input may be active with 0 or with a 1 signal. 2.4) Three-to-eight-line decoder circuit inputs 0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
outputs 0 1 0 1 0 1 0 1
1 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0
0 0 1 0 0 0 0 0
0 0 0 1 0 0 0 0
0 0 0 0 1 0 0 0
0 0 0 0 0 1 0 0
0 0 0 0 0 0 1 0
0 0 0 0 0 0 0 1
X X Y Y Z Z
D0 X Y Z
D1 X Y Z D2 XY Z D 3 X YZ
D4 X Y Z D5 X Y Z D 6 XY Z D 7 XYZ Decoder Logic Diagram
2.5) Larger decoder circuit. Decoders with enable inputs can be connected together to form a larger decoder circuit. To design a line decoder. Using two decoders with enable inputs, we do the following connection: When the top decoder is enable and the other is disable: The bottom decoder outputs are all and the top eight outputs generate minterms to . When the enable condition is reversed, the bottom decoder outputs generate minterms to . X
Y Z
3x8 Decoder
D0 D7
E
W
3x8 Decoder
E
D 8 D15
2.6) Combinational logic implementation: Since, a decoder provides the minterms of input, and any Boolean function can be expressed in sum-of-minterms form, A decoder that generates the minterms of the functions, together with an external OR gate that forms their logical sum, provides a hardware implementation of the function. In this way, any combinational circuit with inputs and outputs can be implemented using line decoder and OR gates. The procedure for implementing a combinational circuit by means of decoders and OR gates requires that the Boolean function for the circuit be expressed as a sum of minterms. Example:-Implementation a full-adder circuit using the decoders. From the truth table of the full adder, we obtain the functions for the sum and carry in sum-of-minterms form:
We have 3 inputs: so, we need a three-to-eight line decoder.