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2213 OSCILLOSCOPE SERVICE

INSTRUCTION

MANUAL

2213 Service

TA BLE O F CO N T EN TS Page

L IST OF I LLUST RATIO NS . . . . . . . . . . . . . . . . . iv LIST O F TA BLES . . . . . . . . . . . . . . . . . . . . . . . . ν OPERATO RS SA FE TY SUMMAR Y . . . . . . . . . . . . vi

S ERV ICING SA FE TY SUMMARY . . . . . . . . . . . . . vii

S E CTIO N 1 S PE CI F ICATION

I

NTROD UCTIO N . . . . . . . . . . . . . 1-1 ACCESSO R I ES. . . . . . . . . . . . . . . 1-1 PERF O RM ANCE CO N DITION S . . . 1-1 SECTIO N 2 OPERATING I NST RU CTIO NS PREP A R ATIO N F O R U S E . . . . . . . SA FE TY . . . . . . . . . . . . . . . . . L I NE VO LTAGE . . . . . . . . . . . P OWER CO R D . . . . . . . . . . . . . L I NE FU SE . . . . . . . . . . . . . . . CO NTRO LS, CO NNECTORS, AN D I N DICATO RS. . . . . . . . . . . . P OWER, DISPL AY, AN D PR OBE ADJU ST . . . . . . . . . . . . VERTICA L . . . . . . . . . . . . . . . H O R IZO NTA L . . . . . . . . . . . . . TR IGG ER . . . . . . . . . . . . . . . . RE AR PANEL . . . . . . . . . . . . . OPERATI NG CO NSIDER ATIO N S . . G RATIC ULE . . . . . . . . . . . . . . G ROUN DI NG . . . . . . . . . . . . . SIGNAL CO NNE CTIO N S . . . . . . I NPUT CO UPL I N G CA PACITOR PRE CH A RGI NG . . . . . . . . . . . . I N ST RUMENT COO L I NG . . . . . OSCI LL OSCO PE DISPL AYS. . . . . . NTROD U CTIO N . . . . . . . . . . . BAS EL I NE T R AC E . .. . . . . . . . . SIG N AL DISPLAY . . . . . . . . . . M AG N I F IED-SWEEP DISPLAY . . DEL AYE D-SWEEP DISPL AY . . . Χ-Υ DISPLAY . . . . . . . . . . . . .

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2-1 2-1 2-1 2-1 2-1

. . 2-3 . . . . . . . . .

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2-3 2-3 2-5 2-5 2-7 2-8 2-8 2-8 2-8

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2-8 2-9 2-9 2-9 2-9 2-9 2-10 2-10 2-10

TV SIGNAL DISPLAYS . . . . . . . . . . . 2-11

REV NOV 1981

Page SE CTIO N 3 THE ORY O F OPERATIO N

I

NTROD UCTIO N . . . . . . . . . . . . . G ENER AL DESC R I PTION . . . . . . . D E TAI LE D CI RCUIT DE SC R I PTION . . . . . . . . . . . . . . . VERTICAL ATTENUATO RS . . . In p ut Co u p ling . . . . . . . . . . . H ig h-Ζ Attenuato r . . . . . . . . . B uffer Amplifier a n d Low-Ζ Atte nuator . . . . . . . . . . . . . . Volts/Div Var Circuit and X1/X10 Amplifier . . . . . . . . . VERTICA L PREAMPS. . . . . . . . Chan nel 1 Vertical P ream plifier Channel 2 Vertical P reamplifier Internal Trigger P ickoff Amplifier. . . . . . . . . . . . . . . CHANNEL SW ITCH AN D VERTICA L O UTPU T . . . . . . . . Diode Gates . . . . . . . . . . . . . Delay L ine Driver . . . . . . . . . Delay L ine . . . . . . . . . . . . . . Vertical Out p ut Am plifier . . . . Chan nel Switch ing L ogic Circuit. . . . . . . . . . . . . . . . . Internal Trigger Switch ing L ogic . . . . . . . . . . . . . . . . . T R IGGER . . . . . . . . . . . . . . . . Internal Trigger Am p lifier . . . . Trigger Source-Switc hing Circuit. . . . . . . . . . . . . . . . . External Trigger Amplifier . . . A uto Trigger Circuit . . . . . . . . Trigger Level Comparator . . . . Inverting Am plifier an d TV T rigger Circuit . . . . . . . . . Sc h mitt T rigger Circ u it . . . . . . Au to B aseline Circuit . . . . . . . SWEEP G ENER ATOR AN D L OGIC . . . . . . . . . . . . . . . . . . Miller Swee p Ge nerator . . . . . Sweep L ogic . . . . . . . . . . . . . Delay Circuit . . . . . . . . . . . .

. . 3-1 . . 3-2 . . . .

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3-4 3-4 3-4 3-4

. . 3-5 . . . .

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3-6 3-6 3-6 3-6

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3-7 3-7 3-8 3-9 3-9

. . 3-9 . . 3-10 . . 3-12 . . 3-13 . . . .

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3-13 3-13 3-13 3-14

. . 3-14 . . 3-15 . . 3-15 . . . .

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3-15 3-15 3-16 3-18

2213 Service

TA BLE O F CO NT ENTS (cont) Page

Page

SECTIO N 5 AD JU STMEN T PROC E DURE

S ECTIO N 3 THE ORY O F OPER ATION (co n t)

I NT ROD UCTIO N . . . . . . . . . . . . PURPOS E . . . . . . . . . . . . . . . TEST E QU I PMEN T RE QU I RE D L I M ITS AND TO LER ANCES . . P ARTIAL PR OC E DURES . . . . AD JUSTMENT I NT ER ACTION PREP ARATIO N F O R AD JU ST MENT. . . . . . . . . . . . I N DEX TO AD JU ST MENT PR OC EDURE . . . . . . . . . . . . . POWER SUPPLY AN D CRT DISPL AY . . . . . . . . . . . . . . . . . VERTICA L . . . . . . . . . . . . . . . . H O R IZONTA L . . . . . . . . . . . . . . TR IGGER I NG . . . . . . . . . . . . . . EXT ERNAL Z-AXIS AND PR OBE AD JU ST . . . . . . . . . . . . .

DE TAI LE D CI RCU IT D ESC R I PTION (cont) AUTO I NTEN SITY AND Z-AXIS AM PL I F IER . . . . . . . . . . . . . . . Auto Intensity . . . . . . . . . . . Ζ-Axis Am p lifier . . . . . . . . . . HO R IZO NTA L . . . . . . . . . . . . . H orizontal Pream p lifier . . . . . ΧΥ Am p lifier . . . . . . . . . . . . H orizontal Output Am p lifier . . P OWER S UPPL Y . . . . . . . . . . . P ower Input . . . . . . . . . . . . . P reregulator . . . . . . . . . . . . . Inverter . . . . . . . . . . . . . . . . C RT Supply . . . . . . . . . . . . . Auto Focus Circuit . . . . . . . . Low-Voltage Supplies . . . . . . . DC R estorer . . . . . . . . . . . . .

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3-19 3-19 3-20 3-20 3-20 3-21 3-22 3-22 3-22 3-22 3-23 3-24 3-24 3-24 3-24

S E CTIO N 4 PERF O RMANCE C HE C K PR OC EDURE

I NTROD UCTIO N .

. . . . . . . . . . . PURPOS E . . . . . . . . . . . . . . . T EST EQU IPMEN T RE QU I RE D L I M ITS AN D TOL ER ANCES . . PREP ARATIO N . . . . . . . . . . . I N DE X TO PERF O RM AN CE CHE CK ST EP S . . . . . . . . . . . . VERTICA L . . . . . . . . . . . . . . . . H O R IZO NTA L . . . . . . . . . . . . . . T R IGG ER I NG . . . . . . . . . . . . . . E XT ERNA L Z-AXIS AND PR OBE AD JU ST . . . . . . . . . . . . .

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4-1 4-1 4-1 4-1 4-1

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4-3 4-4 4-6 4-9

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S ECTION 6

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5-1 5-1 5-1 5-1 5-1 5-1

. . . 5-3 . . . 5-3 . . . .

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5-4 5-7 5-13 5-17

. . . 5-20

M AI NTEN AN CE STATIC-S EN SITI VE CO MPONENTS PREVEN TI VE MAI N TEN ANC E . . . I NTROD UCTIO N . . . . . . . . . . . G ENER A L CA RE . . . . . . . . . . . I NSPE CTIO N AN D C LE AN I N G . LUBR ICATIO N . . . . . . . . . . . . S EM ICON DUCTO R CHE C K S . . . PER IODIC RE AD JU ST MENT . . . T ROUBLE SHOOTI NG . . . . . . . . . . INTROD UCTIO N . . . . . . . . . . . T ROUBLE SHOOTI NG AIDS . . . TR OUBLE SHOOTI NG EQUIPMENT . . . . . . . . . . . . . . T ROUBLE SHOOTI NG T E CHN IQ UE S . . . . . . . . . . . . . CO RRECTI VE MAI NTEN ANCE . . . NT ROD UCTIO N . . . . . . . . . . . MAI NTEN ANCE PRECAUTIONS OBTAIN I N G REPLAC EMENT P A RTS . . . . . . . . . . . . . . . . . . M AI NTEN AN CE AIDS . . . . . . .

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6-1 6-2 6-2 6-2 6-2 6-4 6-4 6-4 6-5 6-5 6-5

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6-7 6-10 6-10 6-10

. . 6-10 . . 6-10

2213 Service

TABLE OF CONTENTS (cont) Page SECTION 7 OPTIONS

SECTION 6 MAINTENANCE (cont) INTERCONNECTIONS . . . . . . . . TRANSISTORS AND INTEGRATED CIRCUITS . . . . . . SOLDERING TECHNIQUES . . . . . REMOVAL AND REPLACEMENT INSTRUCTIONS . . . . . . . . . . . . . Cabinet . . . . . . . . . . . . . . . . . Cathode-Ray Tube . . . . . . . . . . High-Voltage Shield . . . . . . . . . Attenuator/Sweep Circuit Board . . . . . . . . . . . . . . . . . . Front-Panel Circuit Board . . . . . Main Circuit Board . . . . . . . . . Current Limit Circuit Board . . . REPACKAGING FOR SHIPMENT .

. 6-10 . 6-11 . 6-12 . . . .

6-13 6-13 6-13 6-14

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6-14 6-15 6-16 6-18 6-18

SECTION 8 REPLACEABLE ELECTRICAL PARTS SECTION 9 DIAGRAMS SECTION 10 REPLACEABLE MECHANICAL PARTS ACCESSORIES

INTERNATIONAL SALES & SERVICE OFFICES U.S . SALES& SERVICE OFFICES CHANGE INFORMATION

2213 Service

ιι s τ ο F ιιιυ s τ R ατιοιν s Fig u re

2-1 2-2 2-3 2-4 2-5 2-6

2-7 2-8

iv

Page The 2213

Oscillosco pe

viii

Power-i n put-voltage configu rations . . . . . . . . . . . . . . . . . . . . . . L ine fuse a nd power cord . . . . . . . . . . . . . . . . . . . . . . Power, d isp lay, a nd probe adjust controls, connector, an d ndicator

V e rtical co n t r ols an d connectors H orizontal co n t r ols . . . . . . . . .

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Trigger controls, co nn ecto r, an d in dicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

R ear- panel connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 Gratic ule measurement ma rk ings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8

3-1 3-2 3-3 3-4 3-5 3-6 3-7 3-8

B asic b lock d iagram of t he 2213 Oscilloscope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3

4-1

Test setup fo r exte rnal trigger an d j itter chec ks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10

6-1

Multipin connecto r orie ntation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6

9-1 9-2 9-3 9-4 9-5 9-6 9-7 9-8 9-9 9-10

Color codes for resistors an d capacitors . Semiconductor lead co nfigurations . Locati ng components on sc hematic diagrams and circuit board illustrations . 2213 bloc k diagram. A12-Attenuator/Sweep board . Ci rcu it view of A12`-Atte nuato r/Sweep boar d. Circuit view of A10-Main boar d. A10-Main board . All -Front P anel b oard. A19-Current L imit board.

Detailed bloc k diagram of the Chan nel 1 attenuator an d attenuator switching tables Diod e gate b iasing for α C hannel 1 d isplay . . . . . . . . . . . . . . . . . . . . . . . . . . . . CHOP VERTICA L MOD E waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Swee p timing d iagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sim plified diagram of the Ζ-Axis Switch i ng Logic circuit . . . . . . . . . . . . . . . . . . Detailed bloc k diagram of t he H orizontal Amplifier . . . . . . . . . . . . . . . . . . . . . . Sim plifie d diagram of the DC Restorer circuit . . . . . . . . . . . . . . . . . . . . . . . . . .

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3-5 3-8 3-11 3-16 3-18 3-21 3-25

ι ι ιι ι

2213 Service

LIST OF TABLES Table

Page

1-1 1-2 1-3

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 Environmental Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 Physical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7

4-1 4-2 4-3 4-4 4-5 4-6

Test Equipment Required . . . . . . . . . . . . Deflection Accuracy Limits . . . . . . . . . . . Settings for Bandwidth Checks . . . . . . . . . Settings for Timing Accuracy Checks . . . . Delay Time Range Checks . . . . . . . . . . . . Switch Combinations for Triggering Checks

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4-2 4-4 4-5 4-7 4-7 4-9

5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 5-9

Adjustment Interactions . . . . . . . . . . . . . Power Supply Limits and Ripple . . . . . . . Deflection Accuracy Limits . . . . . . . . . . . Attenuator Compensation Adjustments . . . Settings for Bandwidth Checks . . . . . . . . . Timing Accuracy . . . . . . . . . . . . . . . . . . Settings for Timing Accuracy Checks . . . . Delay Time Range Checks . . . . . . . . . . . . Switch Combinations for Triggering Checks

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5-2 5-5 5-8 5-10 5-11 5-14 5-15 5-15 5-18

6-1 6-2 6-3 6-4

Relative Susceptibility to Static-Discharge External Inspection Checklist . . . . . . . . Internal Inspection Checklist . . . . . . . . . Maintenance Aids . . . . . . . . . . . . . . . .

Damage . . . . . . . . . . . . . . . . . .

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6-1 6-3 6-3 6-11

2213 Service

O PER ATO R S SA FETY S UMMARY The general safety information in this part of the summary is for b oth operating and servicing p ersonnel. Specific warnings and cautions will be found throughout the manual where they apply and do not appear in this summary.

Terms i n

Th is Manual

CA UTION statements id entify conditio ns or pr actices that could result i n damage to the equ i pme nt or other property . identify cond itio ns or p ractices that co u l d result in pe rso nal in jury or loss of life . WARN I NG stateme n ts

Terms as

Mar ked on

Equipment

CA UTION indicates α personal i nj ury h azard not immed iately accessible as one reads the ma rk ings, or α h azard to property, inclu d ing t he equ ip ment itself . DA N G ER indicates α perso nal inju ry h azard imme diately accessible as one r eads the ma rk ing. Symbols in This Manual T h is sym bol indicates where applicable cautiona ry or other info rmation is to be found. F o r maximum in put voltages, see Table 1-1 . Sym bols as

M ar ked on Equ ipment DA NG ER - H ig h voltage.

Gro un d ing the

P roduct

Danger Arising

F rom L oss of

This p rodu ct is g rounded th rough t he groundi ng condu cto r of t he p ower cord. To avoid electrical shoc k, pl ug the power co rd into α p roperly wired recepta b le before connecting to the product in pu t or outpu t terminals. Α protective ground co nn ectio n by way of the grou nd ing co nductor i n the powe r cord is essential for safe operatio n.

Grou n d

Up on loss of the protective-grou nd co nn ection, all accessible co nductive p arts (i ncl u d i ng knobs an d cont r ols that may ap pear to b e insulating) can re nder an electric s h oc k.

U se the Proper P ower Cord

U se only the p ower co rd an d connector specifie d for your produ ct . U se only α powe r cord th at is in good conditio n. F or detailed i nformatio n on p ower cord s and co nnectors see F igure 2-1 .

U se the P roper F use

Protective grou nd (eart h ) te rminal .

To avoi d fire h aza rd , use only α fu se of the correct ty pe, voltage rati ng a n d c urrent rati ng as specifie d in the parts list for you r produ ct .

ATTENTION - R efer to manual .

Do

Not

Do

N ot R emove Covers

P ower Source

Th is produ ct is intended to operate from α power so u rce th at does not apply more than 250 volts rms betwee n t he supply conductors or b etween either supply co nductor and grou nd . Α protective groun d co nnection by way of the ground ing con d uctor i n t he power co rd is essential for safe operation .

Op erate in

Ex p losive

Atmos pheres

To avoi d ex plosion, do n ot op erate th is p ro du ct in an explosive atmosph ere unless it h as been specifically ce rtified fo r s uch operation . or

P anels

To avoid personal injury, d o n ot remove th e pr o d uct covers or p anels . Do n ot operate the produ ct wit hout the cove rs an d panels properly i nstalle d .

2213 Service

S ERV ICI N G SA FE TY S UMM AR Y FO R Q UA L IFIED SERVICE PERSONNEL O NL Y Refer also

Do

N ot

to th e preceding Operators Safety Summary.

Service Alone

Do not perform internal service or ad justment of this prod uct u nless another person capable of rend ering first aid and resuscitation is p resent .

Use

Care When Servicing With Power On

Dangerous voltages exist at several points in this product . To avoid personal injury, d o not touch expose d connections or components while p ower is on .

Disconnect power b efore removing soldering, or replacing components .

protective

panels,

Power Source This product is inten d ed to operate from α power source that d oes not apply more than 250 volts rms between t he supply conductors or between either supp ly con d uctor an d ground . Α p rotective groun d connection by way of the groun d ing conductor in t he p ower cord is essential for safe o p eration .

2213 Service

The 2213 Oscilloscope .

Vill

3827-01

Section 1-2213 Service

S PE CI F ICATIO N IN

T ROD UCTION

T he TEKTRONIX 2213 Oscilloscope is α rugged, lightweight, d ual-channel, 60-MHz instrument that features α bright, sharply defined trace on an 80- by 100-mm cathoderay tube (crt) . Its vertical system p rovi d es calibrate d d eflection factors from 2 mV p er division to 10 V per d ivision . Trigger circuits enable stable triggering over the full bandwidth of the vertical system . The h orizontal system provi d es calibrated sweep s p eeds from 0 .5s p er division to 50 n s per d ivision along with α delaye d -swee p feature . Α Χ 10 magnifier exten d s the maximum swee p spee d to 5 ns per d ivision .

ACC E SSO R I E S T he instrument is shipp ed with accessories : 1 Operators manual 1 Service manual

2 2

t he

PERF O RM A NC E CO N DITIO NS T he following electrical characteristics (Table 1-1) are valid for the 2213 when it h as been adjusted at an ambient temperature between +2 ρ° ς an d +30° C, h as h ad a warm-up p erio d of at least 20 minutes, an d is operating at an ambient temperature between 0° C an d +50° C (unless otherwise noted) .

Items listed in the "Performance Re q uirements" column are verifiable q ualitative or q uantitative limits, while items listed in the "Supplemental Information" column are either ex p lanatory notes, calibration setu p descri p tions, performance characteristics for which no absolute limits are specified , or characteristics that are impractical to check .

following stan d ard

P robe p ackages P robe grabber tips

For p art numbers and further information about b oth stan d ar d and optional accessories, refer to the "Accessories" p age at the back of this manual . Your Tektronix representative, your local Tektronix F iel d Office, or the Tektronix p rod uct catalog can also provi d e accessories information .

E nvironmental characteristics are given in Table 1-2 . The 2213 meets the requirements of MIL-T-28800B, Class 5 equi p ment, except where otherwise note d .

Physical characteristics in Table 1-3 .

of the

instrument are listed

S p ecification-2213

Service Table 1-1

E lectrical

Characteristics

P erformance

C haracteristics

Supplemental Info rmation

Requirements

VERTICA L D EFLE CTIO N SYST EM 1 Χ gain adj uste d with VOLTS/DI V switch set to 20 mV per division .

Deflection Factor

10 Χ gain adjusted with VO LTS/DIV switch set to 2 mV per d ivision . 2 mV per d ivision to 10 V per d ivision i n α 1-2-5 se quence.

R ange

Αεευ racy

+20° C to +30° C

±3%ο.

0° C to +50° C

+4%ο.α

of V OLTS/DIV V aria ble Control. Range

Step

Continuously variable b etween settings. Increases d eflection factor b y at least 2.5 to 1 . with α vertically centere d 5-division refe rence signal from α 50- Ω source driving α 50-Ω coaxial cable that is te rminate d in 50 Ω at t h e input connector, with t he V OLTS/DI V V ariable control in its CA L detent. Measure d

Response

R ise

5.8 ns or less .

Time

R ise time is calculated f rom t he formula: R ise

0 .35 BW (in MH z)

Measured with α vertically centered 6- division refere n ce signal from α 50-Ω so urce d riving α 50- Ω coaxial ca ble t h at is terminated i n 50 Ω , both at the in put connector an d at th e P61 20 probe input, with the V O LTS/DI V Varia ble control in its CA L d etent.

B an dwidt h

0°C to +40ο C

20 mV to 10 V per Division

Dc to at least 60 MHz .

2 mV to 10 mV p er Division

Dc to at least 50 MH z .

+400 C to +500 C

2 mV to 10 V per Division

Dc to at least 50 ΜΗΖ.α 250 kH z ±30%ο.

Ch op Mode R epetition Rate

α Perfo rmance

Time =

R equ irement not checked

i n Se rvice Manual .

ι ι ι ι

Specification-2213 Table 1-1 (cont) Characteristics

0

ι ι ι ι

ιι

ι ι ι ι ι ι ιι ι ι

Se r vice

Ι

P erforma nce R equ irements

Ι

Supplemental Information

VERTICA L D EFLE CTIO N SYST EM (cont) In put Characteristics R esista nce

1 ΜΩ ±2%.α

Capacitance

30 p F ±3 ρ F . α

Maximum Safe In put Voltage Q DC Co uple d

400 V (dc + peak ac) or 800 V ρ-ρ ac to 1 kH z or less .α

AC Couple d

400 V (dc + peak ac) or 800 V ρ-ρ ac to 1 kH z or less α

Common- Mode R ejection R atio (CM RR)

At least 10 to 1 at 10 MH z.

Chec ked at 20 mV per d ivision for common-mode signals of 8 divisions or less, with VOLTS/DI V Varia ble control ad ju sted for b est CMRR at 50 kH z.

T R IGGER SYST EM Trigger Sensitivity

AUTO an d N ORM

0.4 division inte rnal or 50 mV external to 2 MH z, i ncreasi ng to 1 .5 divisions inte rnal or 250 mV external at 60 MHz .

E xternal trigger signal from α 50-Ω sou rce d riving α 50-Ω coaxial ca ble that is terminated in 50 Ω at the in pu t connector. W ill trigger on tv line sync com ponents

in N ORM only : > 0.4 d ivisio n intern al or 50 mV ρ-ρ exte rnal. AU TO L owest U sable Frequ ency

20 Ηz.α

T V F I EL D

2.0 divisions of composite vi d eo or composite sync .α

E xternal Input

Maximum Input Voltage Q

400 V (dc + peak ac) or 800 V ρ-ρ ac at 1 kH z or less .α

In put R esistance

1 ΜΩ ±2%.α

Input Capacitance

30 p F ±3 ρ F .α

AC Coupled

10 Hz or less at lower -3 d B point.α

LEVEL Control Range (wit h NO RM T R IGG ER MOD E) ΙΝΤ

On screen limits .α

ΕΧΤ and DC

At least ±2 V (4 V ρ -ρ).α

αPerfo rmance R eq uirement not checked in Service Manual .

1-3

Specification-2213 Service Table 1-1 (cont)

C haracteristics

Performance Re quirements

Su p plemental Information

T RIGGER SYSTEMAcont) LEVEL Control R ange (with NORM T RIGGER MODE) (cont) ΕΧΤ an d DC - 10

VAR HOLDOFF Control R ange

At least ±20 V (40 V ρ-p) .' Increases swee p hol doff time b y at least α factor of four.'

H ORIZONTAL D EFLECTION SYSTEM Sweep Rate Calibrated Range Α Swee p

0.5 s p er division to 0.05 μs per d ivision in α 1-2-5 se quence. Χ 10 Magnifier exten ds maximum sweep spee d to 5 ns p er division . Unmagnifie d

Magnified

+20° C to +30 °C

±3°/ο

±5°/ο

0° C to +50° C

±4ο%α

±6ο%α

Accuracy

POSITION Control R ange

Start of swee p to 100th division will position past the center vertical graticule line with Χ 10 Magnifier.

V ariable Control R ange

Continuously variable between calibrated settings . E xtends the sweep sp eed s by at least α factor of 2.5 .

Delay Time

R ange Selector

Minimum delay is less than selected values of 0.5 μs, 10 μs, and 0.2 ms .

MULTIPLIER Control

Increases d elay time by at least α factor of 20 .

Jitter

One part, or less, in 5,000 (0 .02%) of the maximum available delay time . Χ-Υ OPERATION ( Χ 1 M AGNIFICATION)

Deflection Factors R ange

Same as Vertical Deflection System, with both VOLTS/DIV Variable controls in CAL detent .

'Performance R equirement not checked in Service Manual .

Sweep accuracy applies over the cent 8 divisions. Exclude the first 25 ns of the sweep for both magnified and unmagnified sweep speeds and exclu anything b eyond the 100th magnified division .

ι ι ι ι ι ι ι ι : ι ιι ι ι ι ι ι ι ι ι ι ι

0

REV NOV 1981

ι

S pecification-2213 Service Table 1-1 (con t)

Perform ance Requ irements

Characteristics

Supple mental Informatio n

Χ-Υ OPERATIO N (Χ1 MAG NIFICATION) (cont)

ι

Deflection F actors (cont)

M easured with α dc-coupled, 5-divisio n

Accuracy

refere

+20°C to +30°C

nce

sig

n al .

0°C to +50°C

Bandwidth

Ι

Ι

M easured with α 5-division reference signal.

Χ-Axis

ι

Ph ase Difference Between Χ- an d Υ-Axis Am plifiers PROBE ADJUST Signal at PR OBE ADJU ST Jac k Voltage

0.5 V ±20%.

Repetitio n Rate -

1 kHz ± 20%.α Z-AXIS INPUT

l ie Se nsitivity

ι ι ι ι

5 V causes noticeable modulation . Positive-goi ng input signal decreases intensity

U sable Freq uency Range

Dc to 5 ΜΗ z.α

M axim um Safe Inp ut Voltage

30 V (dc + pea k ac) or 30 V ρ-ρ ac at 1 kH z or less ."

Input Im pedance

10 k Ω ± 10%.α

P OWER SO UR CE

Line Voltage Range

90V to 250V.α

Line F requen cy Range

48 Hz to 62 Ηz.α

M aximum P ower Consumption

Line F use

48 Hz to 440 Ηz.α

I nst ru ments with Curren t Limit Boa rd I nst ru ments with Preregulator Board

50 W .α

Inst ru ments with Current Limit Boa rd

40 W .α

Inst ruments with Preregulator Board

2Α, 250V, F ast

I nstruments with Current Limit Boa rd

1 Α, 250V, Slow

Instruments with Pr eregulator Board

° Perform a n ce R equ irement not c hec ked in Service Manual.

REV JUL 1982

1-5

S pecificatio n-2213 Service

Table 1-1 (cont) Suppleme ntal Information

Performance R equirements

C h a racte r istics

CATHOD E-R AY TUBE Display Area

80 by 100 mm .a

Stan d ar d Ph osphor

Ρ31 .α

N ominal Accelerating Voltage

10,000 V.a

αPerfo rma nce

R equi rement

not chec ked in Service Manual .

Table 1-2 E nvironme ntal Characteristics

Desc ri p tion

Characteristics

NOTE

The instrument meets α// of the following Μ/L-Τ-288008 requirements for Class 5 equipment. Temperature Operating

0°C to +50° C (+32 ° F to +122° F) .

N onoperating

-55° C to +75° ς (-67 ° F to +167 ° F ) .

Altitu de Operating

To 4,500 m (15,000 ft). Maximum operating temperature d ecreased 1 ° C per 300 m (1,000 ft) a bove 1,500 m (5,000 ft) .

Nonoperating

To 15,000 m (50,000 ft) .

Humi dity (Operating an d Nonoperati ng)

5 cycles (120 h ou rs) referenced to MIL-T-28800B, Class 5 instruments.

Vi bration (O perating)

15 minutes along eac h of 3 major axes at α total displacement of 0.015 inch ρ-ρ (2 .4 g at 55 Hz), with frequency varied from 10 Hz to 55 H z to 10 Hz in 1-minute swee ps. Hol d for 10 minutes at 55 Hz . All ma jor resonances must be above 55 Hz .

Sh oc k (Operating an d N onoperating)

30 g, half-sine, 11-ms d uration; 3 shoc ks per axis each directio n, for α total of 18 s hoc ks.

Specification-2213 Service Table 1-3 Physical Characteristics Characteristics Weight

Description

With Front-Panel Cover, Accessories, and Pouch

7 .6 kg (16 .8 lb).

Without Front-Panel Cover, Accessories, and Pouch

6.1 kg (13 .5 lb) .

Domestic Shipping

8.2 kg (18 .0 1b) .

Height With Feet and Handle Width

137 mm (5 .4 in) .

With Handle

361 mm (14 .2 in).

Without Handle

328 mm (12.9 in).

Depth With Front-Panel Cover

445 mm (17 .5 in) .

Without Front-Panel Cover

439 mm (17 .3 in).

With Handle Extended

511 mm (20.1 in) .

Sectio n 2-2213 Se rvice

O PER ATI N G I N ST RU CTIO N S PREP A R ATIO N F O R U S E SA FETY Refer to th e Safety Summaries at t h e front of t h is ma n ual fo r power source, groun d ing, and oth er safety consi derations pertaining to t h e use of t h e 2213 . Before co n necti n g th e instrume n t to α p ow er so u rce, caref u lly read th e followi n g informatio n a b out line voltages, power cor d s, a nd fuses ; then verify t h at t h e pro p er power-input fuse is i n stalled .

L I NE VO LTAG E Th e instrument is ca p able of continuous o p eration using ac-power-input voltages t h at range from 90 V to 250 V nominal at fre qu encies from 48 H z to 62 H z .

P O WER CO R D F or t h e 120- V N orth American customer, th e 2213 is delivere d wit h α th ree-wire power cord perma n ently attach ed . At t h e en d of t h e cord is α three-contact p lug fo r connection to t h e power source and to p r otective groun d . T h e p lug's p rotective-grou nd contact connects (t h ro u g h th e p rotective-groun d con du ctor) to t h e accessi b le metal p arts of t h e instrument . F or electrical-s h ock p rotection, i n sert t h is plug only into α power-source outlet th at h as α securely g r ou nde d p rotective-gro u n d con tact .

F or th e non-North America n customer (a nd for th e 240-V N orth America n user), th e a pp ropriate power cord is sup p lie d by an optio n t h at is s p ecified wh en th e instrumen t is ord ere d . Th e o p tional p ower cords available are illustrate d in F igure 2-1 .

LI NE FU S E T h e instru ment fuse h ol d er is locate d on t h e rear p a n el (see F igu re 2-2) an d contai n s th e line fuse . V erify t h at t h e p roper fuse is installed by performi n g t h e following proce d ure : 1 . U n p lug th e p ower cord from t h e p ower-i n put source (if a p plicable) . 2 . P ress in an d slig h tly rotate th e fuse- h ol d er cap countercloc kwise to release it. 3 . Pull out t h e cap from th e fuse h ol d er, wit h th e fuse attach e d to t h e insid e of t h e ca p . 4.

N ote

fuse values an d verify p ro p er size (2 Α , 250 V, fast-blow) .

5 . Reinstall t h e fuse an d fu se-h ol d er cap .

O

perating I n structions-2213

Plug Co nfiguration

α

λΙ .

'

-'

α

Service

Fu se

L i ne Co rd

Powe r Cord and Plug Type

I nstalled I n strument Fuse

Hol der

U.S . Do mestic Sta ndard

US 150Α V

1 Α, 250 V a Slow-blow AGC/3AG

AGC/3AG

No ne

Euro 240V 10-16Α

1 Α, 250 V a Slow-blow 5χ20 mm

5χ20 mm

None

Option Α2

UK 240V 13Α

1 Α, 250 Va Slow-blow 5χ20 mm

5 χ20 mm

13 Α Ty pe C

Option Α3

Au st r alian 240V 10Α

1 Α, 250 Va Slow-blow 5χ20 mm

5χ20 mm

None

Option Α4

Nort h Amer ica 240V 15Α

1 Α, 250 Va Slow-blow AGC/3AG

AGC/3AG

No ne

Op tion Α1

~

Factory

Category

Ca p

Plug Fuse

3397-03

I nstru ments containing the Current Li mit boa rd have α 2 Α, 250 V, Fast- blow fuse.

Figur e 2-1. Power-input-voltage configurations.

CA UTION Go

FOR [ σΝΤΙΝυε . RGF Ρ τε Cτ10Ν RE11ACI D .11 IT . III RATIO ΓΥΡε AND ΙΙ5 ε . DISCO "'ANICT POWER INPUT BEFORE Ι. Ρ .ROOKS 1-

CAUTION

1. AVOID EIECIR11 IRDCL THE PLAYER CORD ΡΝΟΓΕΠΙΥε

GROUNDING CONDUCTOR MUST SE CONNECTED TO GROUND ΕΜτ ε ΑΜΙ 5 ιΝΝτ Ισκί3 Ρ050Ιυε G0ιΝ6 INPUT 0[CR14111 ΙΝΤΕΝSΠι P CAUSES

5 νσιτ Ρ χ mιεερΒιε

MODULATION AT NORMAL INTENSITY " 3DV PEAK

F ig ure 2-2. L i ne fuse and power co rd.

2-2

REV JUL 1982

ι ι ι

Ope r ati ng Inst ructio ns-2213 Service

ι

CO NT R O LS, CO NNE CTO R S, A N D I N DICATO R S Th e following d escri ptions are i n tended to familiarize t h e o p erator wit h t h e location, operation, a n d f un ction of t h e i n str u ment's co n trols, connectors, a n d in d icato r s .

P OWER, DISPLAY, AN D PR O BE ADJU ST

R efer to

F igure

2-3 for location of items 1 th rough 7 .

nter n al Graticule- E liminates p arallax viewing error between t h e trace a n d graticule lines. R ise-time am p lit u d e and measurement p oints are i nd icated at t h e left e d ge of t h e graticule .

be m aintained as c h anges occur in t h e intensity level of th e trace .

PR O BE ADJUST Connecto r- Provides an a pproximately 0 .5 V, n egative-going, sq u are-wave voltage (at approximately 1 kH z) th at permits t he operator to compen sate voltage probes and to c hec k operation of th e oscilloscope vertical system . It is n ot intended to ver ify t he accuracy of t he vertical gain or time-base calibration .

I

BEAM F I N D Switch - Wh en h el d in, compresses t h e dis p lay to wit h in th e graticule area an d p rovides α visible viewing intensity to ai d in locating off-scree n d is p lays .

P OWER

Switch -Turns instrume n t p ower on and off . P ress in for ON ; press again for O FF .

AU TO F OC U S

Control-Ad j usts dis p lay for optimum d efinition . Once set, t h e foc u s of t h e crt disp lay will

T R AC E R OTATIO N Co ntrol-Screw d river co n trol u se d to align t h e crt trace with t h e h orizontal graticule lines .

A U TO I N T EN SITY Control-Ad ju sts brig h tness of t h e crt d is p lay . Th is cont r ol h as no effect wh e n t h e BEAM F I N D switc h is p ressed in . Once t h e co n trol is set, intensity is automatically maintained at approximately th e same level betwee n S E C/DI V switc h settings from 0.5 ms per d ivision to 0 .05 μ s per d ivision .

2213 6 ο

MENEM

VERTICAL

MENEM MENEM

R efer to

MENEM

Ι Ιι

ΡΜΑ

1 O R Χ an d C H 2 OR Υ Connectors- P rovide for ap plication of exter n al signals to t h e in puts of

CH

3397-04

F igure 2-3. Powe r , d isplay, a nd p ro b e adj ust co nt rols, co nnecto r , an d in d icator .

ι

REV NOV 1981

2-4 for location of items 8 th roug h 16 .

S ER IA L an d Mo d Slots-T h e S ER IA L slot is imprinted wit h t h e instrument's serial nu mbe r . T h e M o d slot co n tains t h e o ptio n num b er t h at h as been installe d in t h e instrume n t .

MOMME

ONE

F igu re

th e vertical d eflection system or for an Χ- Υ disp lay . In t h e Χ - Υ mo d e, t h e signal connecte d to t h e C H 1 O R Χ connector provi d es h orizo n tal deflection, and t h e signal con n ected to t h e C H 2 O R Υ conn ector provi d es vertical d eflection .

GN D

Connector- P rovi d es instrument c h assis ground .

direct

co nn ection

to

2-3

Operating Instructions-2213 Service 10Χ PROBE-Indicates t he d eflection selected when using α 10Χ probe .

factor

VOLTS/DIV Variable Controls-When rotated coun-

ter clockwise out of their detent positions, these controls provide continuously variable, uncalibrated deflection factors between the calibrated settings of the V OLTS/DIV switches . Extends maximum uncalibrated deflection factor to 25 volts per division with IX probe (α range of at least 2 .5 :1) . I NVERT Switch-Inverts the Channel 2 d isplay when button is pressed in . P ush button must be pressed in α second time to release it and regain α noninverte d dis p lay .

VERTICAL MODE Switches-Two three-position switches are u sed to select the mode of operation for the vertical amplifier system . CH 1-Selects only the Channel 1 input signal for d isplay . 3397-05 Figure 2-4 . Vertical controls and connectors.

In put Cou p ling (AC-GND-DC) Switches-Used to select the method of coupling input signals to the vertical deflection system . AC-Input signal is capacitively coupled to the vertical amplifier . The d o component of the input signal is b locked . Low-frequency limit (-3 d B p oint) is a pp roximately 10 Hz . G N D-The in p ut of the vertical amplifier is grounde d to provi d e α zero (groun d ) referencevoltage d isplay (does n ot groun d the input signal) . This switch p osition allows p recharging the input cou p ling ca p acitor . DC-All frequency components of the input signal are couple d to the vertical d eflection system .

C H 1 VOLTS/DIV and CH 2 VOLTS/DIV SwitchesUsed to select the vertical d eflection factor in α 1-2-5 se q uence . To obtain α calibrated d eflection factor,

the VOLTS/DIV variable control must be in detent .

1Χ PROBE-Indicates the deflection factor selected when u sing either α 1 Χ p robe or α coaxial cable .

2-4

BOTH-Selects both C hannel 1 a n d C hannel 2 input signals for display . The BOTH p osition must be selecte d for either ADD, ALT, or CHOP operation .

C H 2-Selects only the Channel 2 input signal for display . ADD-Disp lays the algebraic sum of the Channel 1 an d Channel 2 input signals . ALT-Alternately d is p lays Channel 1 and Channel 2 input signals . The alternation occurs d uring retrace at the end of each sweep . This mo d e is useful for viewing both i nput signals at swee p sp ee d s from 0.05 μ s p er d ivision to 0 .2 ms per division .

C HOP-The dis p lay switches between the Chan-

nel 1 and Channel 2 input signals during the sweep . The switching rate is a p proximately 250 kHz . This mo d e is u seful for viewing b oth Channel 1 and Channel 2 in p ut signals at sweep speeds from 0 .5 ms p er d ivision to 0 .5 s p er d ivision .

POSITION Controls-Use d to vertically p osition the display on the crt . When the SEC/DIV switch is set to Χ - Υ , the Channel 2 P OSITION control moves the d isplay vertically (Y-axis), and the H orizontal POSITION control moves the d isplay h orizontally (X-axis) .

REV NOV 1981

Operati ng I nstructio ns-2213 Service

HOR IZO NTAL R efer to Figure 2-5 for location of items 17 through 22 .

D EL AY TIME-Two controls are used in co njun ctio n with I NT EN S and D LY'D HO R IZONTA L MOD E to select the amount of d elay time b etween t he start of the sweep and the begin n i ng of th e intensified zo ne.

R ange Selector Switc h-T his three-positio n switch selects 0.5 μs, 10 μ s, an d 0.2 ms of delay time . To increase the swee p delay from th e calib r ate d setti n g of t h e R ange Selector switch , rotate t h e M ULTI PL I ER cont r ol cloc kwise .

MU LTI PL I ER Control- Pr ovi d es va r ia b le sweep d elay f rom less th an 1 to greate r t h an 20 times t h e setting of the R ange Selector switch . S EC/DI V Switch -Used to select th e sweep spee d

for the swee p generato r in α 1-2-5 sequ ence . For cali brate d swee p spee ds, the SEC/DI V Variable co ntrol must be i n the calibrated detent (f u lly cloc kwise).

SEC/DI V Variable Cont rol- P rovi des contin uously va riable, uncalibrated sweep sp ee ds to at least 2.5 ti mes the calibrated setting. It exte nds the slowest swee p spee d to at least 1 .25 s p er division . Χ 10 Mag nifier Switch-To increase d is p layed swee p speed by α factor of 10, pull out the SEC/DIV Variab le k nob. The fastest swee p speed can be exte nd ed to 5 n s p er division. Pu sh in the SEC/DI V Var iable co ntrol k nob to regain t h e Χ 1 sweep spee d.

H OR IZONTA L MOD E switch dete r mi n es

Switch -Th is t h ree-position

th e mo de of operation for th e

h orizo n tal d eflection system .

D L Y- H orizo ntal deflection is provide d by t h e sweep ge nerator, without α delayed start, at α swee p speed d etermined by the S EC/DI V switch . ΝΟ

INTEN S- Horizontal d eflection is p rovi ded by th e swee p generato r at α sweep speed d etermined b y the SEC/DI V switch . The swee p generator also provides an i ntensified zone on t he d is play. Th e start of the intensifie d zone repr esents t he swee pstart poi n t wh en DLY'D H O R IZONTA L MOD E is selected. DLY'D-Horizontal d eflectio n is provided by th e sweep generato r at α sweep speed d etermi ned by the SEC/DI V switch setting. The start of th e sweep is delayed from the in itial swee p-t rigge r poi nt by α time determined by the setting of the D EL AY TIME R a nge Selector switc h an d MULTIPL I ER cont rol . POSITION Control-Positions zo n tally in all mod es.

the

d is play ho ri-

T R IGG ER R efer to Figure 2-6 for location of items 23 th rough 31 .

ΕΧΤ I NPUT Connector- Provides α means of i ntrodu cing extern al signals into the tr igger ge nerator . ΕΧΤ COUPLI NG S witch -Determines the method used to co up le exte rn al signals to th e Trigge r ci rcu it .

. Figure 2-5. H orizontal controls

AC-Sig n als above 60 H z are capacitively coupled to the in put of the T rigger circuit. Any do components are bloc ked, an d signals below 60 Hz are attenuated .

O perating

Instructions-2213 Service

DC-All com ponents of th e signal are cou p led to t h e trigger circu itry . T h is position is usef u l for d isplaying low-frequency or low-repetition-rate signals. DC= 10- E xternal trigger signals are atten u ate d by α factor of 10 .

15

SO UR C E Switc h -Determines t h e so u rce of t h e trigger signal t h at is couple d to th e in put of t h e trigger circuit . ΙΝΤ - P ermits triggering on signals t h at are a p plied to t h e C H 1 O R Χ an d C H 2 O R Υ input connectors . T h e so u rce of t h e internal signal is selected by t h e ΙΝΤ switch .

L I NE - P rovi d es

α triggering signal from α sam p le of t h e ac-power-source waveform . Th is trigger so u rce is useful w h e n c h annel-in p ut signals are time related (m u lti p le or su bm u ltiple) to t h e fre q uency on th e powe r-source-in pu t voltage . ΕΧΤ - P ermits triggering on signals applied to t h e ΕΧΤ I NPU T connector.

2 Ιϊ

ΙΝΤ Switch -Selects t h e sou r ce of t h e triggering signal w h en t he SO UR C E switc h is set to ΙΝΤ .

C H 1-T h e signal a pp lie d to t h e C H 1 O R Χ in p ut connector is th e sou rce of t h e trigger sig n al .

VER T MOD E -T h e internal trigger source is determined by t h e signals selecte d for display by t h e VER TICA L M OD E switc h es .

C H 2-T h e signal a p p lie d to t h e C H 2 O R Υ input co nn ector is t h e source of t h e trigger signal .

LEVEL Control-Selects t h e amplit u d e p oint on th e trigger signal at w h ic h t h e swee p is triggere d .

T R IG'D In d icator-T h e lig h t-emitting d io d e ( LE D) illuminates to in d icate t h at th e sweep is triggere d .

S L O PE

Switch -Selects the slope of t he signal that triggers t he sweep . (also refer to TV Sig n al Displays at the en d of Sectio n 2) . -T-Sweep is triggered on p ortion of t h e trigger sig n al .

th e

p ositive-goi n g

-\--Sweep is triggered on p ortio n of t h e trigger signal .

th e

negative-goi n g

MOD E sweep .

Switch -Determines t h e trigger mo d e for t h e

A U TO- Permits triggering on waveforms h avi n g repetition rates of at least 20 H z . Sweep free-runs in th e abse n ce of an adq uate trigger signal o r wh e n th e repetition rate is below 20 Hz . T h e ra n ge of t h e T R IGG ER LEVEL control will compensate for t h e amplitu d e variations of t h e t r igger signals .

N O R M-Sweep

is i n itiate d w h en an adeq u ate trigger signal is ap p lied . In t h e absence of α t r igger signal, no baseli n e trace will b e p resent . Trigge r ing on television lines is accomplish e d in t h is mo d e .

T V FI EL D- P ermits triggeri ng on televisio n fieldrate sig n als (refe r to TV Signal Dis plays at t he e n d of Section 2) .

VAR 3397-07

i

F ig ure 2-6 . T r igge r cont r ols, conn ector, and nd icato r .

2-6

H O L DO FF Control- P rovi d es co n tin u o u s control of h oldoff time b etween swee p s . Increases th e h ol d off time by at least α factor of fo u r. T h is control im pr oves t h e ability to trigger on a p erio d ic signals (such as complex digital wavefo rms) .

REV N OV 1981

ι ι ι ι ι ι ι ι ι ι

Operating Instr u ctions-2213 Service

RE A R P A NEL R efer to

F igure

intensity modulate t h e crt dis p lay . App lied signals

d o not affect d is p lay wavesh ape . Signals wit h fast rise times a n d fall times p rovi d e t h e most abrupt

inte n sity c h ange, an d α 5- V ρ - ρ signal will pro d uce noticeable modulation . Th e Z-axis signals m u st b e time-related to th e d isplay to o b tai n α sta b le presentation on t h e crt .

2-7 for location of item 32 .

ΕΧΤ Ζ AXIS Co n nector- P rovi d es α means of connecting external signals to t h e Z-axis amplifier to

CAUTION

CA U TIO N

FD CONTINUED FIRE PROTECTION FACE PC 01111 .11. G11EI1IN TYPE AND INPUT RATED FUSE DISCONNECT ΘΕ FΟΗΕ REPLACING FUSE REAL,Ρ ΙΙΝ 1 1ΟίΤΑΙΙ RANGE 90 Ζ50ΕΑ'

Ρ~ΜΟΥ~ COVFfl 'ITRFFFR 5ΕΝΥΙ C1ΝG TO

FU5"

Ζ50Υ

ΖΑ FAST

Ο

σUΑΙ111ΕD Ρεθ5σχχει

TO AVOID ELECTRIC SHOCK THE POWER CIRLD PROTECTIVE GROUNDING CONDUCTED MOST 81 CONNECTED TO GROUND Ε%Τ Z AXIS INPUT ιΟκσ POSITIVE GOING INPUT -FEASTS ΙΝτΕΝΙΙΤν 5 VΟίΓ ΡΡ εΑυ5Ε5 ΝΟΠC~Αθ l~ MODULATION AT χαΡΜΑι ιχτεχ 5 ιτν s30V PEAK

POWER χMAX WATTS 55 COΡΡΕχτ 16Α ΡΜ 5

Μ

,DID ΑΘ SIR,

Φ- .

10

ι ι ι ι ι ι ι ι

,

3397-08

F igu re

2-7.

Rear-p an el

co

nnector.

2-7

Operati n g Instructions-2213 Service

O PER ATI N G CO N SID ER ATIO N S T h e following basic operati ng informatio n and tech -

n i q u es s h oul d meas u rements.

be

consi d ere d

before

attem pting

any

G R ATIC ULE T h e gratic u le is internally ma rk ed on t h e face p late of th e crt to enable acc u rate measu reme n ts with out p arallax error (see F igure 2-8) . It is mar k e d wit h eigh t vertical and te n h orizontal maj or d ivisio n s . E ach ma j or divisio n is d ivi d e d into five su bd ivisions . T h e vertical d eflection factors an d h orizontal timing are cali b rated to th e graticule so th at acc u rate measurements can be mad e d irectly from th e crt . Also, percen tage mar k ers for t h e meas u rement of rise an d fall times are locate d on th e left side of t h e graticule .

G R OUN DI N G T h e most reliable signal measurements are ma d e wh en th e 2213 an d th e unit un d er test a r e con n ected b y α commo n reference (groun d lead), in add ition to t h e signal lea d or p ro b e . T h e probe's grou n d lea d p rovi d es th e b est g r oun d ing met h o d for signal interconnection and e n su res t h e maxim u m amount of signal-lea d s h iel d ing in th e p ro b e cab le. Α se p arate groun d lead can also be connected from t h e unit un d er test to t h e oscillosco p e G N D con nector locate d on t h e front p anel .

1ST O R LEF T VER TICA L G R ATIC ULE L I NE

R IS E A N D F A LL TIME ME ASUREMEN T PER C EN TAG E M A RKER S

C EN T ER VER TICA L G RATIC ULE L I NE

11TH OR R IG H T VER TICA L G R ATIC ULE L I NE

C EN T ER

H O R IZO N TA L G R ATIC ULE L I NE

F ig ure 2-8 . Graticu le measu rem e n t mar k i n gs .

2-8

SIG NA L CO NNECTIO NS Generally, probes offer t h e most convenie n t means of connecti n g an inpu t signal to t h e instrument . Th ey are s h iel d e d to p revent p ic ku p of electromagnetic interference, a n d th e sup p lie d 10 Χ p ro b e offers α h ig h in p ut im pedance th at minimizes circu it loading . Th is allows t h e ci r cuit u n d er test to o p erate wit h α mi n imum of c h ange from its n ormal con d itio n as measurements are being ma d e .

Coaxial ca b les may also be u sed to connect signals to th e in pu t connectors, b ut t h ey may h ave consi d erable effect on t h e accuracy of α d isplaye d waveform . To maintain t h e original frequency c h aracteristics of an applied signal, only h ig h - quality, low-loss coaxial cables sh ould be u se d . Coaxial ca b les sh oul d be terminate d at bot h en d s in th eir c h aracteristic im pe d a n ce . If th is is not p ossi b le, use suitable im p eda n ce-matc h ing d evices .

T CO UPL I NG CA PACITO R PRE CHA R GI NG I NPU

Wh en th e in p ut cou p li ng switc h is set to G N D, th e i n put signal is connected to groun d t h roug h t h e in put coupli n g capacitor in series with α 1- ΜΩ resistor to form α p rec h arging network . Th is networ k allows t h e in put co up ling ca p acitor to c h arge to th e average d c-voltage level of t h e signal ap p lie d to t h e p ro be . Th us, any large voltage tra n sients t h at may acci de n tally be ge n erated will not be applied to t h e am p lifier in p u t w h en th e inp u t cou p ling switc h is move d from G N D to AC . T h e p rec h arging n etwor k also provi d es α measu re of p rotection to t h e external circuitry b y re d ucing th e cu rrent levels t h at can b e d rawn from th e exter n al circ u itry d uring capacitor ch arging .

T h e following p roced ure s h oul d be used w h enever th e probe tip is connecte d to α signal source h avi n g α d iffe r ent d o level t h an t h at previously ap p lied, es p ecially if t h e d clevel differe n ce is more t h an 10 times t h e V O L TS/DI V switc h setting : 1 . Set t h e AC-G N D-DC switc h to G N D before connecting t h e p robe ti p to α signal source .

4115-16

2 . Insert t h e connector .

p ro b e ti p into th e oscillosco p e G N D

Operating 3.

W ait several seconds for the input coupling capacitor

to d ischarge .

6. Set the AC-GND-DC switch to AC . The display will

remain on the screen, an d the ac com p onent of the signal can be measured in th e normal manner .

4. Co nn ect the p ro be ti p to the signal so u rce . 5. Wait several seconds for t h e i nput co up ling ca pacitor to charge .

Instructions-2213 Service

I NST RUMENT

COO LIN G

To maintain a d equate in strument cooling, the ventilation holes on b ot h sides an d rear p anel of th e e q u i pment ca binet must remain free of obstructions .

OSCI LL OSCO PE DIS PLAYS I NTR OD U CTIO N

The proced ure in th is section will allow you to set up an d operate you r instrument to obtain the most commonly used oscilloscope d is p lays . Before starti ng this pr ocedu re, ve rify that t h e POWER switch is OFF (pus h button out), then plug th e p ower cord into an approve d ac- p ower-source outlet .

B AS ELI NE TR AC E F irst obtain α b aseline trace. 1 . P reset th e instrume nt front-panel co ntrols as follows: Disp lay

AUTO I NT EN SITY AUTO F OC US

Vertical

( Both

F ully countercloc kwise

(minim um) M i d range

C h annels)

AC-G N D-DC AC m (1 Χ ) V50 O LTS/DIV CA L dete nt V O LTS/DI V Varia ble (fully cloc kwise) CH 1 VERTICA L M OD E Off (b utton out) INVER T M i d ra nge P OSITIO N

H orizontal

S EC/DI V S E C/DI V Variable

H O R IZO NTA L MOD E Χ 10 M agnifier POSITIO N D EL AY TIME R ange Selector MULTI PL I ER

L oc ke d together at 0.5 ms CA L d etent (fully cloc kwise) ΝΟ D LY Off (varia ble knob in) M idrange 0.2 ms F ully countercloc kwise

Trigger

V AR HO L DO FF SLO PE LEVEL M OD E ΕΧΤ CO UPLING SO UR CE ΙΝΤ

NO RM (fully co un tercloc kwise) f (lever up) Mi d ra nge A UTO AC ΙΝΤ VERT M OD E

2. Press i n th e POWER switch button (ON) and allow the instrume n t to warm up for 20 minutes. 3. Ad just the AUTO I N TEN SITY control for desire d

d isplay brightness.

4. Adju st the V ertical and H orizontal controls to center the trace on the screen .

P OSITIO N

SIG NAL DIS PLAY 1 . Obtain α baseline trace . 2. Apply α sign al to either vertical-c hannel input connector an d set the VERTICA L MOD E switch to display th e channel use d . To display two time-related in put signals use both vertical-c h an nel i n p ut co nn ecto rs an d select BOTH VERTICA L MOD E ; th en select either ALT or CHOP, depen d ing on th e fre q uency of in put signals . 3. Ad just the AUTO I NTEN SITY control for desire d display brig h tness. If the disp lay is not visi b le with t he AUTO I NT EN SITY control at midrange, press the BEAM F I N D p us h b utton an d hol d it in wh ile a d justing the a pp ro p riate V O LTS/DI V switch (es) to re d uce the vertical

2-9

Op erating I n stru ctions-2213 Service d is p lay size . Ce n ter th e com p resse d display wit h in th e graticule area using t h e Vertical an d H orizontal P OSITIO N controls, th en release t h e BEAM F I N D p ush b utton . 4 . Ad j ust th e T R IGG ER LEVEL control, if necessary, to o b tain α sta b le display . 5 . Set th e ap p ro p riate V O L TS/DI V switc h (es) and readju st t h e V ertical and H orizontal POSITIO N controls to center th e d is p lay with in t h e gratic u le area . 6 . Set t h e S E C/DI V switch for th e desire d number of cycles of t h e d is p layed signal . Th en a dj ust th e A U TO F OC U S control for t h e best-define d dis p lay .

MAG N I F I E D-S WEEP DIS P LAY 1 . Obtain α Signal Display (see preceding instructions) . 2 . A d ju st th e H orizontal P OSITIO N control to move t h e trace area t h at is to be magnifie d to t h e center of th e crt graticule (0 .5 d ivision on eac h si d e of t h e center vertical graticule line) . Ch a n ge t h e S E C/DI V switc h setting as re q uired . 3. Pull out th e S E C/DI V V ariable kno b ( Χ 10) to obtain swee p magnificatio n . 4 . Ad j ust th e H orizontal POSITIO N control for p recise positioni n g of t h e magnifie d d is p lay . 5 . To calculate th e magnified sweep s p eed , d ivi d e t h e S E C/DI V switc h setting b y 10 .

D E LA YE D-SWEEP DIS PLAY 1 . O btain α Signal Display . 2 . Select I N T E N S H O R IZO N TA L M OD E an d set t h e D EL AY TIME Range Selector switc h to t h e d esire d amount of d elay time .

3. Ad j ust th e A U TO I N T EN SITY control as nee d ed to ma ke th e intensifie d zone d istinguis h able from t h e remain d er of t h e d isplay .

4 . Adj ust t h e D EL AY TIME MUL TI PL I ER control to move t h e start of t h e inte n sified zone to t h e start of th e p oint of interest on t h e crt trace . To capture an event th at occurs after th e swee p en d s, a dj ust t h e start of t h e intensified zone p ast t h e en d of th e swee p.

Χ- Υ DIS PLAY 1 . O b tain α baseline trace .

2 . U se e q ual-le n gth coaxial cables, or t h e two 10 Χ p robes su p p lie d with t h e i n strument, to apply th e h orizo n tal signal (X-axis) to t h e C H 1 O R Χ i n p u t con n ector an d to apply th e vertical signal (Y-axis) to t h e C H 2 O R Υ in p u t connector .

3. Select Χ - Υ mode by switc h ing t h e S E C/DI V switc h to its fully countercloc kwise p ositio n .

4 . Advance th e A U TO I N T EN SITY control setting until two d ots are dis p laye d . T h e d isplay can be p ositioned h orizontally with h e H orizo n tal POSITIO N control an d ve rtically wit h t h e C h annel 2 P OSITIO N control .

t

ΝΟΤΕ

The display obtained when sinusoidal signals are applied to the Χ- and Y-axis is called α L issajous figure . This display is commonly used to compare the frequency and phase relationships of two input signals. The frequency relationship of the two input signals determines the pattern seen. The pattern will be stable only if α common divisor exists between the two frequencies.

Operating Inst ru ctions-2213 Service

T V SIG NA L DISPLAYS Displaying α T V Line-rate Signal

Displaying α T V Field-rate Signal 1 . Perform Step 1 under Displayi ng α TV L ine-rate Signal .

under Baseli n e Trace and Signal Display to obtain α basic display of t he desired TV signal .

1 . Perform the steps an d set th e controls as outlined

2. Set Α SEC/DI V to 2 ms, Α T R IGGER MOD E to TV FI ELD and Α & Β ΙΝΤ to CH 1 or CH 2 as app ropriate for the app lied signal .

2. Set Α SEC/DI V to 10 Ει s, and Α & Β ΙΝΤ to CH 1 or CH 2 as appropriate fo r applied signal .

3. Perform Step 3 and 4 under Displayi ng α TV Line- rate Signal .

3. Set Α T RIGGER SLOPE for α p ositive-goi ng signal (lever up) if the applied TV signal sync pulses are p ositivegoing, or for α negative-going signal (lever down) if the TV sync p ulses are n egative-goi ng.

4. To dis p lay either Field 1 or F ield 2 individually at faster sweep rates (displays of less than one full fiel d), set VERTICA L MOD E to BOTH and ALT simultaneously . This sync hron izes th e Channel 1 dis p lay to one field and the Ch annel 2 display to the ot her fiel d.

4. Adjust the Α T R IGGER LEVER control for α stable d isplay, an d AUTO INTENSITY for d esired display brig ht-

To change t he field that is displayed, interrupt the triggering by repeatedly setting the AC GND DC switch to GND or disco nnecting the signal from the applied signal inp ut u ntil the ot her fiel d is displayed. To display both fields simultaneously, apply the input signal to both t he CH 1 and CH 2 in puts via two probes, two cables, or through α dual-i npu t coupler.

ness . If necessa ry, adjust VERTICA L VOLTS/DI V control to obtain 5 divisions or greater am plitude fo r α stable display.

To examine either α T V Field-rate or Line-rate signal in mo re detail, either the X10 M agnifier or HO RIZONTAL M OD E functions may be em ployed as described for other signals elsewhere in this manual .

NOV 1981

2- 1 1

Section 3-2213 Service

T HE O R Y O F O PER AT I O N IN

T R OD U CTIO N

S E CTIO N ORGA N IZATIO N This section contains α functional d escription of th e 2213 Oscillosco p e circuitry. The d iscussion begi ns with α ge neral summary of instrument fun ctions followed by α d etailed desc ri ption of eac h ma jor circuit. F unctional block diagrams an d sch ematic d iag r ams a re used to s how t h e intercon n ections between parts of the circuitry, to in dicate circuit comp onents, and to identify inter relationsh i ps with the front-panel controls .

Sc hematic d iagrams and the overall bloc k d iagram are locate d i n t h e tabbed "Diagrams" section at the back of t h is manual . The schematic d iagram associate d with each d escri ption is i d entifie d in the text and indicated on th e ta b of th e a pp ro p r iate fol do ut p age by α nu mbered d iamond symbol . F or best u n d erstan d ing of the circuit b eing d escribed , refer to both the ap p ro p riate schematic d iagram an d t h e functional b lock diagram .

IN

TE G RAT E D CI RCU IT D E SC R I PTIO NS

Digital

L ogic Co nventions

Digital logic circuits perform many functions within the instru me nt. Fu nctions and operatio n of the logic circuits are re presented by logic symbology an d terminology . M ost logic functions are d escribe d using the p ositive-logic convention . P ositive logic is α system of notation whereby t h e more p ositive of two levels is th e T RUE (o r 1) state; t he more negative level is the F ALS E (or 0) state. In t h is logic descri ption the TRUE state is referred to as ΗΙ , an d t he F ALSE state is referred to as L O. Th e specific voltages wh ich co nstitute α ΗΙ or α LO state vary between specific devices. F or sp ecific d evice characteristics, refer to the manu facturer's d ata boo k.

L inear Devices

The functioning of ind ivi d ual linear integrated circu it

d evices in th is section use waveforms or ot h er techni qu es such as voltage meas urement an d simplified d iagrams to illustrate their operation.

Th eory

of Op eratio n -2213 Service

G ENER L D E A

In t h e following overall f u nctional descri ption of t h e 2213 Oscillosco pe, refe r to t h e basic bloc k d iagram ( F igure 3-1) an d to t h e d etailed b loc k diagram ( F igure 9-4) located in th e "Diagrams" section of th is man u al . In F igures 3-1 a nd 9-4, t h e num bered d iamon d symbol in eac h maj or bloc k refers to t h e a ppro p riate sc h ematic d iagram num b er . Signals to be d is p layed on t h e crt are applie d to eit h er th e C H 1 O R Χ in p ut connector or t h e C H 2 O R Υ np ut connector . T h e signals may be cou p led to th e atte nu ator circuit eit h er d irectly (DC) or t h roug h an i n put-cou p ling ca p acitor (AC) . Th e input may also be discon n ecte d and th e input to th e attenuators grounde d w h en t h e G N D p osition of t h e cou p ling switc h is use d . In t h e G N D p osition, t h e ac-cou p ling ca p acitor is allowe d to p rec h arge to th e do level p resent at t h e input con n ector . Th is p rech arging p revents large trace s h ifts of t h e d is p lay w h en switc h ing from G N D to AC cou pling .

i

E ac h c h annel out p ut signal f r om th e Atten u ator circuitry is a pp lied to th e Vertical P ream p lifier circu itry for furt h er amplification . Th e Ch annel 2 P reamplifier i nclu des an Invert feature th at allows t h e operator to invert t h e Ch annel 2 signal d is p lay on th e cat h o d e-ray tube (crt) . Trigger P ic koff Am p lifiers in eac h ch an n el supply an internal trigger signal from eith er c h an n el signal or from both ch annels to th e Internal Trigger Am p lifier in t h e Trigger circuitry . E ac h c h annel signal is selecte d for display in turn by t h e C h annel Switc h ing L ogic circuit under control of t h e front- p anel VER TICA L M OD E switc h es . Th e out p ut signal from t h e C h annel Switc h ing Logic circuit is a pp lie d to α Dio d e Gate circuit . T h e Diode Gate circuit switch es eit h er c h annel signal (or bot h signals for ADD) to α Delay L ine Driver stage t h at su pp lies t h e p ro p er drive an d im pe d a n ce matc h to t h e Delay L ine . T h e Delay Line prod u ces approximately 100 ns of d elay in t h e vertical signal to allow the H orizontal circuitry time to p ro d uce th e necessary swee p to d is p lay th e signal .

F inal am p lification of th e vertical signal is s up plied by t h e Vertical Out p ut Am p lifier . T h e Vertical Out p ut Am p lifier su p plies th e re qu ire d signal levels necessary to p ro d uce vertical d eflection of t h e electron beam in t h e crt .

t

Th e Trigger circu itry u ses eit h e r h e Internal Trigger signal d erive d from t h e input signal(s), an E xternal Trigger

3- 2

SC

R P I

signal, or α

TIO

L ine

N

Trigger sig n al o btai n ed from t h e ac- p ower-

source in put waveform to d evelo p t h e triggering signal for th e Swee p Generator. An Auto Trigger circ u it ensures th at th e range of t h e T R IGG ER LEVEL control conforms a pp roximately to t h e p ea k-to- p ea k am p litu d e of t h e trigger signal w h en eit h er A U TO or T V F I EL D T R IGG ER M OD E is selected . In N O RM M OD E , th e T R IGG ER LEVEL control must b e adj usted for t h e cor rect trigger signal level before α swee p can be generate d . Α TV Fiel d sync circuit p rovi d es stable triggering on televisio n -signal vertical-sync pulses. Triggering at t h e television line rate is accomplish e d wh en eit h er A U TO or N O RM MOD E is used . Th e Sweep L ogic circuit controls t h e generatio n of th e swee p an d t h e unblan king of t h e Ζ -Axis Amplifier for th e Swee p d is p lay . Wh en t h e T R IGG ER M OD E switc h is set to eith er AU TO or T V F I EL D an d no trigger signal is p resent, t h e Auto Baseline circuit causes t h e Swee p Logic circuit to prod u ce α s w eep after α p erio d of time . In th e N O RM p osition of t h e T R IGG ER M OD E switch t h e Auto Baseline circuit is d isable d , an d α swee p will not be generate d until α triggering signal is received . T h e outpu t gate signal from t h e Swee p Logic circ u it is a pp lie d to th e M iller Swee p circuit . T h is circuit p ro d uces α linear sweep output wit h α run-up time th at is controlled by t h e S E C/DI V switch . Th e sweep signal is a p plie d to t h e H orizontal Pream p lifier for initial amplification . F inal am plification of t h e swee p signal to d rive t h e crt h orizontal d eflection plates is provi d e d by t h e H orizontal Out p ut Am p lifier . Th e H orizo n tal P reamplifier gain is increased b y α factor of 10 w h en t h e Χ 10 M agnifier feature is used . H orizontal positioning of th e d isplay is also accom p lish e d in t h e H orizontal Pream p lifier circu it . In th e Χ -Υ M o d e of o p eration th e C H 1 signal, via t h e internal Trigger circuitry, is a pplie d to th e ΧΥ Amplifier w h ere it is am p lified for a pp lication to t h e H orizontal P ream p lifier. In t h is o perating mode, t h e C H 1 I n ter n al Trigger signal su pp lies t h e h orizo n tal d eflectio n to t h e crt, an d ' α sweep signal is not p roduce d by t h e M iller Swee p circu it . T h e H O R IZO N TA L MOD E switch ( ΝΟ D L Y, I N T EN S, an d D L Y'D) controls th e action of t h e Delay circuit . Th is

Theory of Operatio n-2213 Service

CN 1 0R Χ

CH 1 AND CH 2

"~

ΛΤΤΕΝUΛΤΟRS

CH 1

CH 2

CH 1+

CH 1 AND CH 2 VERT ICAL PREAMPS Ο

1~7

+ α

ι α

ύ ά

ύ ά

J

J

ά ω

ω Ή

ΙΝΤ L INE ΕΧΤ

AUTO NORMAL IN. TV F IELD ΕΧ7 I NPUT

~~

49

CH 1 BOTH CH 2

VERTICAL MODE

VARIABLE SEC/DIV

TIMING

CAL

Ο

S WITCH

CH 2

ΧΥ

υ

HORIZONTAL M ODE

DELAY TIME

ΙΝ 7 TRIGGER SOURCE

CRT V87θ

AUTO Ζ

X-AXIS SIG

I ΧΥ

ΧΥ SWEEP GENERATOR AND Σ-ΑΧΙ S L OGIC

ΙΝΤΕΝS

-

<

g = _

DLY

+

< g

Χ

Χ-AXIS SIG TRI G SI G AUTO BASE LINE

SIG

CH 1 VERT MODE

Ο

Ι<

Ο

TRI GGER

SIG

AM ALT CHOP

8

VAR HOLDOFF

VERT I CAL

CHANNEL S W ITCH AND VERT ICAL OUTPUT

CH 2CH 1 TRIG CH 2 TRIG

CH 2 OR Υ

SOURCE

VERT I CAL

CH 1CH 2+

F IND

BEAM

ALT SYNC

SWP

SWP

DLY'D

ι~

0 .2αια

<

&

ΧΥ ΑΜΡL/ ΗΟRΙΖ OUTPUT

ΗΟR ΙΖ ΗΟRΙΖ

\

/

7 Ο

U

ε <

1 θμα θ .5 μα

lip

ΜΙΗ.Τ 1 PL 1 ER

PROBE Λ D JUST

CRT ANODE .

Ζ -DR I VE SWΡ DUTY

A UTO INTENSITY AND Z-AXIS

ΙΝΤΕΝ S LEVEL A UTO

I NTENSI TY

Σ-DRIVE ΙΝΤΕΝS

-

P OWER SUPPLY PROBE ΛDJ> AND CR7 Ο

BEAM FI ND

LINE

TRI GGER

FOCUS INTENSITY

-

_

CATHODE

ν Lγ TO A LL BLOCKS 3827-11

F igure

'

@

3-1 .

B asic

block

d iagram

of the 2213 Oscilloscope .

3-3

T heory of Operation-2213 Service circ u it fun ctions to either pro d uce no d elay, disp lay an intensified zone on the Swee p dis p lay, or to d elay the start of the Swee p fo r α perio d of time after receivi ng α triggering signal . The d elay time is established by two front-panel controls : the DEL AY TIME switch wh ich sets th e basic d elay, an d t he MULTI PL I ER p otentiometer wh ic h increases the basic d elay b y α factor of up to twenty times. Out p ut signals from the Delay circuit are a p plie d to α logic gate circuit to control both the timing of the start of the swee p an d the Ζ-Axis drive .

The Swp Duty signal from the Sweep Logic circuit is ap plied to the Auto Intensity circuit. The Auto Inte nsity circuit provides partial cont rol of the intensity of the d is p lay when switch ing b etween different p ositio ns of t h e S EC/DI V switch .

The Ζ-Axis d rive from the Sweep L ogic circuit is app lie d to the Ζ-Axis amplifier. The output signal from the Ζ-Axis Am p lifier circuit sets the crt intensity. Α Chop Blan king signal from the Ch o p Oscillator circuit b lanks the crt d is play d uri ng the transition between the vertical channels when using CH OP VERTICA L MOD E.

The P ower Supp ly provides all the necessary o p erating voltages for th e instrument circuitry . Operating p otentials are obtained from α circuit com posed of the P reregulator, Inverte r an d Transforme r, and Rectifiers an d F ilters . The Preregulator p roduces ap p roximately +45 V from the acpower-input source wh ich is used to drive the 20-kH z Inverter stage. The Transformer secondary win d ings provide various ac levels that are rectifie d an d filtered to produce the operating voltages. Α H igh -voltage M ultiplie r circuit p ro d uces the accelerating, focus, and cathode potentials re q u ired by t he crt.

The DC Restoration circuit raises the out p ut level of the Ζ-Axis Am p lifier to allow it to be coupled to the crt control gri d . Direct co u p ling is not em ployed due to the am p litude of the voltage levels ap plied to the crt elements .

Α front- p anel PR OBE AD JU ST output is provi d ed for use in a djusti ng probe compensation . The voltage at the PR O BE ADJU ST co nnector is α negative-going sq uare wave that h as α pea k-to- pea k amplitu d e of approximately 0.5 V an d α repetition rate of app roximately 1 kH z.

D E TAI LE D CI R C U IT D E SC R I P TIO N VERTICA L ATT ENUATORS Both the Channel 1 and Channel 2 Atte nuator ci rcuits, shown in Diagram 1, are identical in operation. In the following d iscussio n, only th e Channel 1 Attenuator circu it is descri bed . The matc h ing com ponents in the Channel 2 Attenuator ci rcu it perform t he same function . T h e Atte nu ator circu it (see F igu re 3-2) p rovi des control of input coupli ng, vertical deflection factor, and variable volts- per- d ivision bala nce . Input signals for crt vertical d eflectio n may b e connected to either or both the CH 1 O R Χ and the CH 2 O R Υ i nput connectors . In the Χ-Υ M ode of operation, th e signal app lied to the CH 1 OR Χ connector provides horizontal (Χ-Axis) d eflection fo r t h e d isplay, and the signal ap plie d to the C H 2 O R Υ co n nector provides the vertical (Y-Axis) deflection for the display.

In p ut Cou p ling

The signal ap p lied to t he CH 1 O R Χ in p ut connector can be ac-cou p le d , dc-cou p le d, or internally disconnecte d from t he input of th e H ig h-Ζ In put Atte n uato r circuit.

3-4

Signals app lie d to the CH 1 in put co nnector are ro ute d t hrou gh resistor R101 to In put Co up ling switch S101 . Wh en S101 is set fo r do coupli ng, the CH 1 signal is ap p lied directly to the in put of th e H ig h-Ζ Attenuator stage. Wh en ac-coupled , the in put signal p asses th roug h R 100 and d c- blocking ca pacitor C102 . T he bloc king ca p acitor p reve nts the do compo nent of the input signal from being applie d to the Atten uator circuit. Wh en S101 is set to GN D, the direct signal pat h is opened an d the in put of the atte nuato r is connected to groun d . T his p rovi des α ground reference without th e need to d iscon nect the a p plied signal from t he in p ut connector. Th e coup ling ca pacitor is allowed to precharge th roug h R 102, α hig h-resistance component, whic h is connected across Input Coupli ng switch S101 in the GN D position .

H ig h-Ζ Attenuator

The first section of attenuator switch S105A d irects the in p ut signal to one of t h ree p at h s: directly throug h R 103 (no attenuation) ; t h roug h α 10 Χ attenuato r consisting of C105, C107, R 105, R 106, R 107, an d R 108; or t h roug h α 100Χ atte nuator consisting of C111, C112, R 110, R 111, R112, R114, an d R 115. M edium-freque ncy no rmalization of t he i n put capacitance is accomplis hed by

T heory S105

_ _ _ _Ι _ _ - _ _ _ -

νοιτ s/Dτν

Ι

CAL

s101

1

OR

Ι

Ι-

CH 1 I NPU T BUFFER AMPLIFIER U 12θ , Q122

Υ

Ι Ι

R141

[AC-G NO-DC

CH

of Operation-2213 Service

L OW-Ζ ΛΤΤΕΝUΛΤΟR

-1 > -2 .5,

Q125, Q133 ρ 131, Q139

5

VOLTS/ D IV VA R

CH 1 VER T

CH 1+

Χ1 /Χ10 ΛΜΡL U 145

SIG

TO Ρ RΕΛΜΡ

CH 1-

R 143 -8 .6 Vς JVV4- +8 . ΒVς R146

- Β . ΒV ς DIV \Γ- +8 . βVς R 138

X10 GAIN

STEP ΒΛL

LOW-Ζ ATTENUΛTOR

HIGH-Ζ ATTENU Λ TOR

L

V O TS/ DI

V 2 mV 5 mV 10 mV 20 m V 50 m V

100 m V 200 mV 500 m V 1 V

2 V 5 V

10

V

_1

- 10

L

VO TS/ DI

=1 00

Χ Χ Χ Χ Χ

Χ

Χ Χ Χ

Χ

Χ

2 V

Χ

Ι

10

V

Ι

100 mV 200 mV 500 mV

Χ

Χ

Ι

V 2 mV 5 mV 10 mV 20 mV 50 mV DI

Χ

Χ

Χ

VOLTS/

_5

Χ

Χ

100 mV 200 mV 500 mV

5 V

- 2,5

Χ

1 V

Χ Χ

_1

V 2 mV 5 mV 10 mV 20 m V 50 mV

XI/X10 ΛΜΡL

Χ

Ι

Χ

1 V

2 V

Ι

5 V

10

V

Χ1

Χ Χ

Χ10

Χ Χ Χ

Χ Χ Χ Χ Χ Χ

Χ

382β-21

F ig ure 3-2. Detailed b lock d iagram of the Channel 1 atte nu ator a nd atte nuator switchi ng ta bles.

C104 i n t h e 10 Χ attenuator and by C110 in t h e 100 Χ attenuator . Switc h S105 B connects t h e a p p rop r iate attenuator out p ut to t h e i np ut of t h e Bu ffe r Am p lifier .

B uffer Th e

Am p lifier an d Low- Ζ Attenuator

B uffer Amplifier presents α h ig h -im p e d ance, lowcapacitance load to t h e in p ut signal a nd d elivers an accurate re p lica of t h at signal to α low-impedance buffer o u t p ut circuit . T h e Low- Ζ out p ut circu it is composed of α 250-Ω voltage-divider networ k ( R 139 F t h roug h R 139J ) and t h e Volts/Div Var circuit ( R 141, C141, and R 143) . Switc h S105 B selects t h e a p p ro p riate out p ut from t h e voltage d ivider . Th e B uffer Amplifier contains two p at h s : α slow pat h consisting of R 116, R 117, U120, and R 119 in parallel wit h C119 ; an d α fast pat h th roug h C121 . T h e signals t h roug h bot h p ath s are ap p lie d to t h e gate of Q122 .

In t h e slo w -p at h p ortio n , t h e i np ut signal is d ivi d ed by te n by t h e combination of R 117 and R 116 an d is t h en a pp lie d to U 120 p in 3 . Th e B uffer Am p lifier out p u t signal is also d ivi d ed by ten by t h e combination of R 139 B , R 139C, R 139D, an d R 139 N . Su fficient dc-gate bias for input FE T Q122 is ge n erate d by th e slow-p at h circ u it to produce α null (zero d ifference) between p ins 2 an d 3 of U 120 . T h e closed-loop gain of t h e slow p ath is match e d to t h e fast- p at h gain . If t h e average output voltage from t h e fast p at h c h anges, transcon d uctance am p lifier U 120 a d j usts t h e do gate bias on Q122 to kee p U 120 p in 2 an d U 120 pin 3 nulled . T h is action k eeps th e slow-p at h an d th e fast- p at h gains matc h e d . R esistor R 119 isolates t h e output im p ed ance of U 120 from t h e in put of FE T 0122 . T h is isolatio n , i n com b inatio n wit h th e h ig h in pu t im p e d ance of U 120, p revents h igh -fre q ue n cy loading of th e in p ut signal . Capacitor C119 com p ensates for t h e output ca pacitance of U 120 .

3-5

T h eory Ste p

of Operation-2213 Se r vice

Balance p ote ntiometer R 138

adj usted to

compensate for

in pu t

(at

p in

offsets

1 of

R 139)

reac h ing

is

U 120

pins 2 and 3 wh en switching between V OLTS/DIV switch positions.

In the fast path, th e input signal is ac-cou ple d to i np ut FE T Q122 through C121 . The in put FE T is arra nged i n α source-follower config ur ation used to drive complementary emitter followers 0133 an d Q134. The combi nation of Q125, R126, R131, R132, V R 130, and R130 sets α constant cu rrent through R 125 in t he source lead of Q122 . Th e voltage d rop across R125 b iases Q133 an d Q134 for about α 10-mA idle current. Α bootstrap ci rcuit composed of Q139, VR 122, an d R 122 co nnects the Q122 drai n to the Q122 so urce. T his circuit forces the b ias voltage across Q122 to r emain constant, wh ich i n conju nction with th e consta nt b ias current su pplied by R 125, keeps Q122 operating at α constant power level to prevent d istortio n due to changing signal cu rrents . Complementary emitter followers Q133 an d Q134 su pply drive current to the =1, =2 .5, an d =5 voltage divi ders and p rovi de impedance match ing b etween in pu t FE T Q122 and th e d ivider network. The b ias levels of Q133 and Q134 are sta b ilized by emitte r resistors R 139A an d R 139 E respectively . Average voltage changes occurring in th e output of Q133 and Q134 are sensed th rough R 139B and R 139D wh ic h are connected to t he point of lowest impedance (t he emitters of Q133 an d Q134) . Resistor R 139C provi des α pat h t h at completes th e feed back loop to the slow-pat h portion of the B uffer Am plifier.

V olts/Div Var Circu it an d X1/X10 Am plifier

The appro priate voltage divider signal output (=1, =2 .5, or =5) is selected by VO LTS/DI V switch S105 B an d ro ute d to the Volts/Div V ar circ u it composed of C141, R 141, and R 143. . Changes that occur in the B uffer Amplifier output im pe d ance due to setting R 141 or switching th e d ivid er outpu t are se n sed via R 139M . These changes mo dify th e slow-pat h feedbac k signal to cause U 120 to again matc h th e gain of both path s. From the Volts/Div V ar circ uit, the signal is applied to th e in put of the X1/X10 Switc hable-gain Amplifier U 145. Am plifier U 145 produces α d ifferential output signal from the si ngle-end ed in put signal . The gain of the am plifier is controlled by the setting of V O LTS/DIV switch S105 . Am p lifier gain is changed by switch ing between two pairs of transistor am plifiers containe d in U 145. Gain of the Χ 10 am plifier pair is a djuste d by R 145 to obtai n t he

3-6

correct

d eflectio n

facto r for t h e 2m, 5m, an d 10m

DI V switch positio ns .

R esistors

8146,

R 147,

V O LTS/ R 148

an d

act to balance any do offsets between t h e Χ 1 an d Χ 10 amplifiers . Trace shift occu rri ng when the VO LTS/DI V Varia ble co ntrol is rotated is minimize d by resistor R 142 which stabilizes the in put b ias current to U 145.

VER TICA L PRE AM P S The Chan nel 1 and Chan nel 2 Pream p ci rcu itry, shown in Diagram 2, incl udes the ve rtical pream plifiers, the internal trigger pic koff am plifiers, and α common-base output stage fo r each c hannel. V ertical positioni ng of the ch annel d isplay is inco rporated in the common-base am plifier stage.

C hannel 1 Vertical P ream plifier

T he Channel 1 Vertical Preamplifier produces d ifferential output signals to dr ive the Vertical Output Am p lifier and internal trigge r signals to drive the Trigger circuitry . Differential signal current from t he Attenuator circuitry is ap plied to common-base transistors Q157 and Q167 th roug h ca ble-te rminati ng resistors R 151 and R161 respectively . The collector currents of Q157 and 0167 will flow th roug h R 158 an d R 168 to produ ce level-sh ifte d signals whic h drive U 170D and U 170E. B alance potentiometer R 154 is ad juste d to balance th e d o level of the Ch annel 1 output with the Channel 2 output by setting the bias levels of Q157 an d Q167 . Channel 1 frequency res ponse is matched to Channel 2 response b y adjusti ng C167 . Transistors U 170D and U 170E form α common-emitter amplifie r. Th e gain of U 170D an d U 170E is set by R 180 (connecte d between the emitters), an d t he h ig h-fre que ncy response is compensate d by C180 . Th e emitte rs are also co nnected to the b ases of U 170C and U 170B res p ectively to provi de an internal trigger signal p ic koff point. V ertical signal output current flows from the collectors of U 170D an d U 170E to the emitters of common-base amplifiers Q177 an d Q187 . Α s hunt resistor gain networ k ( R 176 and R 186) sets the gain of the common-base stage. Channel 1 POSITIO N control R 190 supplies α va r iable offset current to the emitters of Q177 an d Q187 wh ich allows the trace to be vertically p ositioned on the crt. The common-base amplifier stage converts the d iffere ntial signal in put current to α d ifferential sig n al output voltage th at is applied to the Diode Gate circ u itry (Diagram 3) . Channel 2 V ertical

P ream plifier

Th e Channel 2 V ertical P ream p lifier fu nctions the same as the Channel 1 V ertical P ream p lifier previously d escri bed,

Theory wit h th e exceptio n of an additional p ai r of tra n sistors th at performs t h e inverting fu nction . In th e N o r mal mode of o p eratio n , Q257 an d Q267 are biased on a n d Q258 and Q268 biase d off by I NVER T switc h S264 groun d ing one en d of R263 . In th e Invert mo d e (I NVER T switc h p ressed in), cross-wired transistors Q258 and Q268 are biased on and Q257 an d Q267 b iase d off by g roun d ing t h e ju nctio n of R256 and R266 . Invert ΒαΙ p oten tiometer R264 is ad j uste d to correct for do offsets between th e two switc h i n g-transistor pairs . Wh en R264 is correctly adj usted, α baseline t race will maintain th e same vertical positio n as t h e am p lifier is switc h ed between Invert an d N ormal . Internal Trigger

P ic koff Am plifier

Th e Internal Trigger P ic koff Am p lifier su pp lies trigge r sig n als to t h e Internal Trigge r Am p lifier in the Trigge r circuitry (Diagram 4) . Inter n al t r igger signals are p rovide d by th e vertical p ream p lifiers an d are a p plie d to t h e b ases of U 170 B an d U 170C (for Ch annel 1) and U 270 B an d U 270C (for Ch a nn el 2) . Th ese transistor p airs are biase d on, eith er in d ivi d ually or togeth er, f rom th e Internal Trigger Switch ing L ogic ci r cuit (Diagram 3) . Wh e n C h annel 1 is t h e selecte d internal trigger so u rce, Q173 an d U 170A (C H 1) will b e biase d on an d Q273 (C H 2) biase d off . Curre n t flowing t h rou g h R 173, R183, an d R197 will b ias on U 197A to kee p U 197 E c u t off . E mitter current is su p plie d to U 170A b y U 197D . In turn, U 170A t h en sup p lies emitter curre n t to U17013 and U 170C to enable th e C h annel 1 internal trigger signals to pass to t h e Inte rnal Trigger Am p lifier . Wh en C h annel 2 is selected as t h e internal trigger source, Q273 a n d U 270A will be biased on a nd Q173 biase d off . Transistor U 197A will remain on, and current su pp lied by U 197D will su p p ly emitte r c u rrent to U270A . T h en U 270A in turn sup p lies t h e emitter current to U 270 B and U 270C a n d e n a b les th e C h annel 2 internal trigge r signals to pass to t h e Internal Trigger Am p lifier . Wh en th e T R IGG ER ΙΝΤ sw itch is set to VER T M OD E , t h e actual signal source selecte d d epends on t h e setting of t h e VER TICA L M OD E switc h es . If either C H 1 or C H 2 VER TICA L M OD E is selecte d , t h e p recedi ng discussion on Ch annel 1 or Ch annel 2 internal trigger signals a pp lies . Wh en th e VER TICA L M OD E switc h is set to BOTH, the VER TICA L M OD E ADD-A L T-C H O P switc h setting determines th e switc h ing action for selecting th e internal trigger source . Selecting ADD VER TICA L M OD E causes both i nternal trigger-select signals (C H 1 Trig and C H 2 Trig) to be LO, an d bot h Q173 a nd Q273 are biased off . Transistor U 1 97A t h en becomes biase d off causing U 197 E to saturate . Wit h U 197 E saturated, emitter current is s u pp lied to bot h

of Operatio n-2213 Service

1 an d C h an n el 2 Trigger P ic koff Amplifie rs ( U 170C an d U 170 B for Ch a n nel 1 an d U 270 B an d U 270C for Ch annel 2) via R196-C R 196 a nd R 296-C R 296 res p ectively . Wh e n b ot h pic k off amplifiers are ena b led, th e resulti n g trigge r signal is t h e sum of t h e Ch annel 1 an d Ch an nel 2 i nte rn al trigger sign als . Th e su m of th e current sup p lie d b y U 197 E to bot h pic k off am p lifiers is th e same magnitude as th e curre nt from U 197D wh e n eith e r C H 1 or C H 2 is selected i n dividually . Th erefore, th e d o o u tput to th e Internal Trigger Am p lifier will be th e same for C H 1, C H 2, an d ADD VER TICA L M OD E trigger signals .

C hannel

Wh en A L T VER TICA L MOD E is selected with th e previously esta b lis h e d settings ( VER TICA L M OD E to BOTH, ΙΝΤ to VER T M OD E , an d SO UR C E to ΙΝΤ ), t h e inte rnal trigger-select signals alter n ate between c h annels . On one swee p th e C h a nn el 1 intern al trigge r will b e selecte d as previously descri be d . On t h e alternate swee p , C h annel 2 internal trigger will be selecte d , agai n as p reviously d escri b e d .

U n d er t h e same switc h -setting co nd itions, selecting C H O P VER TICA L M OD E p roduces t h e same triggerselection con d itions as d escri bed for ADD VER TICA L M OD E . T h e sum of t h e Ch a nn el 1 an d C h an n el 2 i n tern al trigger sig n als will be p assed to th e Internal Trigger Am p lifie r. See t h e "Internal Trigger Switc h i n g L ogic" d iscussion for α d escri ptio n of h ow th e internal trigger selectio n signals a re generated .

C H AN N EL S W ITC H A N D VER TICA L O U T PU T Th e Ch annel Switc h circ u itry, s h own on Diagram 3, selects t h e in p ut signal or combination of in p ut sig n als to be co n necte d to t h e Vertical O u t p u t Am p lifier . By setting t h e logic in p ut into t h e Ch an n el Switc h ing Logic circuit, VER TICA L M OD E switc h es S315 an d S317 select t h e i np ut signal com b inations to be displayed . Th e i n ter n al trigger-select signals a re also generated in t h e C h annel Switc h circuitry . Dio d e Gates

Th e Diode Gates, consisting of eig h t d iodes, act as switc h es t h at are controlle d by th e C h an n el Sw itch ing

Logic circuitry . T h e Q- an d Q-out p uts of U317A ( p ins 5 a n d 6 resp ectively) control forwar d biasing of t h e d iodes to t u r n th e gates on an d off .

C H A NNEL 1 DIS PL AY O NL Y . To dis p lay only the Ch a nn el 1 sign al, t h e CH 1 E nable signal ( U 317A p in 5) is ΗΙ an d t h e C H 2 E nable signal ( U 317A p in 6) is LO .

3-7

Th eory

of O p eration-2213 Service

W it h C H 1 Enable ΗΙ , gate diodes C R 187 and C R 177 are reverse biased (see F igure 3-3) . Series gate d iodes CR 188 and C R 178 are forwar d biased, an d t he Channel 1 vertical signal is allowed to pass to th e Delay L ine Driver . Α LO CH 2 E na ble signal ap p lied to th e Channel 2 gate d iodes forwar d biases CR 287 an d C R277, an d t he C h annel 2 vertical-signal current is sh unted away from series diodes CR288 and C R278. The C hannel 2 series d iodes are reverse biased, an d t h e C hannel 2 signal cu rrent is prevented from reac h ing the Delay L ine Driver .

C HANNEL 2 DISPL AY ONL Y. Wh en CH 2 VERTICA L is selected, the C H 1 E nable signal goes LO an d th e

M OD E

CH 2 E nable signal goes ΗΙ . The Channel 1 signal is bloc ked, and the Chan nel 2 signal reac h es the Delay L ine Driver .

ADD DISPL AY. Bot h Diode Gates are biased on to pass t h e C hannel 1 an d C hannel 2 vertical sign als. The channel signal currents are summed at t h e input to th e Delay L ine Driver . The Add E nable signal su pp lies the extra current require d to kee p bot h Diode Gates forwar d biase d an d to maintain th e proper d o level at the b ase of th e Delay L ine Driver in put tra nsistors (Q331 an d Q341) .

A L T ERN AT E A N D

C H O PPE D DIS PL AY.

Diode

Χ-Υ DISPL AY . Setting th e S EC/DI V switch to t h e Χ-Υ position activates the Χ-Υ dis play featu re . The Channel 1 Diode Gate is h el d off, and t h e Channel 2 Diode Gate is b iased on . The Ch annel 2 signal is passe d to the Delay L ine Driver and u ltimately to t he crt to provide the Υ-Axis display deflection . The X-Axis d eflection signal is su pp lied to the ΧΥ Am plifier (Diagram 7) from the C h annel 1 signal via the Internal Trigger Amplifier (Diagram 4) . Delay L ine Driver

The Delay L ine Driver co nverts the signal current from the Diod e Gates into α signal voltage for application to t h e Delay L ine. The Delay L ine Driver is configured as α d ifferential shunt feedback am plifier and is composed of Q331, Q335, Q341, a n d Q345 . In put cu rrents to common-

FR O M

VERT ICA L S IGNAL TO DEL AY L INE D RIVER

CHANNEL

SWITC HING L OGI C

S IG N A L

ADD EN ABLE

F ig ure 3-3. Diode gate biasi ng fo r α C hann el 1 display.

3-8

Th e

Gates are switch ed on and off by the Chan nel Ena ble signals from the Channel Switc hing L ogic circuit. Wh en A LT VERTICA L MOD E is selected, th e Diode Gates are switched at t h e end of each trace. F or CHOP VERTICA L MOD E , th e gates are switched at α rate of about 250 kH z.

PATH

$ REVERSE BI ASED DIOD E 3826-25

Th eory of Operatio n -2213 Service transisto rs

emitter

at

voltages

t he

E mitter-follower

drive

th e

C335 and by

R

R 340

336 a n d

Delay

Delay

Q331

bases

L ine

C340,

R 345 .

and Q335

Q341

are

and

Q345

converted

to

respectively .

o u t p ut transistors Q335 an d Q345 t h e n

R 345-C345.

an d

of

t h roug h an d

R 335p rovi d e d

reverse termi n ations

Amp lifier com p ensation is

s h unt fee d bac k is s u pp lie d by

L ine

Delay L ine D L 350 p rovi d es a b out 100 ns of d elay in th e vertical signal . Wh en using inter n al triggering (C H 1, C H 2, or VER T M OD E ), t h e delay time allows t h e Swee p Generator sufficient time to produce α swee p before t h e vertical signal reach es t h e crt d eflection p lates . T h is feature p ermits viewing t h e lea d ing e d ge of th e internal signal th at originates th e trigger pulse .

Vertical

Outp ut Am p lifier

Th e V ertical Output Amplifier, also sh ow n on Diagram 3, provi d es final am p lification of t h e in pu t signals for a pp lication to t h e d eflection p lates of t h e crt . Signals from th e Delay L i n e are a pp lied to α d ifferen tial amplifier in p ut stage com posed of Q350 an d Q360. T h e Delay L ine is terminate d in th e p ro p er im p edance by resistors R338 an d R348 . Resistor R355 sets th e gain of Q350 an d Q360 . T h ermal com pensation of t h e stage gain is p rovi d ed b y th ermisto r R T356, connected in series wit h R 356 across R355. T h e RC networ k s connecte d across R355 p rovide bot h low- and h ig h -frequency com pensation of t h e stage . Th e d iffere n tial out p ut is app lie d to output transistor p airs Q376-Q377 an d Q386-Q387 . T h ese transistors form α common-emitter s h unt-fee d bac k am p lifier stage, with R 376, R377, R386, an d R387 serving as feedb ac k eleme n ts . Capacitors C377 an d C387, co n nected across R377 and R387 respectively, p rovi d e increasing negative feedb ac k as t h e signal fre q uency rises to limit t h e amplifier bandwi d t h at th e u pper fre q uency limit . Out pu t voltage from t h e amplifier is d ivided between t h e two transistors of eac h h alf . T h e signal voltage applie d to th e crt vertical deflection p lates is t h e sum of voltage d rops across t h e p airs (Q376Q377 an d Q386-Q387) . T h e deflection voltage is p rop ortional to th e sig n al current d riving th e bases of 0376 a nd Q386 . BEAM F I N D switc h S390 (Diagram 6) normally s u pp lies -8 .6 V directly to R390 to set t h e stage bias . Wh en t h e BEAM F I N D butto n is p ressed in an d h el d , th e d irect voltage is removed an d t h e -8 .6-V bias is p rovi d e d via series resistor R391 . T h e output voltage swing is t h ereby re du ced to h old t h e vertical trace d eflectio n to wit h i n t h e graticule area .

Ch annel

Switch ing

L ogic

Circuit

Switch ing Logic circuitry compose d of d U 317A selects eit h er Ch a n nel 1 or C h annel 2 U310A an an d vario u s d is p lay mo d es for crt dis p lay via fron t-panel switch es an d th e Χ - Υ position of th e S E C/DI V switc h . Th e

C h annel

M

ode, signal Wh en t h e instrument is not i n t h e Χ - Υ line ΧΥ is gro u nde d th roug h contacts on t h e S E C/DI V switc h (Diagram 8) . Th is actio n esta b lis h es LO logic levels on p ins C, Β , and G of front-panel switc h S317 (CH 1BOTH-CH 2) a nd on pins C a nd Β of S305 (I NT) .

Switc h S317 selects t h e ve rtical c h a n nel signal t h at d rives th e Delay Line Driver via t h e C h an n el Diode Gates . With S317 set to C H 1, α L O is ap p lie d to th e Set in p ut ( p in 4) of U 317A . F li p -flo p U 317A will th en be set, a n d t h e Q output ( p in 5) will be ΗΙ . P in 5 of U 317A is the C H 1 En able signal line, and w h en it is ΗΙ , th e Ch annel 1 vertical signal is gated to t h e Delay L ine Driver . Wh e n S317 is set to C H 2, t h e Reset in pu t of U 317A ( p in 1) will b e h el d L O th rough C R 705 . T h e C H 2 E nable signal ( U 317A, p in 5) is th en set Η Ι an d t h e C h annel 2 vertical sig n al is gated to t h e Delay

L ine

Driver .

Setting S317 to t h e BOTH position removes t h e L O from bot h t h e Set an d Reset inputs of U317A . T h is action allows t h e ch annel selected for d is p lay to be determined eit h er by t h e logic level app lie d to t h e D in pu t ( p in 2) and t h e cloc k ap plied to pin 3 or by th e logic level a pp lied to t h e Set a nd R eset i np uts from t h e ADD-A L T-C H O P switc h .

Th e ADD-A LT-C H O P switc h (S315) is enabled b y t h e LO place d on pi n s Α , C, and F wh en t h e C H 1-BOTH-CH 2 switc h is set to BOTH . Wh en in ADD, S315 h ol d s bot h t h e Set an d R eset input of U 317A LO t h ro u g h C R 706 and C R 701 res p ectively . T he Q an d Q out p uts of U 317A will t h en b e ΗΙ , an d both Ch annel 1 an d Ch annel 2 vertical signals are gate d to th e Delay L ine Driver. T h e sig n al cur r ent is summed at t h e input to t h e Delay L ine Drive r , an d t h e resulting oscilloscope Add vertical disp lay is th e algebraic sum of t h e two vertical signals .

Th e Add E nable circuit, com p osed of Q316, U 197C, an d U 315A, is activated wh en b oth Dio d e Gates are turned on for an A dd vertical d isplay . With th e Q an d Q outpu ts of U 317A ΗΙ , t h e o u tpu t of U 315A will be LO and transistor Q316 is biased on . Th e collector of Q316 rises toward +5 V an d U 197C is b iase d on . Transistor U 197C supplies t h e additional current re qu ired to k eep both Diod e Gates fo rward biase d an d to su pp ly t h e p ro p er d o level to t h e Delay L ine Driver input . By pass ca pacitor C316 prevents switch ing transients from being introduced into t h e Delay L ine Driver by t h e Add E nable ci rcuit .

3- 9

Th eory of O peratio n -2213 Se rvice Wh en S315 is set to A L T, α ΗΙ is place d on bot h th e Set a nd R eset inputs of U 317A . F li p -flo p U 317A will transfe r t h e logic level on t h e D in p u t (pin 2) to t h e Q output ( p in 5) on each clock -pulse rising e d ge . P in 1 of N A N D-gate U 310A is h el d Η Ι b y th e Ch op Oscillator out pu t, a nd p in 2 follows th e Alt Sync sig n al p rod u ced by th e H oldoff circuit ry in th e Α Sweep Generator (Diagram 5) . T h e ou t p ut of U310A ( p in 3) is t h erefore an inverted Alt Sy n c pulse . T h e signal on th e D in p ut of U317A ( p in 2) follows t h e logic level set by the Q outpu t p i n . As eac h cloc k pu lse occurs, t h e states of t h e Q a nd Q outputs reverse (toggle), enabli n g C h a n nel 1 and Ch annel 2 Dio d e Gates altern ately wit h eac h sweep .

CH O P OSCI LL ATO R . Setti n g S315 to C H O P enables t h e Ch op Oscillator an d t h e C h op B lan k i n g circuit . P ins C an d D of S315 are connecte d to p lace α L O logic level on t h e Set in put (pin 10) of U 317 B . T h e Q ou t p ut of U 317 B is set ΗΙ an d t h e Ch op Oscillator is allowe d to ru n . Α ΗΙ level is p resent on U 310D p in 13 due to C308 b ei n g c h arged to t h e ΗΙ level on U 310D pi n 11 . Wh e n p in 12 of U 310D also goes ΗΙ , th e output of U 310D goes L O . Ca p acitor C308 now must d isc h arge to t h e new d o level . As soon as th e c h a rge of C308 reac h es t h e LO t h resh ol d level of U 310D, t h e output at pin 11 switch es ΗΙ again an d C308 c h a rges towar d t h e ΗΙ logic level (see Figure 3-4) .

Wh en t h e ΗΙ switc h ing t h res h ol d level is reac h ed , t h e out p u t of U 301D c h anges state to L O again . Th is cycle continues at about 500 kH z to p ro du ce b oth th e C h o p Clock and th e Ch o p Bla nk signals.

T h e Ch o p signal is gated t h r o u g h N A N D-gate U 310C a n d a pp lied to U 310A p in 1 . Th e Alt Sy n c p ulse on U 310A pin 2 is ΗΙ (except during h ol d off time) so t h e out p ut of U 310A p in 3 is t h e inverte d Ch o p Oscillator sig n al on p in 1 . Th is sig n al is app lie d to t h e Cloc k In put ( p i n 3) of U317A to d rive t h e C h annel Switc h i n g circuitry . Since fli p flo p U 317A cloc k s wit h rising e d ges only, t h e fre q uency of t h e c h o pp ed ch annel switc h ing is about 250 kH z . T h e signal outp ut from U 310C p in 8 is also fed to th e C h op Blan k ing circu it . Capacitor C311 an d resistors R310 an d R311 form α d ifferentiating circuit t h at p roduces p ositive an d negative s h ort-du ratio n pu lses wh en th e Ch o p Oscillator sig n al c h anges levels . T h e do level at U 310 B p ins 4 an d 5 is set slig h tly above t h e ΗΙ switc h ing t h res h old logic by α voltage divi d er consisting of R310 an d R311 . Positive pulses from C311 continue to h ol d U 310 B above th e th resh ol d level, so t h e o u tput remains LO . N egative pulses from C311 d rop below

3- 1 0

t he th res h ol d level of U 310 B , an d t h e out p ut of U 310 B switc h es ΗΙ for α d uration of a bout 0 .4 μ s (see F igure 3-4) to p rodu ce t h e positive Ch o p B lan k ing pulse . Th e C h o p Blan k ing p u lse is fe d to t h e Ζ -Axis Am p lifier an d is used to prevent d isplay of th e t r ansistio n s w h en switch i n g betwee n vertical ch an n els .

Internal Trigger Switch ing

L ogic

internal trigger-selection sig n als to th e Trigger Pic k off Amplifier (Diag r am 2) a r e p ro d uce d n α logic circ u it compose d of U 305 B , U 305C, U 305D, U 315 B , a nd U 315C . Th e T R IGG ER ΙΝΤ Source switch (S305), i n co nju nction wit h C H 1-BOTH-CH 2 switc h (S317), determi n es t h e i n ternal trigger sou r ce selected . Wh en eit h er th e C H 1 o r C H 2 Internal Trigge r signal is selecte d b y S305, t h e selected ch a n nel will be t h e i n ter n al t r igger so u rce . Wh en VER T M OD E is selected as th e i n ter n al t r igger signal, t h e positio n of S317 determines th e ch a nn el(s) selecte d as t h e i n ternal trigger sou r ce .

i

C H A NNEL 1 SO UR C E . Th e ΧΥ signal li n e from th e Α S E C/DI V switch (S630 B ) a pplies α LO logic level to ΙΝΤ switc h S305 on p ins Β an d C . In th e C H 1 p osition, th e L O is cou p le d from p in C to p in D an d ap p lie d to U 305 B pin 4 .

The

LO

is gated t h roug h U 305 B a n d a p p lied to th e C H 1

Trig sig n al line i n α wire d -A N D connection . Th e L O from U305B is a pp lie d to Q273 i n t h e C h a n nel 2 Internal Trigger P ic k off Amplifier (Diagram 2) to bias it off, t hu s p reventing th e Ch a n nel 2 signal from being selecte d . Operation of th e Internal Trigger Pic k off Am p lifiers is disc u sse d in th e "C h a nn el 1 and Ch annel 2 P reamps" circuit d escri ptions. Concurrently, p ins 9 an d 10 of U 305C are pu lle d ΗΙ th ro u gh R 304 an d R300 respectively to place α ΗΙ at U 305C p in 8 . Th e ΗΙ fro m U 305C to t h e wire d -A N D connection on th e C H 2 Trig sign al li n e en a b les th e out p ut of U 315 B to control t h e logic level of t h e C H 2 Trig signal . Control is accom p lish e d by th e logic levels on t h e in pu ts of U 305D, pins 12 an d 13 . Th e L O on U 305 B pin 4 ( p laced t h ere by S305) also occurs on U 305D p in 13 . T h is ensures α LO at U 305D p in 11, w h ic h is a pp lie d to U 315C pin 9 an d to U 315 B pin 5 . T h e logic l evel a p p lied to U 315C pin 9 h as no effect on th e C H 1 Trig signal because α LO is alread y p resent at t h e wire d -A N D connection to th e signal line . H owever, t h e L O a p p lie d to U 315 B pin 5 ensures t h at th e out p u t of

U 315 B is ΗΙ . Wh en t h e C H 2 Trig signal is ΗΙ , Q173 i n t h e C h an n el 1 Internal Trigger P ic koff Am p lifier is biase d on an d t h e Ch annel 1 signal is p assed to th e Internal Trigger Amplifie r (Diagram 4) .

Theory of Operation-2213 Se rvice

CHOP OSCI LLATO R U310C, PIN 8

+5 0

INPUT TO U31 0B,

PINS

4&5

0

ι

Ι

C HOP

BLANKING PULSE U 10B, PIN 6

C H O P C LOC K U 317A, PIN 3

+5

THRESHOLD Ι

0 .4μs

0

+5-9

0 +5 CH 1 EN ABLE U 317A, PIN 5

Ε`

4μs

0 +5

CH 2 ENABLE U317A, PIN 6

0 3826-23

F ig ure 3-4. CHOP VERTICA L MOD E wavefo rms .

CH ANNEL 2 SO UR CE. W hen S305 is set to CH 2, the L O logic level present on S305 pin Β is couple d to p in Α an d ap plied to U 305D p in 12 and to U 305C p in 10 . The output of U 305C at p i n 8 is α L O wh ic h is app lied to the CH 2 Trig signal line by the wired-AN D con nection . Wh en th e CH 2 Trig signal is LO, the Chan nel 1 Internal Trigge r Pic koff Am plifier is biased off to prevent th e C hann el 1 signal from reach ing the I nternal Trigge r Amplifier. The inputs to U 305B , pi ns 4 an d 5, are both pulled ΗΙ thro u gh R305 an d R 304 respectively, an d t he ΗΙ output from pin 6, applie d to t he wire d -A ND connection on the CH 1 Trig signal line, allows U 315C to control the CH 1 Trig signal logic level. As d escribed in th e precedi ng "Ch annel 1 So urce" disc ussion, the logic levels at U 305D p ins 12

U 315B. Th e L O on U305D pin 12 ensures α L O outp ut at pin 11, wh ic h is app lie d to U315C at pin 9. Th is L O ensu res α ΗΙ output at U 315C pin 8, the CH 1 Trig signal line . a nd 13 control th e outpu t of

W ith the CH 1 Trig signal ΗΙ , Q273 in th e Ch an nel 2 Trigger P ic koff Am plifier is b iase d on and t h e C h a n nel 2 signal is passed on to th e Inte rnal Trigge r Am plifier .

VERT MOD E SO UR C E. Additiohal switch settings are involved in d etermining the internal trigger signal selection when VERT M OD E Trigger Source is selected. Both t he CH 1-BOTH-CH 2 an d t he ADD-A LT-CH OP VERTICA L MOD E switch es establis h t he vertical signal d isplay an d, as

3- 1 1

Th eory

of Operation-2213 Se rvice

suc h , must also be use d to obtain th e internal vertical mode trigger signal .

Wh en S305 is set to VER T M OD E , t h e L O logic level on t h e ΧΥ signal line is remove d from bot h U 305 B p in 4 an d from U 305D pins 12 an d 13, pulling th ese i nputs ΗΙ . In eit h er ADD or A L T VER TICA L M OD E, U 305C pin 9 and U 305 B pi n 5 are also pulled ΗΙ w h e never α L O is not bei n g applied from 5315 . Th e in pu t conditions j ust desc r i bed for U305 B , U 305D, an d U 305C allow t h e logic levels on U 315 C p in 10 and U 315 B pi n 4 to control t h e states of th e C H 1 Trig an d

Α CH O P VER TICA L MOD E disp lay also uses t h e su m of t h e two i n ternal trigger signals, bu t th e switch ing logic involved is d iffere n t from t h e ADD VER TICA L MOD E d is p lay . Wit h S315 set to C HO P, α L O logic level is applied to U 305 B p in 5 a nd to U 305C p in 9 from th e ΧΥ signal line via contacts on S315, S317, a nd S305 . Th e outpu ts of both U 305C and U 305 B are L O an d are appli ed to th e wire d-A N D connection on t h e CH 1 Trig and C H 2 Trig signal lines . Th ese LO signals over r ide th e out p uts from U 315C an d U 315 B to h ol d h e in p ut transistors of b oth Ch annel 1 and Ch annel 2 Trigger P ic k off Amplifiers biased off . C h annel 1 an d Ch a n nel 2 Trigger signals are summe d as describe d pr eviously fo r h e ADD VER TICA L M OD E dis p lay .

t

t

CH

2 Trig trigge r -selection sig n als . In p ut sign als to p i n s 10 an d 4 are o b tained from t h e C h annel En able signals p rese n t at pins 5 a nd 6 of Ch annel Switc h U 317A .

Wh en C H 1 E na b le is ΗΙ (selecting th e Ch a n nel 1 sig n al for d isplay), U 315C p in 10 is also ΗΙ a n d U 315C pi n 8 is L O to d isable th e C h annel 2 Trigger P ic k off Amplifier . Concurrently U 317A p in 6 a pp lies α LO to U 315 B p in 4, and th e ΗΙ out put o btained from U 315 B p in 6 as α res u lt enables th e Ch annel 1 Trigger P ickoff Am p lifier .

F or

A L T VERTICA L M OD E disp lays, t h e out pu t states of C h annel Switc h S317A are switc h e d alternatel y, at t h e en d of eac h swee p , in sync h ronization wit h t h e Alt Sync signal . Th erefore, on alternate sweeps, t h e logic levels on U 315C p in 10 and on U315 B p in 4 also c h a nge states .

Wh en t h e C h an n el 1 sig n al is bei n g d isp layed, t h e Ch a n nel 1 Trigger sign al is selecte d as th e internal source . F or Ch annel 2 signal d is p lays, th e Ch annel 2 Trigger sign al is selected .

An ADD VER TICA L M OD E d isp lay causes both pin 5 and p in 6 of U 317A to b e ΗΙ (see "Ch annel Switc h i n g Logic" d iscussion for α description of t h e circuit operation) . Th e sum of t h e two ch annel vertical signals is d isp laye d , an d t h e sum of t h e two c h an n el trigger signals is use d as t h e internal trigger signal .

Summation is accom p lis h ed by t h e ΗΙ logic levels from U 317A pins 5 an d 6 causing b oth t h e C H 1 Trig and C H 2

Trig signals to go L O . Wit h t h e in put transistors to bot h Trigger P ic k off Am p lifiers biased off, a dd itional circuitry wit h in t h e Trigger P ic k off am p lifiers biases on t h e p ic k off transistors for bot h C h annel 1 an d C h annel 2 (see t h e Ch annel 1 an d C h annel 2 P ream p lifier circuit d escriptions .

Χ - Υ M OD E . Wh e n t h e S E C/DI V switc h is set to Χ - Υ , t h e C h a n nel 2 signal is selecte d as t h e in put to t h e Vertical Out p ut Amplifier to provide t h e Χ -Axis d eflection . Th e Ch annel 1 Trigger signal p rovides t h e Χ -Axis signal to t h e ΧΥ Am p lifie r (Diagram 7) via t h e Internal Trigge r Am p lifier. T h erefore, t h e Trigger Switc h ing Logic circu it m u st h ave in p uts th at ena b le th e Ch annel 1 Trigger P ic koff Am p lifie r.

T h e L O logic level signal su pp lied by th e ΧΥ signal line to S305 a nd S317 is removed by switc h ing contacts on t h e S E C/DI V switc h . Concurrently, α L O logic level is place d on th e ΧΥ signal line by contacts on th e S E C/DI V switc h .

Th e L O on t h e ΧΥ line is a p plied to t h e Reset input of U 317A to select t h e C h annel 2 sign al for d is p lay . T h is L O is also a pp lied to U 305 B p in 4 an d to U 305D p in 13 via U 305A to set up th e Trigger Switc h ing Logic th at enables t h e C h annel 1 Trigger P ic k off Am p lifier.

Α LO on U305 B pin 4 ensures th at t h e out pu t of U 305 B pin 6 is α LO, w h ic h is a pp lied to th e C H 1 Trig signal line to d isable th e Ch annel 2 Trigger P ic k off Am p lifier . Th e LO on U 305D p i n 13 is gate d to U 315 B p i n 5 . Wit h U 315 B p in 5 L O, t h e out p ut of U 315 B will be α ΗΙ t h at, w h e n AN De d wit h th e ΗΙ p resent from U 305C p in 8, e n ables t h e C h annel 1 Trigger P ic k off Amplifier .

T R IGG ER T h e Trigger circuit, s h own on Diagram 4, is compose d of t h e Internal an d E xternal Trigge r Am p lifiers, Sou rceswitc h ing circuit, an d Trigger Generator circ u it . Include d in th e Trigger Generator circuit is t h e Auto Trigger an d Auto Baseline circuitry a nd h e T V Triggering circuitry .

t

Theo ry of O peration -2213 Service Internal Trigger Am p lifier

Th e Internal Trigger Am p lifier converts th e d ifferential curre n t input f r om th e Trigger P ic koff circuit to α ze r oreference d , si n gle-e n de d out put for use by t h e Trigge r Level Comparator. Differential signals from t h e P ic k off Am p lifier ci r cuit are co n necte d via R421 and R422 to common- b ase transistors U421 E an d U421 D respectively . Transistor U 421C an d R428 co n stitute an i nverting-feed back am p lifier t h at co nverts U 421D collector c urrent to α voltage at th e collector of U421 C. Th is voltage is adde d n p h ase with t h e voltage dro p across R427 produce d by t h e signal current of U421 E . T h e resulting sum is α single-ende d voltage sig n al th at is a p p lie d to t h e base of emitter-follower U421 A . The emitter-follower stage p rovi d es a low-output-impedance signal source th at d rives bot h t h e ΧΥ Am p lifier (t hroug h R 701) a n d emitter-follower U421 B . T h e out put signal from U421 B is ap p lie d to t h e Trigge r Source Switc h ing Dio d e circuit at t h e cat h o d e of C R 440 w h ere it is available for selectio n as t h e triggering signal .

i

Trigger Source-Switch ing Circuit Trigger signal selection is accom p lis h e d by using t h e SO UR C E switch (5440) to ena ble o n e of t h ree triggering signal p at h s (internal, external, or line) to th e Trigger L evel Comparator circuit . With S440 set to ΙΝΤ , t h e i nh ibiting voltage is removed from R438, causing bot h U421 B a nd d io d e C R 440 to be biase d on . The internal trigger signal is t h en passe d from t h e emitte r of U421 B t h roug h d io d e C R 440 to t h e T r igger Level Comparato r an d Auto Trigger circuits. Th e SO UR C E switc h preve n ts t h e li n e an d external triggering signals from reach ing t h e Trigger Level Comparator by reve rse biasing d iodes C R444 an d C R 448 an d also by reverse b iasing Q414 and C R 418 t h roug h R 417 . Wh en S440 is set to L I N E, U 421 Β an d C R 418 are b iased off t h roug h R 438 an d R 417 respectively, w h ile C R444 is enable d by removal of t h e in h ibiti n g voltage from R446 . Similarly, wit h 5440 set to ΕΧΤ , th e external trigger signal is selecte d b y b iasing off C R444 an d U 421 B th rough resistors R444 a nd R 438 respectively an d by ena b ling Q414 t h roug h t h e removal of t h e in h i biting voltage from R417 .

E xternal

Trigger Am p lifier

Th e E xternal Trigger Am p lifier provides α means of triggering t h e instr u ment from an externally s u pp lie d signal t h at can be a pp lie d to th e ΕΧΤ I NPU T connecto r . Input cou p ling to t h e Amplifier is selectable by th e t h ree-p osition ΕΧΤ CO UPL I N G switc h , 5401 . In t h e AC positio n , t h e do component of t h e extern al trigger sig n al is bloc k ed by coupling t h e signal th ro u g h C402 . In t h e DC position, all components of t h e signal are cou p le d d irectly to t h e gate of Q41 1A t h rou g h an i n put divider compose d of R404 and R408 . Resistors R402 an d R403 fo r m α voltage-divi d er n etwor k t h at atten u ates t h e signal by α factor of 10 w h enever 5401 is set to DC+10 .

F ield-effect tra nsistors Q411 Α an d Q411 Β are α matche d p air . Source-follower Q411A pr ovi d es α h igh input impeda n ce for t h e external trigger signal . Cu rre nt-source transisto r Q411 Β causes Q411 Α to operate at zero gate-tosou r ce b ias, so th e device f u nctio n s w it h no do offset b etween t h e in p ut an d output signals . T h e out put signal from t h e source of Q411A drives t h e b ase of emitter follower Q414 . Th e emitter-follower stage lowers t h e output im p e d a n ce of t h e Trigger Am p lifie r an d functions as p art of th e Trigger Source Switc h ing circuitry .

Auto Trigger Circuit Wh en eit h er AU TO or TV F I EL D triggering is selecte d, t h e Auto Trigger circuit detects p ositive a n d negative p eak s of th e in p ut trigger signal a n d prod u ces output voltages t h at set th e T R IGG ER LEVEL control range to wit h in t h e pea k -to-pea k am p litu d e of th e triggering signal . T h e pea k detectors are d isable d wh en S611 is set to N O RM, an d fixe d voltage levels are app lie d to both en d s of T R IGG ER LEVEL p ote n tiometer R455 . In eit h er A U TO or TV F I EL D, t h e T R IGG ER M OD E switc h (S611) opens t h e Auto Disable signal line to allow C R 503 and C R 504 to become reverse b iased . T h is actio n isolates th e voltage d ivi d er n etwork (compose d of R525, R527, R528, R526, an d Q519) from th e + in puts of U 507A and U 507 B . Th e pea k detecto rs (com posed of Q503 for th e positive peak a n d Q504 for t h e negative p ea k ) become ena b led w h en t h e A uto Disable signal is remove d . T h e trigger signal is applie d to t h e bases of Q503 an d Q504 via R444 . Positive trigger signal p ea k s b ias Q503 into co nduction, cau sing its emitter voltage level to rise to t h e p ea k level of th e trigge r amplitu d e min u s th e b ase-toemitter voltage dro p .

Ca pacitor C503 c h arges up to t h e positive emitter voltage level . T h e c h arge is retained between trigger p u lses due to th e long RC time constant of R505 and C503. T h e com parator voltage is a pp lied to U 507A p in 3 w h ic h is α voltage follower an d level s h ifter th at sets t h e voltage at one end of t h e T R IGG ER LEVEL p otentiometer (13455) . Transistor Q507 p rovides t h e feedbac k pat h for U 507A an d t h ermally compensates fo r Q503 . Th e base-to-emitte r d ro p of Q507 corrects for t h e d o offset introduced by Q503, an d potentiometer R511 is adj usted to balance out d o offsets introduce d from t h e trigger circuitry . T h e negative pea k d etector operates in t h e same manner as t h e p ositive p ea k d etector, with correspon d i n g com p o n ents pe rforming t h e i d entical circuit functio n on th e trigger-signal negative pea k s .

Theory of Operation-2213 Se rvice Wh en S611 is set to N O RM, +8 .6 V is applie d t hroug h he t switch to R 525 and R 517. Transistor Q519 is b iased into saturation by the p ositive voltage, an d both C R 503 an d C R504 become forwar d biase d . Th is action reverse b iases p ea k detector tra nsistors Q503 and Q504 to pr event the trigger sign al from affecting the TR IGG ER LEVEL co ntrol ra nge . W ith C R 503 an d C R504 forward biased, the voltage d ivi d er network (R525, R 527, R 526, a nd R 528) sets the in pu t voltage to U 507A pin 3 and U 507 B pin 5. Α fixed p ositive output voltage from U 507A p in 1 is ap plied to one

en d of R 455, and α fixed negative outpu t voltage from U 507 B pin 7 is applie d to th e oth er en d of R 455.

Trigger

L evel

Comp arator

The Trigge r Level Comparator circuit dete rmi n es both

t he trigger level and slope at which α triggering signal is

prod uced. Transistors U 460E an d U460B form α comparator circuit. It compares th e t rigger signal level applie d to the base of U 460E with t he reference d o level set by the TR IGG ER L EVEL potentiometer ( R455) and applie d to the base of U 460B . Slope switching is accomp lis h ed by controlli ng the biasing of transistor p airs U 460A- U460D an d U460C-U460F. Wh en AUTO or TV FI EL D triggering is selected, the Auto Trigger circ u it maintains α do level r ange at the b ase of U 460B th at is de pen dent upon the am plitu d e of the trigger in put signal . In th is in stance, th e Comparator (U460 E an d U 460B) determines t h e p oint on th e input trigger waveform at whic h the Sc hmitt Trigger circuit will pro d uce an outp ut. Wh en N O RM triggering is selecte d , t he TR IGG ER LEVEL potentiomete r ( R455) is set manually to α do level that will produce α trigger signal at the o utput of the Comparator . If t he trigge r signal amplitude at t he base of U 460E is below th e reference level, th e Sch mitt Trigger circuit will never switch. If the trigger signal is above the reference level, the Sch mitt Trigger circuit ou tput will switch ΗΙ an d remain ΗΙ until either the trigger signal is decrease d or the reference d o level is increased.

The TR IGG ER SLOPE switch (S464) controls th e

b ias on U 460C an d U 460F. Wh en set to the p ositive slope position, the groun d is removed from the b ottom end of R 464, and th e forwar d bias is then d etermined by th e voltage d ivi d er formed by R 462 and R 463. B ot h U460C an d U 460 F are biased into con d uction an d carry t he signal cur rent from the Com p arator transistors . M oving the S LOPE switch to the negative slope p ositio n g rou nd s the b otto m of R 464 and re d uces the b ias level of U460C an d

3- 14

U 460F . The fixed bias level on the bases of U 460A and U 460D is now h ig her th a n t he bias on U 460C an d U 460 F so that U460A an d U460D carry the signal curre nt from the Comparator transitors. T he collectors of U 460A an d U460D are cross connected to the collectors of U 460F an d U460C, so the resulti ng trigger signal output is i nverte d .

Inverting Amplifier an d

TV Trigger Circuit

C urrent from one transistor of th e conducti ng p ai r of tra nsistors chosen by S LOPE switch 5464 is applied to U480C pi n 10 . Current from the other si de of th e Comparator is applie d to p in 14 at the outpu t side of U 480C th rough R468. P in 11 of U 480C is at α LO logic level exce pt when TV F I EL D triggering is enabled. Th is L O d oes not affect ci rcuit operation in either AUTO o r NO RM triggeri ng.

N O R -gate U 480C is an emitter-cou ple d logic (E CL) device th at is operate d in the li near region. In t he linear

region, U 480C acts as α high-speed inverting amplifier. Common-mode signals such as noise or th ermal d rift in the Comparator output signal are cancelled by U 480C an d associate d circuitry . These ty p es of offsets eq ually affect t h e o utputs from b ot h si des of the Comparator . Ch anging current to p in 10 of U480C causes α corresponding voltage change at U480C pin 14 . The voltage change at one end of R468 is equ al in amount and o pposite in d irection to the voltage change at the ot her en d since the same common -mo d e signal from th e ot h er h alf of the Com parator is applie d to the oth er en d of R 468.

Wh en th e TR IGG ER MOD E switc h is set to TV F I EL D, +8 .6 V is ap plie d to t he T V Trig E nable signal line . Transistors Q474 an d Q476 are b iase d on via R 474, an d U480C p in 11 is set ΗΙ , causing th e output of U 480C at p in 14 to be LO . Current flowing t h ro ugh R 466 from either U460C or U 460D causes α voltage drop that esta blishes th e b ias

voltage on the base of Q474 . Current flowing th rough R473 an d R 472 p ro du ces α voltage dro p across R 473 that esta blishes t h e bias voltage on the base of Q476 . Th e ci rcuit com ponents are selected such that when the Compa rator output voltages from both h alves are equ al, t he base voltages to both Q474 and Q476 will be th e same . With equal base voltages, each transistor will con d uct an equal amou nt of cur rent .

Wh en the Comparator output becomes un b alanced , due to an input trigger signal, uneq ual b iasing of Q474 an d Q476 occurs . In response to α ch anging b ias con d ition, t h e collector cu rrents vary p roportio nally .

Theory of Operation-2213 Se rvice The collector current changes from Q474 are filtere d

by α network composed of C476, C477, R 477, and R 478. Th e filter network re jects TV vi deo information and

averages the TV horizontal-sync pu lses. Setting the triggerlevel th reshold at near the ce nte r of the h orizontal-syncpulse swi ng establishes the untriggered level. Wh en th e TV vertical-sync b lock occurs, the output of the filter r ises to α level th at will cause the Sc hmitt Trigger ci rcu it to switch. P recise TV field sy nchronization is obtained as α result of the filtering action . Th e output signal from the filter is app lie d to U480 B pi n 6. The Sch mitt Trigger circu it respond s only to the TV sync signal because p in 7 is h eld LO by the output of U 480C . Schmitt Trigger Circuit

W ith α LO on U480B p in 7, the output at pin 3 goes LO as soon as the signal on U 480B p in 6 reac hes th e switch ing th reshol d. The LO is applie d to U 480A p in 4 and,

together with the fixed LO on p in 5, ca uses t h e output of U 480B pin 6 via R 480 to reinforce the switchi ng action . As α resu lt, the outpu t signal at U 480A pin 2 switches r ap idly . Wh en the level from t he filter networ k falls to the L O threshol d level, the feedbac k s up plied by R480 h ol d s the Sc hmitt Trigger switched ΗΙ fo r α s hort time . The amou nt of time involved prevents noise occu rring exactly at th e threshol d level from causing false trigge ring. Wh en eithe r A UTO or N OR M triggeri ng is selected, input p in 6 of U 480B is hel d LO, and the Co mp arator outpu t signal on U 480B pin 7 su p plies the in put to the Sc hmitt Trigger circ uit . The output of th e Sc hmitt Trigger ci rcuit is obtai ned from U 480D pins 9 and 15 . The d ifferential output signal derived from U 480D is ap plied to α two-transistor levelshifting circ uit composed of Q492 an d Q493 . Th e levels h ifting circuit converts t he E CL logic levels to TT L logic levels required for t he Swee p Ge nerator . Α signal obtai ned from the collector of Q493 is used to d rive the Auto B aseline circuit . Auto

Baseline

Circuit

T he Auto Baseline circuit (com posed of U 640A, Q605, an d associated components) is e nabled in bot h AUTO and TV F I EL D triggering modes. Th is circuit p rovides α signal to the Sweep Generator circuit (Diagram 5) that i nitiates α swee p if α t riggeri ng signal is not received by the Sch mitt Trigger circuit with in α perio d of about 100 ms . Α seco n d out p ut from the ci rcuit illumi n ates the TR IG'D LE D on th e instrument front p anel when t he swee p is triggere d.

Wh en ade q uate trigge ring signals are being received, th e output of Q493 is applied to pin 5 of mon osta ble multivi br ator U 640A. The n egative-goi ng edge of the signal causes p in 6 of U640A to switch ΗΙ . The ΗΙ forward biases C R 615, an d Q605 is then biase d i nto conduction. With Q605 con d ucti ng, the Auto Baseli ne signal li ne is hel d LO to p revent the Sweep Generator circuit from free running. The amou nt of time that p i n 6 of U 640A stays ΗΙ without receivi ng an in put signal is d ete r mi ned by timing components R 614 and C614 . If α trigger signal is not received in about 100 ms, p i n 6 of U 640A will go L O an d Q605 will be b iase d off. T h e Auto B aseline signal line then goes ΗΙ throug h pull-up resisto r R610, an d the Sweep Gene rator free runs to p ro du ce the baseline trace. In N O RM t riggering mo de, the Auto Disable signal (+8 .6 V) is a p plied to the b ase circ uit of Q605 via CR611 an d R 611 . The signal h ol ds Q605 fo rward biase d and p revents the Sweep Ge nerator from free ru nning. The ot her fu nctio n of th e Auto B aseline circuit is to illumi nate the TR IG'D LE D when th e swee p is p roperly triggere d. As long as U 640A pi n 6 remains ΗΙ (t rigge ring sig n als occur ring with the p rope r ti me), TR IG'D LE D DS618 will be illuminate d. The trigger mode in u se d oes not affect the operatio n of the TR IG'D LE D.

S WEEP G ENER ATO R A N D

L OGIC

Th e Sweep Gene rator an d Logic circuitry, shown on Diag r a m 5, p roduces α sawtooth voltage th at is am p lified by the Horizontal Am plifier to p rovi d e h o rizontal deflection on the crt. Th is sawtooth voltage (sweep ) is p ro d uced on comma n d from the Swee p L ogic circuits . Th e Swee p Ge nerator ci rcuits also produce gate wavefo rms th at are used by the Auto Intensity an d Ζ-Axis circuits to esta blish t he co rrect timing of the crt u nb la nk ing and i nte nsity levels u sed for viewing the d isplay. See F ig u re 3-5 for th e Swee p timi ng diagram . Th e Swee p Logic circuitry controls the h oldoff time, starts t h e swee p upon reception of α trigger signal, an d te rmi nates the swee p at th e p roper swee p level . Wh e n usi ng AUTO or TV FI EL D triggeri ng, the Sweep L ogic circuitry will ca use the Swee p Generator to free ru n, p ro d ucing α baseline trace if α trigger signal is not received with in the p re d etermined time period.

M iller Sweep Generator

The M iller Sweep ci rcuit is composed of Q630A, Q630 B, 0631, an d associated timing components . The circu it operates to h ol d t he ch arging current to the timing

3- 1 5

Th eory of O p eratio n -2213 Se r vice ca p acitor at α constant value . Wh e n α cap acitor is c h arged i n th is ma n ner, t h e rise of voltage across th e capacitor is linea r rat h er t h an exponential .

F ield-effect transistors Q630A a nd Q630 B are matc h ed d evices . As suc h , t h e IDSS ( d rai n cu rre nt wit h gate-to-

sou rce sh orte d ) c h aracteristics of eac h are nearly i d entical . FE T Q630 B acts as α source-current su pp ly for Q630A an d h ol d s th e gate-to-so urce voltage of Q630 B at zero volts .

TR IGG ER POI N TS

Α TR IGG ER U 603, PI N S 4 & 11 SWP GATE U 620, PIN 6

Before α swee p starts, pin 6 of U 620 (th e Sweep L ogic Gate) is ΗΙ , an d bot h d isco n nect d iod es (C R 626 an d CR 630) are forward b iased . Th e c h arge on th e selected timing ca p acitor will be zero volts. Wh en U 620 p i n 6 goes LO, th e d isconnect d iod es become reverse b iase d a n d th e timing ca p acitor begins c h arging t h rough th e timi n g resistor to sta r t th e sweep . Th e ove r all gai n of th e amplifie r com p ose d of sourcefollowe r Q630A an d common-emitter am p lifier Q631 is very h ig h . As th e timi n g capacito r c h arges, Q631 su p p lies feed b ac k to th e gate of Q630A to h ol d t h e gate voltage nearly constant . Voltage across th e timi n g resistor is therefore constant, and t h e c h arging current to t h e timi n g capacitor is co n sta n t . Th e resulti n g voltage waveform p r o d uce d at th e collector of Q631 is α linear ram p. Wh en t h e swee p wavefo r m am p litu d e reac h es a bout +13 V, th e End -of-Sweep Com parator (0640) is biased on an d th e Sweep Logic circuit resets. P in 6 of U 620 goes ΗΙ to forward bias d isconnect d iod e C R 626, a n d th e current t h rou g h th e timing ca p acitor reve r ses d irection . Th e swee p out p u t waveform d ro p s rap i d ly until d isconnect d iode C R 630 also becomes forwar d b iased . At th is p oi n t, t h e Swee p Generato r is rea d y to start another sweep .

CO LLE CTO R EN D O F

SWEEP Q640 CO LLE CTO R

STA R T O F H O L DO FFN

j EN D O F HO LDO FF

U 6408, PIN 9

L ogic

F ollowing

t h e sweep com p letion, α fi n ite ti m e is re q u ired to d isch a rge t h e timi n g ca p acito r . Th e Swee p Logic ci rcuit is prevente d from resp ond ing to α trigger signal d u ring t h is time by t h e H ol d off circu it. Th e end of sweep (and start of t h e h oldoff p eriod) is d etermine d by t h e En d -of-Swee p Com p a rator (Q640) .

H O L DO FF TI M I N G U 640 B, PIN 14

H O LDO FF U 603,

PINS 1&13

U

Th e Sweep ram p waveform is applied to t h e b ase of Q640 thr ough both α voltage d ivi d er an d α b iasing networ k com pose d of R637, R638, a nd C637 . Wh en t h e ram p amplitu d e reach es t h e th resh ol d level of Q640, t h e collecto r of Q640 goes LO, an d α L O is placed on both U 640 B pin 11 an d U 607C pin 10 . Th e o u tput of U607C goes ΗΙ , and th e positive feedback supplie d to th e base of Q640 t h roug h R 639 speed s up the c h ange of state of Q640 . By reinforci ng th e switch ing actio n of Q640 i n t h is ma nner, noise occurring at th e thres h old level of Q640 is over r id d en .

SWP GATE U 603, PIN 9

SWP DUTY U620, PIN 8

A LT SYN C C R 644, A N OD E

D LY EN D U 620

PI N S

Swee p

Th e sweep h ol d off period co m mences w h en the L O from Q640 is applied to pin 11 of monostable multivibrato r

LO F O R D

U 640 B . Th e Q out p ut on pi n 9 goes LO a n d remains L O for α le n gt h of time determi n ed b y th e RC timing com ponents con n ected between p ins 14 an d 15 of U 640 B .

3 & 13 3827-15

Figure 3-5. Sweep ti m i n g diag ram . .

3-16

H ol d off time can be va r ie d from t h e normal perio d by usi n g V A R H O L DO FF control R557 . P ote n tiometer R557

Theory of Operation-2213 Service and α voltage d ivider com p ose d of R645 and R 646 establish the charging voltage of hol d off timing ca p acitors C645, C646, an d C647 . The capacitor (or combination of capacitors) used is switche d into the hol d off circuit by contacts on S630B, the SEC/DIV timing switch . During h ol d off time, while U 640B p in 9 remains L O, the output of U 607C will b e ΗΙ . Inverter U 607B will invert the ΗΙ to α LO logic level that is then applied to the R eset inputs of both U603A an d U 603B at p ins 1 an d 13 respectively . The LO at these inputs hol d s both flip-flops in t he reset state, with t he Q out p uts ΗΙ and Q outputs L O. In the reset state, flip-flops U 603A and U603B will not res p ond to input trigger signals. The Set input of U 603B is hel d ΗΙ by the output of U 607A an d d oes n ot affect flipflop operation. (With A UTO trigger mode selected, α different condition at the Set input of U 603B occurs when triggering signals are not received ; see "Auto Baseline Sweep."). As long as the R eset input of U 603B is h eld LO, the Q output at U 603B pin 9 stays LO. The LO is app lied to one of the inputs of all four AND-gates contained i n Sweep Logic Gate U 620, and output pins 6 and 8 of U620 will be held ΗΙ . As p reviously describe d , α ΗΙ on U 620 pin 6 resets the M iller Sweep Generator. When the timing capacitor is charged up to the reset threshold of U640B, the h ol d off time elapses, an d U 640B switches b ack to the stable state to p lace α ΗΙ on the Q output (pin 9) . The End-of-Swee p Comparator output on U 607C p reviously b ecame ΗΙ when the M iller Sweep Generator finished resetting. W ith both i n p uts of U 607C now ΗΙ , the output on p in 8 is LO. This LO is inverted to α ΗΙ by U607B an d ap p lied to both U603A and U603 B to remove the reset condition . The Q output of U603B at p in 9 will remain LO when the reset is removed, while the Q output on U 603A ( p in 5) will d epen d on the state of the Set input when the reset is removed. If the Set input to U603A is ΗΙ when the reset is removed , the Q out p ut will be L O. H owever, if the Set input is LO, the Q output on U 603A will b e ΗΙ prior to the reset removal, an d it will remain ΗΙ after the reset is r emoved . If the Set in p ut of U 603A was ΗΙ when the reset was removed, the triggering signal will make α negative transistion to set U 603A b efore U 603B is clocke d , since U 603B clocks only on positive transitions . In either case (with t he Set input either ΗΙ or LO when the h oldoff p erio d en d s), the Q output of U 603A will be ΗΙ as U603B is clocked by the first positive transition of the trigger signal after holdoff ends . The ΗΙ output present on the D input of U 603B (pin 12) is then transferre d to the Q output (pin 9), where it is ap p lied to one input of each

A ND-gate containe d i n Sweep Logic Gate U 620. Gating of the Swp Gate signal through U620 is controlled by the H ORIZONTAL MODE switch and the Delay circuit. A UTO BASELINE SW EEP. This feature causes an automatic sweep to be generated after about 100 ms if no trigger signals are received. Generation of the Auto B aseline signal was d iscussed p reviously in t his section. The Auto B aseline signal is L O either when trigger signals are being received or when t he circuit is d isabled by u sing N ORM triggering . The Auto Baseline signal is ap p lied to pin 1 of N ANDgate U 607A, while the H ol doff Gate signal is applied to U 607A pin 2. As long as the Auto Baseline signal remains L O, the output of U607A on pin 3 will be ΗΙ an d will not affect the Set input of U 603B . When the Auto Baseline signal goes Η Ι in the absence of triggers (using either AUTO or TV FIELD triggering), the output of U607A is an inverte d H oldoff Gate signal . During hol d off, the output of the H oldoff Gate is α LO and places α r eset on both U603A and U603B. The reset causes the Q out p ut of U 603B to b e L O. At the end of the h oldoff p eriod, p in 2 of U 607A goes ΗΙ , and the reset is removed from U 603A an d U603B . W ith both pins 1 an d 2 of U 607A ΗΙ , the output on p in 3 goes L O, an d U 603B becomes set. Pin 9 of U 603B becomes ΗΙ , and if no delay is used U620 pin 6 goes LO to initiate the Sweep. If the instrument is set for α delay, U 620 p in 6 will go LO to start the sweep at the end of the delay time . As long as no trigger signal is received, U 603B will continue to free run in the manner just d escribed to p roduce α Swp Gate signal to U 620 at the end of each holdoff p eriod .

Χ-Υ DISPLAY. Switching the SEC/DIV switch to the Χ-Υ p osition applies α LO logic level to U 640B pin 11 and U607C pin 10 via CR640 an d to U 607A p in 1 via CR610. The LO applie d to U 640B pin 11 prevents the H oldoff monostable multivibrator from being triggere d . The LO ap p lied to U 607C pin 10 an d to U 607A pin 1 ensures that both U603A and U603B are h eld i n t he reset cond ition and d o n ot respon d to input trigger signals.

A LT SYNC PULSE. Α s haping network connected to

U 640B pin 9 converts the lead ing edge of the negative-going h oldoff transitions into α narrow pulse suitable for use as α synchronization signal . Zener diode VR644 h ol d s the voltage at one end of C644 at about 3 V, while the Q out p ut of U 640B at pin 9 is ΗΙ . When the Q output of U 640B goes L O at the start of the h ol d off perio d , C644 couples the n egative-going e d ge of the pulse to the Alt Sync signal line .

3- 1 7

Theory of Operation-2213 Se rvice Ca p acitor C644 c harges ra pidly to the new voltage d ifference throug h R642 to p ro d uce α very narrow pulse o utp ut across R642 . Wh en t he h ol doff pe rio d e n ds, the Q ou tput of U 640B goes ΗΙ again a n d C644 c h arges i n th e op posite direction t hr o ugh VR 644 . The resulting Alt Sy n c signal is applied to the C h an nel Switching circuit to sy nch ro nize the horizontal d is p lay with c hannel switching transitions when using AL T VERTICA L MOD E . Delay Circuit

The Delay ci rcuit, composed of Q624, Q632, Q644, Q650, Q652, U 607D, and associated components, ge nerates the timing and gate sign als required to p roduce th e inte nsifie d Swee p display and to provi d e the va ria b le Sweep d elay . H OR IZONTA L MOD E switch 5650 controls the display mo de (ΝΟ IDLY, I NTEN S, or D LY'D), and DEL AY TIME switch S660 selects the b asic d elay time (0 .2 ms, 10 μs, or 0.5 μs) . The D EL AY TIME MULTI PL I ER co ntrol ( R658) increases the possible d elay available by up to at least twenty times t he basic d elay . ΝΟ D LY. W it h HO R IZONTA L MOD E switch S650 set to the ΝΟ DLY p osition, the Delay circ uit is d isabled and the Sweep starts immediately after the Swp Gate sign al is produced by U 603B at p in 9. P in D of S650 is open, so p ins 4 a nd 10 of U 620 are pu lled ΗΙ t hrou g h R608. Wh en the

Sw p Gate occurs, p ins 1, 2, 5, an d 9 of U 620 all go ΗΙ . T he ΗΙ on pin 5 is AN Ded with the ΗΙ on pin 4, an d U620 pi n 6 goes L O to initiate α Sweep. Th e output of the Delay circuit is d isable d by groun ding the base of Q644 throug h p in Α of S650 . T h is action h ol d s t he Dly Gate sign al at the collector of Q652 at α ΗΙ logic level. W it h t h e Dly Gate signal ΗΙ , α ΗΙ is also gated thr o ugh U620 to p in 8 to b ias off CR620. Diode C R622 is then forward b iased to enable t he Intens L evel current from R 622 to the Ζ -D rive line to unbla nk the crt for t he Swee p display . I NTENS. W it h 5650 set to the I NTEN S p osition, the Delay circ uit is enable d. Νο delay in the Swee p occurs in this mode, but an i ntensifie d zone is d isplaye d . The amoun t of d elay between t he start of the Sweep a nd th e start of the intensified zone is dete rmine d by th e DEL AY TIME switch setting an d the MULTI PL I ER co ntrol p osition .

The inte nsifie d zo ne is generated by gati ng throug h U607D to control the Ζ -Axis gating diodes, CR619 and C R 621 (see F igure 3-6) . P in 12 of U 607D is p ulled ΗΙ th rough R607 as p in Η of S650 is open. When the d elay time h as ela p sed, U 607D pi n 13 is also switched ΗΙ (by the Dly Gate signal), and p in 11 goes LO. Diode C R619 becomes reverse b iase d , and C R621 p asses the I n te ns L evel curren t to the Ζ-D rive li ne. The extra current is ad d e d to

SWP DU TY

_ I

TO A U TO N TEN S I TY

CR 622 FR OM HOR I ZO N TAL M ODE SW I TC H PIN D

H OR I ZO N TA L M ODE SW I TC H PIN Η

3827-16

Figure 3-6. Sim plified diagram of th e Ζ-Axis Switching L ogic circu it .

3-18

Theory of Operation-2213 Se rvice

the Sw p Ζ-Axis current al ready pr esent from CR622 to

intensify the display. The non-intensified portion of t he trace ind icates the amount of total d elay time .

A UTO I NTEN SITY AN D Z-AXIS AMPLI FI ER Auto Intensity

D L Y'D . In th is position of H O RIZONTA L MOD E switc h S650, t h e start of t h e sweep is d elayed b y th e amount of time establis he d by the Delay circ uit . Wh en α trigger signal cloc ks U 603B to p roduce α ΗΙ Sw p Gate signal on U 603B pin 9, the d elay time is started. The ΗΙ is a p plied to the base of Q624 via R613 to b ias that transistor off. Transistor Q624 is u se d as α switch across the delay timing capacitors . Wh en b iased on, the transistor keeps the timing ca p acitors d ischarged. Wh en the transistor is biased off, the delay timing ca pacitors are allowed to ch arge . B ot h t he amount of capacita nce and the chargi ng voltage are controlled by DEL AY TIME switch S660 . The DEL AY TIME switch also controls the voltage ra nge a p plied to MULTIPL IER potentiomter R 658.

F or the longest delay-time range (0 .2 ms), S660 switches C622 in parallel with C624 . Wh en switched to the 10-μs d elay position, C622 is out of the delay timing circ uit . F inally, in the 0.5-μs p osition, add itional chargi ng cu rre nt is supplied to C664 via R 692 to increase th e charging rate, an d +8.6 V is applied to th e MULTI PL I ER potentiometer via R 600. Th e increase d voltage ch anges th e control range availa ble at th e wiper of R 658. At t h e start of the d elay time, U603B pin 8 goes L 0. This removes th e p ositive bias from Q632, a nd t he emitter voltage of 0632 becomes near grou nd potential . As th e d elay timing ca pacitor charges, the base of 0632 remains at α constant voltage, therefore the base of Q652 goes negative . Wh en the base of comparator transistor Q652 reac hes α mo re negative level th an th e base of comparator t ransistor Q644 (set by the MUL TI PL I ER co ntrol), Q652 starts to switch off an d Q644 star ts to switch on . The collector voltage drop of Q644 is coupled back to the emitter of Q632 via R 641 to complete the switching action . The collector voltage of Q652 rises to α ΗΙ logic level whic h is applie d to Swee p Logic Gate U 620 on p ins 3 and 13. The ΗΙ is A NDe d with the ΗΙ Swp Gate signal alrea d y p resent to pr o d uce α L O out p ut at U 620 pin 6 an d pin 8. T he L O at pi n 6 in itiates α Swee p, and the L O at p in 8 unblan k s the crt. In th e D LY'D M ode, p in 12 of U 607D is LO, so pin 11 will be ΗΙ to bias C R619 on an d C R621 off ( F ig u re 3-6) . T h is actio n prevents i n tensifying current from reac hi ng the Ζ -Drive line d u ring the DLY'D Swee p dis p lay. Duri ng Swee p retrace time, C R 621 is b iased off by th e ΗΙ applied to CR668 from U 603B p in 8 to keep the crt bla nk ed off.

The pu rpose of the Auto I ntensity ci rcuit, show n in Diagram 6, is to keep the intensity of the trace on the crt at α consta nt level wit h c h angi ng sweep s p eeds and trigger sig n al repetition rates. In conventional oscilloscopes, as the d uty cycle of the d isplayed trace changes, the inte nsity will vary . The Auto Intensity circ uit compensates fo r t his effect by increasing the Ζ-Axis Drive voltage for low Sweep du ty factors. Th e elements of the Auto Inte nsity circ uit consist of fou r blocks : the d uty-cycle averager, the boostfactor converter, th e inte nsity-control mu ltiplier, and the crt triode compensation circ uit . T he d u ty-cycle ave r ager consists of an electronic switching circuit compose d of U 825A, U 825B, an d U 825C . The Swp Duty signal th at is a pp lie d to U 825B p in 11 causes th e outpu t voltage at p in 14 to b e switched between grou nd an d +5 V. The output voltage of U 825B is averaged by R 821 and C821 and app lied to U 835A pi n 3 via U 825C . As the swee p d uty factor d ec reases, the crt beam current must b e increase d to maintain α constant inte nsity . To accomplish the task, the b oost-factor converter increases the d rive in inverse p ro portion to the duty factor of the trace being d isplaye d . Amplifier U 835A is α high-imped ance voltage follower. F or 100%ο duty factor, the output voltage will be app roximately zero . Decreasing the d uty factor to 10ο/ο resu lts in

app roximately 4.5 V output, and when no swee p occurs (Οο/ο d uty factor) the output will be 5 V. The output of U 835A is a p plied to α netw or k consisting of CR 828, C R 830, an d resistors R 827, R 828, R 829, R 830, an d R 831 . T h is network pro duces an ou tpu t current wh ic h is α nonlinear fu nction of the d uty-factor voltage . F or 10ο%ο d uty facto r, the outpu t current is 10 times greater th an th e current at 100% d uty factor . M aximum available boost limits at α factor of about 25 :1 .

The nonlinear cu rrent is co nn ecte d to t h e emitters of the d ifferential am p lifier comp osed of Q811 an d Q812 . Th e emitte rs of the two amplifier t ransistors are h eld at α constant voltage by the action of Q813 . AUTO INTENSITY control R807 is connected to the base of Q811 via R 811 . It controls the portion of the boost cu rr ent that goes to the summing j unction of U 835B. Boost cu rrent is prop ortional to the true beam current requi red at the face p late of the crt. The c rt triode compensation circu it is an inverti ng o p erational amplifier with nonlinear feedback. It is com p osed of U 835B, R 834, R 835, C834, an d C R834. Output voltage of the circuit changes i n res ponse to th e

3- 19

Theo ry of Operation-2213 Service in put current in α manner t hat comp lements the nonlinear trio d e ch aracte ristics of the crt. Th is output voltage is applie d to the Ζ-Axis Am plifier via the Ζ-Axis Gati ng ci rcuit . The Intens Level signal is also applie d to th e F oc us circuit (Diagram 9) for use i n focus track ing of the inte nsity level changes. The intensity of the d isplay is allowed to re duce to zero th ro ugh t h e action of CR809, VR 809, and R 809. W ith out this circ uit, the Auto Intensity circuit woul d not allow the intensity to go to zero when the AUTO I NTEN SITY co ntrol is set to mi n im u m i ntensity. Ζ-Axis Am p lifier The Ζ-Axis Am plifier controls the crt intensity level via several in p ut-signal sources. The effect of these in put signals is either to increase or d ecrease trace intensity or to completely blan k portions of the dis p lay. Th e Ζ-Drive signal current an d the input current from the Z-AXIS I NPUT connector (if in u se) are summed at the emitter of common-base am p lifier transistor Q841 . Th e algebraic sum of these signals determines th e collector current of Q841 . In pu t transistor Q841 p rovides α low-impedance termination fo r t h e in put signals an d isolates the signal sources from followi ng stages of the Ζ-Axis Am p lifie r. Signal current from Q841 flows th roug h C R844 an d develops α signal voltage dro p across R 844. Increasing current th rough Q841 re d uces the forwar d bias of Q844, thereby reduci ng the current thr ough Q844 . Th is action causes the collector voltage of Q844 to go more n egative (toward t he -8 .6 V su p ply) an d increases the forward b ias on emitter-follower Q845 . As emitte r current of Q845 increases, negative-going voltage develo p e d across R847 is applied to the bases of complementary- pair outpu t transistors Q847 and Q850 . Positive transistions of the Ζ-Axis signal are couple d to the b ase of Q850 via C852 . The fastrise transitions are am plified by Q850 to spee d up the resp onse time . F or negative transitions of the Ζ-Axis signal, as well as for do an d low-frequency signal components, Q847 acts as th e amplifier, with Q850 su p p lying t he cu rrent. Diod e CR856 p revents the Ζ-Axis output signal from going negative, an d neon lamps DS854 an d DS856 p rovide protection to the Ζ-Axis Am p lifier in the event of highvoltage arcing in the crt. T h e am p lifier gain with respect to t h e Ζ -Drive current is set to about 10 by th e negative feed bac k supp lied from th e collectors of Q847 and Q850 to the b ase of Q845 via fee d bac k resistor R 846. The gain with res pect to the external Ζ-Axis Input signal is h eld to about three by R 801, R 802, and R 803 in se ries with t h e exte rnal input signal . Diodes CR801 an d C R802 p rovi de protection for the

3-20

Ζ-Axis Amplifier in case of an acci dental a pp lication of excessive signal amplitude to the Z-AXIS I NPUT connector. Wh en C HO P VERTICA L MOD E is selecte d , t he Ch op B la nk signal is applied to the collector of 0841 d uring th e d isplay switch ing time . Signal current is shunted away from

CR844, and the forward bias of Q844 increases to the b lanking level. Wh en blanked, the out p ut of the Ζ-Axis Amplifier dro p s to about +10 V, an d t he crt b eam current is r educe d to below viewing intensity to eliminate ch o p switching transients from the disp lay.

F or an Χ-Υ d isplay, the Swee p Ζ-D rive signal cu rrent is switched off. Wh en t he ΧΥ signal is L O, C R837 is forward b iased an d Intens L evel current flows th roug h R 837 to Ζ-Axis Amplifier transistor Q841 to establis h t h e d isp lay intensity. The last input to the Ζ-Axis Am p lifier is the Beam F ind current. N ormally, BEAM F I N D switch S390 is closed , an d -8 .6 V is supplied to the base bias networ k of Q841 an d Q844. Wh en the BEAM F I ND switch is ope ned, the -8 .6 V is remove d , an d t he bias voltage becomes more p ositive. Transistor Q841 becomes mo re forward b iased wh ile Q844 becomes much less forwar d b iase d . The current th rough Q844 is re duced, an d t he base b ias voltage of Q845 is thereby increased. The output of Q845 th en goes to α level that p ro d uces α fixe d, pre determi ne d Ζ-Axis output signal level . Thus neither the AUTO INTEN SITY control nor the Ζ-Drive signal have any control over th e intensity level of the crt display whenever the BEAM F I N D push button is p resse d in, a n d α b rig ht trace (or d ot if no swee p is presen t) will be d is played .

H O R IZO NTAL The H orizontal Amplifier ci rcuit, show n on Diagram 7, provides the output signals th at drive the h orizontal crt deflection p lates. Signals a p plied to the H orizontal P reamplifier can come from either the M iller Swee p Ge nerato r (for sweep d eflection) or from th e ΧΥ Amplifier (w hen Χ-Υ d isp lay mode is selecte d ) . See F ig ure 3-7 for α detailed block diagram of the H orizontal Amplifier circu it . The H orizontal P OSITIO N control, Χ10 magnifier circuitry, and the h orizontal portion of the beam finder circuitry are also containe d i n t he H orizontal Amplifier circuit.

H orizontal P ream p lifier

Th e sum of the sweep an d positioning current is applie d to the in p ut of one side of α differen tial am p lifier composed of Q730 an d Q731 . F or all conditions oth er th an

Theory of Operation-2213 Service

the Χ-Υ M o d e, ΧΥ Switch transistor Q720 is b iased on to provi de α ground reference at the other in p ut of the d if-

ferential am p lifier (at the base of Q731). The output of the d ifferential amplifier, taken from the collector of Q731, is amplifie d by Q736 . Α feedback network connected b etween the out put of Q736 an d t he b ase of Q730 provides the circuitry required for the Χ 10 magnification feature. In the unmagnifie d mode, Χ10 M agnifier switch S734 is closed and the feedback is provi de d by the paralleled combination of R732 an d C732 . R esistor R 732 sets the unmagnifie d amplifier gain an d C732 p rovides the HF compensation . When the Χ10 M agnifier push button is pressed in, S734 opens an d additional components are added to the feedback network . W ith t he fee d back re d uced, the am p lifier gain is increased by α factor of 10. The Χ 10 Gain

p otentiometer (R733) is a d justed to produce the exact gain require d . H igh-spee d linearity compensation of the feedback network is provi d ed by a d justable capacitor C734 . ΧΥ Am p lifier

When the Χ-Υ display mode is selecte d using the SEC/ DIV switch, the ΧΥ signal line goes LO and ΧΥ Switch transistor Q720 is biase d off. The ΧΥ signal is also ap p lied to FET Q714 (used as α switch to p revent crosstalk) in the ΧΥ Amplifier to bias it on. W ith this action, the ΧΥ Amplifier is enable d to p ass Χ-Axis signals on to the H orizontal P reamplifier. Another function of the ΧΥ signal is to d isable the Sweep Generator to p revent the Sweep signal from being applied to the H orizontal P reamplifier. The Χ-Axis signal is d erived from the Channel 1 internal trigger signal and applied to the base of Q703. Transistor

M AGNIF I ER

HORIZONTAL

P OS I T ION R 726

FROM S WEEP G ENER ATOR

FR O M Λ

S IV I INT ERNA L

E C/D SW TC H

FR O M TRIGG ER ΑΜΡL

ΗΟR ΙΣ

Ρ R ΕΛΜΡ

TO C R T HORIZONTAL DEFLE CT ON PL AT ES

Q730 Q731

I

Q736

Χ X-AXIS SIG

FR O M Z-AXIS AMPL

BEAM

FIND 3827-17

Figure 3-7 .

Detailed bloc k d iag r am of the

Ho rizo n tal Amplifie r .

3-21

Theory of Operatio n-2213 Service Q703 is one- half of α differential amplifier composed of Q703 an d Q706 . The base of 0706 is referenced to ground through R706. Transistor Q708 am plifies the output signal from the collector of Q706 and applies it to the drai n of FET 0714 . Α feedb ack networ k composed of R709, R708, and C708 is connected between the collector of Q708 and the b ase of Q703 . The feed back netwo rk sets the overall gain of the Χ Υ Amplifier, with Χ-Gain potentiometer R709 adjusta ble to obtain th e exact gain required. The Χ-Axis signal p asses t h rough FE T Q714 an d is applie d to the base of Q731 in the H orizontal Pream plifier . H orizontal position ing cu rrent on the base of 0730 is added to the Χ-Axis signal by the action of the d ifferential amplifier. Then the sum of these two currents is amplifie d by Q736 an d applied to the in pu t of the H orizontal Output Amplifier.

H orizontal

Outp ut Am p lifier

Th e H orizontal Output Am plifier converts the singleen d ed output of the P reamplifier into the d ifferential output re q uire d to drive the crt h orizontal deflection prates . Th e output stage consists of an input paraphase amplifier an d an outp ut com p lementary amplifier .

Horizon tal signal voltage from Q736 is ap plied to the

base of Q763 . The base of the ot her transistor (Q753) in the paraph ase am plifier, is biase d t hroug h α voltage divi d er com posed of R 758, R757, an d R 756 . H orizontal centeri ng between the Χ1 and Χ 10 M agnified swee ps is accomplish ed by ad justing M ag R egistration potentiometer R758 . Gain of the p arap hase amplifier is determined by components co nnected between th e emitter leads of Q763 and Q753. The exact gain is a d juste d by H oriz Gain potentiometer R752. Transistor Q747 supp lies the emitter current to both Q763 an d Q753 . T he horizo ntal p ortion of the Beam F in d circuitry affects the available current to Q747 . N ormally, -8 .6 V is app lie d to t h e emitter of Q747 from the BEAM F I N D switch via CR745 and R746 . Wh en the BEAM F I N D push button is p ressed in, the direct -8.6 V is remove d . In th is con d ition, -8.6 V is supplie d via R 745 wh ic h re duces the current available, t hereby re d ucing the output voltage swing cap ability of 0763 and Q753 . Diod es CR772, CR 782, CR783, an d C R 773 prevent the paraph ase am p lifier from over d riving the output amplifie r stage when the Χ10 Mag n ificatio n feat ure is in use.

F inal am plification of th e h orizontal d eflectio n signal is p rovi d e d by the comp lementary- pair out put stage. B ot h sides of the differential output amplifier are identical in function, so only one si d e is d iscusse d in d etail.

3- 22

Transistors Q780 and Q785 form α cascode feedbac k amplifier . Gain of the stage is set by feed bac k resistor R 785, an d hig h-s peed compensation is p rovi d ed by C783 and adju stable capacitor C784 . F or d o a nd low-frequency components of the horizontal deflectio n signal, Q789 acts as α current source for 0785 . H igh-frequency comp onents of t he signal are coup led th rough C789 to th e emitter of 0789 to speed up the out p ut response time .

E mitter voltage for b oth Q780 and Q770 is supp lie d by α circuit com p ose d of Q765 and associate d com ponents . The emitter voltage is maintained at α level that p rovides p roper biasing for Q763 an d Q753 . Diodes C R 770 and C R780 set up an emitter- bias d ifference between Q780 an d Q770, causing the b ase voltage of bot h transistors to be e q ual.

POWER

S UPPLY

The Power Supply circ uitry converts the ac-source voltage into the various voltages needed for inst ru ment operation. It consists of the P ower I nput, Preregulator, an d Inverter ci rcuits (which drive th e p rimary of the power transforme r) an d other Seco nd ary circuits (which produ ce the necessary supp ly voltages fo r t he inst ru ment) . This instrument h as either the Current Limit boar d (Α19) or the Preregulator boa rd (Α18) installed as part of the power supp ly . Refer to the appropriate circuit d escription for your p articula r instrument config uration . ΝΟΤΕ In struments with α SN Β020100 or above contain the

Preregulator board. Some instruments below this serial number were built con taining the Preregulator board. To determine if yours is one of these, look to see if there is an Option 48 sticker attached to the rear of the instrument. If there is not an Option 48 sticker attached and the serial number is below Β020100, your instrument contains the Current Limit board.

C urrent Limit Boa rd

Co nfiguration

The P ower switc h (S901) connects the line voltage to the inst rument throug h li n e fuse F 901 and transient su ppressor VR 901 . Su ppresso r VR 901 protects the instrument from large voltage transients . H ig h-frequency line noise is attenuated by C901 . The P reregulator circ uit converts the ac-power-sou rce input voltage to α regulated do voltage. Α triac is used as α switch to cond uct curre nt duri ng α controlled period of the input-line-voltage cycle so that en ergy to be used by the Inverter circuit is stored in ca pacitor C937 .

REV NOV 1982

Theo ry of Operation-2213 Service Current from one si de of the ac-power-source in put will go th ro ugh L925 (α current-limiti ng im pedance) and triac 0925 . Diodes CR931 and C R933 (on the M ai n board) and CR932 and CR934 (on the Current Limit boa rd) form α fullwave bridge rectifier circuit. The rectifie r co nverts the acinput voltage into do pulses that charge C937 . Su rge a rrestor VR938, co nn ected in parallel with C937, co nducts to p rotect the following circuitry should the Prereg ulato r output voltage b ecome too h igh. The two-transistor circuit composed of 0933, 0938, and associated components provides over-current protection in t he event of triac misfiring or ac-power-source transients . Transistor Q938 is an insulatd-gate FE T u sed as α switch in t h e charging p at h of C937 . Transistor Q933 controls the FE T b ias to limit the current under abnormal firi ng conditions of Q925 . In n ormal power-supply operation, the voltage d eveloped across R937 is not s ufficie nt to bias 0933 into conduction . The gate-to-source voltage of Q938 is set to 10 V by VR 934 and R 938, so the FET presents α low resistance to the charging current to C937 . If triac Q925 s hould misfire to cause excessive current, 0933 becomes forward biased an d 0938 is switched off to reduce the current. When 0938 switches off, the current t hat was flowing throug h Q938 flows throug h R939. The voltage d rop developed across R939 ca uses current to flow throug h VR 933 and R 933, which holds Q933 on for most of the remainder of the ac-power-source inpu t cycle. Resistor R939 limits the rate of collapse of th e field around L925 to prevent damage to Q938 . Thermistor RT935 adjusts the bias of Q933 over varying am bie nt temperat ures . PREREGUL ATOR CONTROL. T he ac-source voltage is full-wave rectified by CR903 t h roug h C R906 and app lied to α voltage d ivider composed of R911, R912, and R915. Output from this divider serves as α reference voltage for α ramp-and-pedestal compa rator utilizi ng α prog rammable unijunctio n transistor (PUT), Q921 . Capacitor C912 filte r s the line noise to prevent false triggeri ng of the PU T. Voltage-dropping resistor R 914 provides current for zener diodes VR 914 an d VR 915 to p roduce co nstant voltages d uring each half of the ac-power-source cycle. Wh en th e instrument is first turned on, C917 is not charged. Capacitor C915 charges through CR917 to th e voltage of VR 915 mi nus the diode drop of CR917. Wh e n t he anode voltage of 0921 is greater than t he gate voltage, 0921 will fire and C915 will d ischarge through the primary of Τ925. T h is event will h appen after t he pea k of the voltage waveform . P ulse transformer Τ925 is connected to t he gate of Q925, and the discharge of C915 throug h th e Τ925 p rimary winding is coupled to the secondary to cause triac Q925 to condu ct. After firing, the triac will turn off agai n w hen t he si nusoidal source voltage crosses throug h zero . As C917 charges through 8917, Q918 current increases proportionally to charge C915 more rapidly. Wh en C915 charges at α faster rate, the anode voltage of 0921 rises above the gate voltage ea rlier in the ac-source cycle and thereby ca uses Q925 to conduct fo r α lo nger period of time .

REV NOV 1982

T he portion of the cycle preceding the zero-crossing point

over whic h the triac is conducting is called the condu ctio n angle. The conductio n angle will increase from n early zero (at turn on) to an angle sufficient to supply the energy needed by the inverter. F eedbac k from th e inverter thro ugh o ptical isolator U931 h olds the correct cond uction angle by shu nting cu rrent from R 917. This shu nting action controls t he voltage on C917, thereby controlling the increase in base voltage on 0918 . This action controls the chargi ng rate of C915 a nd therefore the conduction angle of 0925 . The Preregulator circuit can h andle α wide range of inp u t voltages by changing the conductio n angle of the triac as t he in p ut voltage changes. As the input voltage increases, t he con d uctio n angle will d ecrease to maintain the Pre regulator outpu t voltage at α constant level. The voltage d ivider com posed of R911, R912, and R915 p roduces an output voltage pr oportional to the input li ne voltage th at is a p plied to the gate of 0921 . Since VR914 and VR 915 h ol d b ias levels on Q918 consta nt regardless of input voltage, the point on the cycle at whic h 0921 fires will vary with changes in the ac-source votlage. This feed-forward, together with the feedb ack from the In verter through o ptical isolator U931, ensures α constant P reregulator output to the Inverter . Pr eregulator

B oa rd Configuratio n

The Power Input circuit converts the input ac-source voltage to filtered do for use by the Preregulator. The POWER switch (S901) conn ects the ac-supp ly source thro ugh fuse F901 to b ridge rectifier CR904. The bridge full-wave rectifies t h e so ur ce voltage, and its output is filtered by C909 . In p ut surge current at the time of instrument power-up is limited by thermistors RT901 an d RT902 . Initially their resistances are h ig h, b ut as they warm up, their resistances d ecrease an d they dissipate less power. The instrument is protecte d from large voltage transients b y su pp ressor VR 901 . Cond ucted EMI is attenuated b y li ne filter FL9001, common-mode tra nsformer Τ 901, differential-mode transforme r Τ907, and ca pacitors C901, C903, C904, and C905 . Capacitors C907, C908, and C910 form α hig h-fre quency bypass networ k to prevent the diodes in CR904 from generati ng EMI. The Preregulator provides α regulated dc-output voltage for u se by the Inverter circuitry . When t h e instrument is turned on, voltage developed across C909 will charge C913 throug h R911 . Wh e n the voltage h as risen to α level h ig h enough t hat U 920 can reliably drive Q933, U920 will receive its Vcc voltage throug h 0915 . This level is set by zener diode VR 917 in the emitter circuit of 0917 and b y the voltage divider consisti ng of R912 and R913. The ze ner diode will kee p 0917 off until the voltage at its b ase reaches approximately 6.9V. Then

3- 23

Theory of Operatio n -2213 Service Q917 will be biased into its active region and t h e resulting collector c urrent will cause α voltage drop across R916. T his voltage dro p will b ias on Q915, and t he positive feed back t h roug h R 914 will rein force t h e turn-on of Q917 . T hu s Q915 and 0917 will drive each oth er into saturation very quic k ly. Once Q915 is on, U920 will begin to fu cntion.

Pu lse-widt h modulator IC U 920 controls t he out p ut voltage of t h e Prereg u lator by reg u latin g t h e du ty cycle of t he p u lse app lied to th e gate of Q933 . It utilizes an oscillato r whose frequency is determined by R920 and C920 (a pproximately 40 kH z) and wh ose output at p in 5 is α sawtooth voltage. An internal com p arator com p ares th is sawtoot h voltage wit h th e outp ut voltage prod uced by t h e two error amplifie rs. Wh e n ever the sawtoot h voltage is greater than t he erro r -am plifier output voltage, Q933 is b iased on to supply cu rre n t to b ot h C934 and t he rest of t he circuitry . T h e two e rror am plifiers are used to mai ntai n α constant output voltage an d to mon itor t he outp ut curren t of th e Preregulato r . One input of eac h am p lifie r is connected th roug h α divider netwo rk to the i n te rn al +5 V refe re nce . T he outp ut voltage of th e Preregulator is monitored by the voltage d ivid er at p in 2. T h e voltage drop across R933, produced by the P reregulator output current, is app lied to t h e current-limit am plifier via R 929. When th e instru ment is first turned on, t he current limit am plifier co n trols the conductio n time of 0933 . While Q933 is cond ucting, th e output curre nt i n creases until α sufficiently large voltage drop is developed across R 933 to invok e t he c urre nt limit mode . Th e curren t-limit amplifier holds t he ou t put curre n t to the current-limit t h res h old at a pp roximately 1 ampere. Wh en t h e voltage across C934 reac hes app roximately 43 V , t h e voltage am plifier starts controlli n g t he d uty cycle of Q933 and th e Preregulator will not limit current unless th e r e is excessive current demand . W it h Q933 off, C933 charges to t he outp u t voltage of t h e Power I nput circuit. Wh en Q933 turns on, current throug h the FET will come from t h e win d i ng connected to pi n s 1 and 2 of Τ933 and from C933 . Cu rrent to C933 is s upp lied by th e winding con nected to pins 4 an d 5 of Τ933. When U 920 s h uts off Q933, t h e colla p sing magnetic field will raise the voltage at t he anode of CR 933 . Th is diode t hen becomes forward biased and passes current supp lied by t he winding connected to pi n s 1 and 2 of Τ933. Th is process will continue for each p e r iod of t he oscillator, an d t he duty cycle will be altered as necessa r y to maintain 43V across C934 . To s hut off Q933 du ring eac h oscillator period , Q931 is used to disch arge t he gate-drain capacitance . Pin 10 of U 920 goes LO, reverse biasing CR 931 and turning on Q931 to effectively s hort together t he gate and source, t h us sh utting off t h e FET.

Once t h e su pp ly is running, power to U 920 will be su p plied from t he win d ing co nnected to p ins 6 and 7 of Τ933. Diode CR 913 h alf-wave rectifies t he voltage across pins 6 and 7 to keep filter capacitor C913 ch a rge d and to maintain V cc voltage to U 920 through Q915 .

3-24

I nstrument protection from excessive ou tpu t voltage is supp lied by silico n -controlle d rectifier 0935 . Should th e Preregulator output voltage exceed 51V, ze n er d io d e VR935 will co nduct, causi n g Q935 to also con du ct . Th e Pr e regulator ou t pu t current will th e n be s hunted t hroug h Q935, a nd th e output voltage will very q uick ly go to zero. With th e Vcc voltage of U920 no lo nger being s upp lied by the wi n di n g connected to pins 6 an d 7 of T933, the Preregulator will s h ut down a nd Q935 will be reset . T he su pply will then attempt to power up, but will agai n shut down o nce th e overvoltage cond itio n is reac hed . T h is sequ ence con tin u es until the overvoltage conditio n is corrected .

Inverter Th e Inverter circuit ch a n ges the d o voltage from t h e Preregulator to ac for use by the supplies that are connected to t h e seconda r ies of Τ940. T he outpu t of t h e P reregulator circuit is applied to th e center tap of Τ940. Power-switc h ing transistors Q940 a n d 0942 alternate con ducti n g curren t t hr oug h R 941 from th e primary ci rcuit common to the Prereg u lato r outp u t line. T h e transistor switc hing action is controlled by Τ942, α sat uratin g base-drive tra nsfo rmer.

When t he instrumen t is first tu rned on, one of th e switch i n g transistors will start to co nduct a nd t h e collector voltage will d ro p toward t he common voltage level. Th is will indu ce α positive voltage from t h e lead of Τ942 wh ic h is conn ected to t he b ase of th e condu cting tran sistor to reinforce cond u ction . Eventually Τ942 will saturate, an d as t he voltage across Τ942 (an d Τ940) begins to reverse, th e condu cting transistor cuts off because of t he drop in b ase drive. Th e oth er transistor will n ot start cond uctio n until t he voltage on t h e leads of Τ942 reve rse e no ug h to b ias it on . Th is process will contin ue, and th e saturation time of Τ942 pl u s th e transisto r-switc h ing time will d eter mine t he freq uency of Inverter operatio n (ty p ically 20 kHz). After the initial Inverter start up, t he switchi n g transistors do not saturate ; t h ey remain i n t he active regio n during switch ing. In instruments having th e C u rre n t L imit board, dio des CR 940 and C R942 serve as α negative-peak detector to ge nerate α voltage con trolli n g t h e outp uts of both th e Prereg u lator an d t he error amplifier. In instruments havi ng t he Prereg u lator board, dio d es CR 940 and C R 942 serve as α negative- peak detector to generate α voltage fo r co ntrolling t he output of th e error amplifier. Capacito r C951 will ch arge to t h e pea k am p litude of t h e collector voltage of 0940 and 0942 . T h is voltage level is applie d to th e d ivider composed of R 945, R 946, a nd R947. Th e e rror amplifier , composed of Q948 and Q954, is α differential amplifier th at compares t h e reference voltage of VR951 wit h t h e voltage on th e wiper of poten tiometer R 946. T h e cu rren t t h rou g h Q954 will set t he base drive of Q956 and t hereby co n trol th e

REV N OV 1982

Theory of Operation-2213 Service voltage on C957 . This voltage will bias 0940 and Q942 to α level that will maintain the peak-to-peak input voltage of Τ940. The amplitude of the voltage across the transformer primary winding and thus, that of the secondary voltages of Τ940, is set by adjusting -8 .6 V Adj potentiometer R946 . At turn on, Q948 is biased off and Q954 is b iased on . All

t he current of the error amplifier will therefore go through

Q954 to bias on Q956 . Diode CR956 allows the base of Q956 to go positive enough to initially turn on Q940 or Q942 . The current through Q956 controls the b ase drive for 0940 and Q942 . Base current provided by base-drive transformer Τ 942 will charge C957 n egative with respect to the Inverter circuit floating ground (common) level. NOTE The following paragraph applies only to instruments having the Current Limit board.

Voltage from CR940 and CR942 also provides α measurement of the minimum collector voltage of Q940 and Q942 with respect to the Inverter circuit floating ground . This voltage is fed back to the Preregulator through optical isolator U931 to control the output voltage fro m t he Preregulator circuit. As the n egative peak voltage at the collectors of the switching transistors is regulated by the error amplifier with respect to the output of the Preregulator, control of the do level from the preregulator will control the minimum voltage with respect to the floating ground . P otentiometer R952 (Head Room Voltage Adjust) is used to set this minimum voltage level to α point that prevents saturation and excessive power d issipation of the Inverter switching transistors .

C RT Supply H igh-voltage multiplier U990 utilizes the 2-kV win d ing of

Τ940 to generate 8 kV at one output to drive the crt anode. It also uses an internal half-wave rectifier diode to produce -2 kV for the crt cathode. The -2 kV supply is filtered by α t hree-stage low-pass filter compose d of C990, R992, R990, C992, R994, and R995. N eon lamp DS870 p rotects against excessive voltage between the crt h eater and εrt cathode b y conducting if the voltage exceeds approximately 75 V . Auto

Focus Circuit

Focus voltage is also developed from the -2 kV supply via α voltage divider composed of R884, R882, AUTO FOCUS potentiometer R883, R881, R880, R879, R878, R872, Auto Focus Adjust p otentiometer R875, and 0877 . The focus voltage tracks the intensity level through the action of Q877 . The Intens Level signal from the Auto Intensity circuit (Diagram 6) is applied to the emitter of Q877 through R877 . When the Intens Level signal changes d ue to α changing display intensity, the current through t he divider resistors changes proportionally . Auto Focus Adjust potentiometer R875 is adjusted to p roduce the best focus tracking . REV NOV 1982

L ow-Voltage

Supplies

The low-voltage supplies u tilize the secondary windings of Τ940 and are all full-wave, center-tapped bri d ges. The +100 V supply u ses CR961 and CR963 for rectification and u ses C961 for filtering. Diod es CR965 an d CR967 rectify ac from taps on the 100-V winding, and C965 filters the output to p roduce +30 V dc . The diode bridge consisting of CR971 through CR974 produces the +8 .6 V and -8 .6 V supplies . F iltering of the +8 .6 V is accomplished by C971, C975, and L971 ; while filtering of the -8.6 V is done b y C972, C976, and L 972. Voltage regulator U 985 uses the rectified +8 .6-V s upply to produce the +5 V out put . Diode CR985 protects the regulator by not allowing the output voltage to go more positive than the +8 .6 V input voltage. DC R estorer The DC Restorer circuit produces the crt control-grid bias and cou p les both do an d low-frequency components of the Ζ-Axis Amplifier o utput to the crt control grid . Direct coupling of the Ζ-Axis Amplifier outp ut to the crt control grid is n ot employed due to the h igh potential d ifferences involved . Refer to Figure 3-8 during the following discussion. The ac drive to the DC Restorer circuit is obtained from

pin 16 of Τ940. T he drive voltage h as α peak amplitude of

about 150 V and α frequency of about 20 kHz. The sinusoidal drive voltage is coupled through C863 and R863 into the DC Restorer circuit at the j unction of CR860, CR863, and R864 . The cathode end of CR860 is h eld at about +85 V by the voltage applied from the wiper of Grid B ias potentiometer R860. When the positive peaks of the ac-drive voltage reach α level that forward biases CR860, the voltage is clamped at that level. The Ζ-Axis Amplifier output-signal voltage is applied to the DC Restorer at the anode end of CR863. The Ζ-Axis signal voltage level varies b etween +10V and +75V, depending on the setting of the AUTO INTENSITY control . The ac-drive voltage will hold CR863 reverse b iased until the voltage falls below the Ζ-Axis Amplifier output voltage level. At that point, CR863 b ecomes forward biased and clamps the junction of CR860, CR863, and R864 to the Ζ-Axis output level. Thus, the ac-drive voltage is clamped at two levels on the positive swing of the cycle to produce an approximate square-wave signal with α positive dc-offset level. The DC Restorer is referenced to the -2 kV crt cathode voltage through R867 and C R867 . Initially, both C865 and C864 will charge up to α level determined b y the difference between the Ζ-Axis output voltage and cathode voltage. Capacitor C865 charges from the crt cathode through R867, CR867, CR868, and R 865 to the Ζ-Axis output . Capacitor C864 charges through R867, CR867, R864, and CR863 to the Ζ-Axis output .

3-25

T heory of Operation-2213 Service When the ac-drive voltage starts its positive transition from the lower clam ped level toward the hig her clamped level, the charge on C864 increases due to the risi ng voltage. The increase in charge acquired by C864 is proportional to the amplitude of the p ositive transitio n. Wh en the ac-drive voltage starts its negative transition from the upper clamped level to the lower clamped level, the negative transition is couple d t hro ugh C864 to reverse b ias CR867 and to forward bias CR868. The increased charge of C864 is then transferre d to C865 as C864 discharges toward t he Ζ-Axis output level. The amou nt of charge that is transferred is proportional to the setting of the AUTO I NTEN SITY control, since that control sets the lower clam p ing level of the ac-d rive voltage. The added charge on C865 also determines the controlgrid bias voltage. If mo re charge is added to the charge already p resent on C865, t he control grid becomes more

-AXI S OUTPU T

negative, and less crt writing-beam current will flow. Co nversely, if less charge is added, the cont rol-g rid voltage level will b e closer to the cathod e-voltage level, an d more crt writing-beam current flows. Dur ing periods that C865 is chargi ng, the crt control-gri d voltage is held constant b y the long time-consta nt discharge path of C865 through 8868 .

Fast-rise and fast-fall transitions of the Ζ-Axis output signal are coupled to the crt control grid thro ugh C865 . The fast transitions start the crt writing- beam current toward the new intensity level. The DC Restorer outpu t level th en follows the Ζ-Axis output-voltage level to set t h e new bias voltage for the crt control grid . N eo n lamps DS867 and DS868 protect the crt from excessive grid-to-cat hode voltage if the potential on either the co ntrol grid or the cat hode is lost for any reason .

η+1 ΦV ΤΟ +75V L-+10 V

+1 Φ0V

CO NTROL G R I D CR867 5Ζ

AC DR I VE VOLTAGE FROM T940, PIN 16

+15ΦV θ-

CATHOD E V OL TAGE S UPPL Y ( ;~ -2 kV )

8867

(-- ) DS868 DS867

3828-28

F igure 3-8. Simplified diagram of the DC

3- 26

Ι

restorer ci rcuit.

ADD N OV 1982

Section 4-2213 Service

PERF O RM A N C E IN

ι ι ι ι

10

ι ι ι

C HE C K PR OC E D URE

T R OD U CTIO N

PURP OS E The "Performance Check Procedure" is used to verify the instrument's Performance Requirements as listed i n the "Specification" (Section 1 ) and to d etermine the need for readjustment . These checks may also b e used as an acceptance test, as α p reliminary troubleshooting aid, and as α check of the instrument after repair . Removing the instrument's cover is not necessary to preform this p rocedure . All checks are ma de using the operator-accessible front- and rear-panel controls an d connectors . To ensure instrument accuracy, its p erformance should be chec ke d after every 2000 h ours of op eratio n or once each year, if u se d infrequently .

T E ST E QU I P M EN T RE QU I RE D The test equi p ment listed i n Table 4-1 is α complete list of the equipment required to accomplish both the "Performance Check Procedure" in this section an d t he "Adjustment P rocedure" in Section 5. Test equi p ment specifications d escribed i n Table 4-1 are the minimum necessary to provide accurate r esults . Therefore, equipment used must meet or exceed the listed specifications. Detailed operating instructions for test equi pment are not given in this p rocedure . If more operating information is re quired, refer to the appropriate test-e qui pment instruction manual . When eq ui p ment other than that recommen ded is used, control settings of the test setup may need to be altered. If the exact item of equipment given as an exam ple in Table 4-1 is not available, first check the "Purpose" column to verify use of this item . If it is used for α check that is of little or no importance to your measurement requirements, the item and correspon d ing steps may b e deleted. If the check is important, use the "Minimum Specification" column carefully to determine if any other available test equipment might suffice.

Special fixtures are u sed only where they simplify the test setup and p roce dure. These fixtures are available from Tektronix, Inc. an d can b e ordered by part number through your local Tektronix F ield Office or representative .

LI M ITS AN D TO LER A N C E S T

he tolera nces give n in th is p rocedure are vali d fo r an inst rument th at is operating in a nd has been p revio usly

calibrated in an ambient temperature between +20° C and +30° C. The instrument also must h ave had as least α 20minute warm-up p eriod . Refer to the "Specification" (Section 1) for tolerances applicable to an instrument operating outside this temperature range. All tolerances specifie d are for the instrument only and d o not inclu de test-equipment error.

PREPAR ATIO N Test equipment items 1 through 9 in Table 4-1 are

req uired to accomplish α complete P erformance Check. At the beginning of each subsection, in both t he "Performance Check Procedure" and the "Adjustment P rocedure"

sections, there is an equipment-required list showing only the test equipment n ecessary for p erforming the steps in that subsection. In this list, the item n umber t hat follows each piece of equipment corresponds to the item number listed in Table 4-1 .

This p roce dure is structured in subsections, which can be p erformed i ndependently, to permit checking individual portions of the instrument . At the beginning of each

subsection is α list of all the front-panel control settings

required to p re pare the instrument for p erforming Step 1 in that subsection . E ach succee d ing step within α p articular subsection should then be performe d, both i n the sequence p resente d and in its entirety, to ensure that control-setting changes will be correct for ensuing steps.

Performance Check Proce dur e-2213 Se rvice Ta ble 4-1 Test Item Νο . and Desc ription 1 . Cali bration Ge nerator

Eq uipment R e q uired

Minim u m

Specification

Stan d ar d-amplitud e signal levels : 10 mV to 50 V . Accuracy : ±0.3%.

Purpose

Examples of S uitable Test E q uipment

Vertical a nd horizontal chec ks an d ad ju stments.

TEKTRO N IX P G 506 Calibration Generator.'

Hig h -amplitu d e signal levels : 1 V to 60 V. R epetition rate : 1 kH z. Fast-rise signal level : 1 V . R epetitio n rate : 1 MH z . R ise time : 1 ns or less . Flat ness: ±0 .5%. 2. L eveled Sine- Wave Generator

Frequ ency : 250 kH z to above 70 MHz. Outp ut am plitude : variable from 10 mV to 5 V ρ-ρ. Output im pe d ance : 50 Ω . R eference frequency: 50 kH z. Am plitu de accuracy : constant wit h in 3% of refe rence frequ ency as ou tput frequency changes.

Vertical, horizontal, an d triggeri ng checks and adjustments . Display adj ustment and Z-axis c h ec k.

T EK TRONIX SG 503

3. Time- Mar k Generator

M arker outputs : 10 ns to

H orizontal checks an d adjustments . Display ad justment.

T EK TRONIX TG 501 TimeM ark Generator .a

4. Ca ble (2 required )

Im pedance : 50 Ω. Lengt h : 42 in . Connectors : bnc .

Signal interconnection .

Te ktronix Part N umber 012-0057-01 .

5. Termination (2 requ ired)

Im pe d ance : 50 Ω. Connecto rs : b nc .

Signal termination .

Te ktronix Part Nu mber 011-0049-01 .

Connectors : bnc-female-to-

Vertical chec ks and a djustments .

Te ktronix Part Nu mber 067-0525-01 .

7. 10Χ Attenuator

R atio : 10Χ. Im peda n ce : 50 Ω.

Connectors : b nc .

Ve rtical compensation an d triggering chec ks.

Te ktronix Part N um ber 011-0059-02.

8. Τ-Co n nector

Connectors : b nc .

Signal interconnection .

Te ktronix Part N um ber 103-0030-00.

9. Ad apter

Connectors : bnc-male-tomi niature p ro be ti p .

Signal interconnectio n .

Te ktronix Part Nu mber 013-0084-02.

10. Variable Autotransformer

Ca p able of supplying 1 .5 Α at 115 V.

Instrume nt input voltage adj ustment.

General R adio W 8 MT3 V M Variac Autotransformer .

'

6. Du al-Input Coupler

0.5 s. Marker accuracy : ±0 .1%. Trigger ou tput : 1 ms to 0.1 μs, time-coi nci d ent with ma rkers.

d ual-bnc male .

' Req ui res α TM 500-series power-modu le m ai nframe.

Leveled Sine-Wave Generator.'

Performance Check Procedure-2213 Service Table 4-1 (cont) Item Νο . and Description

M inimum

Specification

Examples of Suitable Test Equipment

Purpose

11 . Digital Voltmeter

Range : 0 to 140 V. Dc voltage accuracy : ±0 .15% . 4 1/2-digit d isplay .

P ower su pply checks and

T EKTRONIX DM 501 Α

12 . Test Oscillosco pe with included 10Χ probe (Standard Accessory) and 1 Χ probe (1 Χ probe is option#accessory) .

Bandwi dth : d o to 10 MHz. Minimum d eflection factor : 5 mV/div . Accuracy : ±3°/ο.

P ower su pp ly ripple check

α. T EKTRONIX 2213 Oscilloscope . b. TEKTRONIX Ρ6101 P robe (1 Χ). P art N umber 010-6101-03 .

13 . DC Voltmeter

R ange : 0 to 2500 V, calibrated to 1°/ο accuracy at -2000 V.

H igh-voltage p ower supply check.

Triplett Mo d el 630-NA .

14. Screwd river

L ength : 3-in shaft. Bit size : 3/32 in .

Adjust variable resistors.

Xcelite R -3323.

15. L ow-Capacitance Alignment Tool

Length : 1-in shaft. Bit size : 3/32 in .

Adjust variable capacitors.

J .F .D . Electronics Corp .

adjustment. Vertical adjustment .

and general troubleshooting.

Digital Multimeter .a

Adjustment Tool Number 5284 .

aRequires α TM 500-series power-module mainframe.

IN

Vertical

Horizontal (cont)

DEX TO PERF O R MAN CE CHE C K ST EPS Page

1 . Check Deflection Accuracy an d Variable R ange . . . 4-4 2. Check Bandwi dth . . . . . . . . . . . . . . . . . . . . . . . 4-5 3. Check Common-Mode R ejection R atio . . . . . . . . . 4-5

H orizontal 1 . Check Timing Accuracy . . . . . . . . . . . . . . . . . . . 4-6 2. Check S EC/DIV Variable R ange . . . . . . . . . . . . . . 4-7 3. Check Delay Time R ange . . . . . . . . . . . . . . . . . . 4-7

REV NOV 1981

4. 5. 6. 7.

Check Delay Time J itter . . . . . . Check POSITION Control R ange Check Χ-Gain . . . . . . . . . . . . . Check Χ-Bandwidth . . . . . . . . .

Page . . . .

. . . .

. . . .

. . . .

. . . .

. . . .

. . . .

. . . .

. . . .

. . . .

. . . .

. . . .

. . . .

4-7 4-8 4-8 4-8

Triggering 1 . Check Internal Triggering . . . . . . . . . . . . . . . . . . 4-9 2. Check External Triggering . . . . . . . . . . . . . . . . . . 4-10 External Ζ-Axis an d P robe Adjust

1 . Check ΕΧΤ Z-AXIS Operation . . . . . . . . . . . . . . .4-12 2. Check PROBE ADJUST Operation . . . . . . . . . . . .4-12

4-3

Performa nce Check Procedure-2213 Service

VERTICAL Eq ui pment

R eq uired (see Table 4-1) :

Cali br ation Generator (Item 1)

L eveled Si ne-Wave Gene rator (Ite m 2)

50-Ω BN C Terminatio n (Item 5) Dual-Inpu t Couple r (Item 6)

50-Ω BN C Ca ble (Item 4)

IN

ITIAL CO NTR OL SETTI NGS ON (bu tton i n )

POWER C RT AUTO INTEN SITY AUTO F OCUS

Vertical

POSITIO N (bot h)

VERTICA L MOD E CH 1 VOLTS/DIV CH 2 V OLTS/DIV V OLTS/DIV Va ria ble (bot h) I N VER T AC-G ND-DC (bot h)

H orizontal

POSITIO N H OR IZONTA L MOD E SEC/DI V SEC/DI V Variable Χ 10 M agnifier

Trigger

V AR HOLL DO FF

As d esire d B est focused d isplay

M idrange CH 1 2 mV 10V

M idrange ΝΟ DL Y 0.5 ms CA L detent Off ( k no b i n)

SLOPE

ΙΝΤ SO UR CE

VERT ΙΝΤ

LEVEL

ε. Set the VERTICA L MOD E switch to CH 2 and move the ca ble from the CH 1 OR Χ nput connecto r to the CH 2 OR Υ i nput co nnecto r.

i

CA L dete n t N ormal (button out) DC

NORM A UTO _r

MOD E

b. C HE CK-Deflection accu racy is wit hin the limits give n i n Table 4-2 fo r each CH 1 V OLTS/DI V switch setti ng and corres pon d ing stand ard-amplit u de sign al . Wh en at the 20-m V VO LTS/DI V switc h setting, rotate the CH 1 V OLTS/DIV Va ria ble control fully co un terclockwise an d CHECK t h at the d is play d ecreases to 2 d ivisio ns or less . Then ret urn t he V O LTS/DI V Varia ble cont rol to the CA L detent and co ntinue with t he 50-m V ch ec k.

M i d range

M OD E

PR OC E D URE ST EP S 1 . Check Deflection Accuracy an d V ariable R ange α. Con nect α 10-m V stan dard-amp litude signal to the CH 1 OR Χ i n put connector usi ng α 5042 ca ble .

Table 4-2

Deflection Accu racy Limits

Vertical Deflection (Divisio ns)

3% Accuracy L i mits (Divisio n s)

10 mV

5

4.85to5.15

5 mV

20 mV

4

3.88 to 4.12

10 mV

50 mV

5

4.85to5 .15

VO LTS/DIV Switch Setting

Standard Am plitude Signal

2 mV

20 mV

0.1 V

5

4.85to5 .15

50 mV

0.2

V

4

3.88 to 4.12

0.1 V

0.5 V

5

4.85 to 5.15

0.2 V

1 V

5

4.85 to 5.15

0.5 V

2V

4

3.88to4 .12

1 V

5V

5

4.85to5 .15

2V

10 V

5

4. 85to5.15

5V

20 V

4

3.88 to 4.12

10 V

50 V

5

4.85to5.15

Performance Check Procedure-2213 Service

d. CHE C K-Deflection accuracy is with in the limits given in Ta ble 4-2 for each CH 2 VO LTS/DIV switch setti ng and correspond ing stan da rd -amplitude signal . P erfo rm the chec ks from t h e bottom to the to p of Table 4-2 to avoi d unnecessary switch-positio n changes. Wh en at the 20-m V VOLTS/DIV switch setting, rotate the CH 2 V OLTS/DI V Varia ble control fully coun te rclockwise a n d CHE C K that th e d isplay decreases to 2 d ivisions or less . Then retu rn the VOLTS/DIV Varia ble control to the CA L detent an d finish t he chec k.

2. Chec k Ban d width α. Set:

3. Chec k Common-Mode

R ejection Ratio

α. Set both VO LTS/DIV switches to 20 mV .

ε. Set the generator outp ut am plitu de to pro d u ce α 6-d ivision display.

2 mV 20 μs

S E C/D1 V

upp er limit of the sine-wave ge nerator being used .

b. Con nect α 10-MHz, levele d sine-wave signal via α 50-Ω ca ble, α 50-Ω te rmination, an d α dual-i nput couple r to t he CH 1 OR Χ a nd t he CH 2 OR Υ i nput connectors.

e. Disconnect the test setu p.

V O LTS/DI V (b oth )

h . Repeat p arts c through e fo r all indicated CH 2 VO LTS/DIV sw itch settings, up to the outpu t-voltage

b. Co nn ect the levele d sine-wave ge nerator outpu t via α 50-Ω ca ble and α 50-Ω terminatio n to the CH 1 OR Χ input co nnector . ε. Set the ge nerator output amp litude fo r α 5- division, 50-kH z display.

d. Change the gene rator out p ut frequ ency to the value show n i n Ta ble 4-3 fo r the co rr espo nding V OLTS/DI V switch setting.

d. Vertically ce nte r the d is play using the Ch annel 2 P OSITIO N co ntrol . Then set VERTICA L MOD E to CH 1 an d vertically center the d isplay u sing th e Ch a nnel 1 P OSITIO N cont rol . e. Set the VERTICA L MOD E switches to BOTH and ADD ; then push in the I NVER T button. f. CHE CK-Dis p lay am plitu de is 0.6 d ivision o r less . g. If the check in part f meets the re qu irement, skip to

p art η. If it does not, continue wit h p art h . Table 4-3 Setti n gs fo r B andwi dth Chec ks

VOLTS/DI V Switch Setti n gs

Ge nerator Output Fr equency

2m V to10mV

Ι

50 MHz

20 mV to10 V

1

60 M Hz

e. CHE CK-Dis p lay am p litu de is 3.5 d ivisions or greate r. f. R epeat parts ε t hroug h e for all ind icated CH 1 VO LTS/DIV switch setti n gs, up to the outpu t-voltage up per limit of the sine-wave ge nerator being used. g. M ove the gene rator outp ut signal from the C H 1 OR Χ i nput co nnector to the CH 2 OR Υ i nput co nnector . Set the VERTICA L MOD E switch to CH 2.

h. Set VERTICA L MOD E to CH 1 . i. Change the ge n erato r freq ue ncy to 50 kH z an d a dju st the output to obtain α 6- d ivision d is play. j.

Set VERTICA L MOD E to BOTH .

k. Ad just the CH 2 VOLTS/DIV Varia ble co ntol for minimum display am plitu de (best CMRR) . Ι. Change the generator frequency to 10 MHz. m. CHE CK-Dis p lay am plitu d e is 0.6 d ivision or less . η. Disconnect the test setup.

Pe r fo r ma n ce

Ch ec k P roce d u re-2213 Serv ice

H O R IZO N TA L Equ i pment R equ ired

(see Table 4-1) :

Cali bration Gene rator (Item 1)

Leveled Si ne-Wave Ge nerator (Item 2)

Two 50-Ω BN C Cables (Item 4) Two 50-Ω BN C Te rminations (Item 5)

Time-Mar k Ge nerator (Item 3)

I N ITIA L CO N TR OL

P OWER

CRT

AUTO INTENSITY A UTO FOCUS

S ETTI N GS

ON ( button in)

As d esired B est focused display

Vertical

Chann el 1 POSITIO N Midrange VERTICA L MOD E CH 1 CH 1 VOLTS/DIV 0 .5 V CH 1 VO LTS/DIV Varia ble CA L detent N ormal (b utton out) INVER T Ch annel 1 AC-G N D-DC DC GND Chann el 2 AC-G N D-DC

H orizontal

POSITIO N

H O R IZONTA L MOD E SEC/D1 V SEC/DI V Variable Χ 10 M ag nifier D EL AY TIME MULTI PL I ER

M i d range ΝΟ D L Y 0.05 μs CA L detent Off (kno b i n) 0.5 lis X20 .

d. CHE CK-Each DELAY TIME and SEC/DI V combi natio n under "MUL TI PL I ER >Χ20" in Table 4-5 produ ces α noni ntensified d is play of le ngt h s how n in t h e "Display Length" column .

Ta ble 4-5

Delay Time R a nge Ch ec ks MULTI PL IER Χ20

Display L ength (Divisions)

SEC/DI V Setting

Dis p lay Lengt h (Divisions)

0.5 μs

0 .1 μs

5

lops

2 μs

4

0.2 ms

50 μs

4

2. Chec k S E C/DI V Variable R ange α. Set : CH 1 VOLTS/DIV S E C/DI V S E C/DI V Variable Χ10 M agnifier

0.5 V 0.2 ms Fully counterclockwise Off (kn ob in)

b. Select 0.5-ms time ma rkers from th e time-mark generator.

ε. CHE CK-Time ma rkers are 1 d ivision or less ap art.

d. R etu rn

d etent.

the

SEC/DI V Variable cont rol to th e CA L

4. Check Delay Time α. Set:

J itter

CH 1 VO LTS/DIV Channel 1 AC-G N D-DC S EC/DI V D EL AY TIME MULTI PL IER b. Select generator.

50-μs time

0.5 V DC 50 μs lops Χ20" in Ta ble 5-8 p rodu ces α no n intensified display of length s hown in the "Dis p lay Lengt h" column . 8. Chec k Delay Time

J itter

α. Set: CH 1 V OLTS/DI V C h ann el 1 AC-G N D-DC

S E C/D 1 V DELAY TIME MULTI PL I ER

0.5 DC

V

50 μs 10 μs Iich t h e comp o n e nt is a nd λ ocated in α cor ner t t he boa rd o utli ne .

Ι

3C 1G « 3E 3D 3C 3D 3E 3C 3D 2D 4Β ν 3Β θ 2D 3D 3D 3Β

CIR C U IT NUMBER

ι

Q656 0665 Q668

BOAR D SC HEM LOCATIO N LOCATIO N

2F 1G 2G

2Θ 18 2Β

Α604 R605 R 608 R 609 R 610 R 614 R616 R623 R625 'r R627 εεσ30

4C 5υ 4E 4E 78 7C 1C 40 7F 7F 7G

1E 1E 1υ 2D 3E 3D 3D 2E 2D 2D 1D

ΤΡ624

3Β

2D

U615

1D

3C

Ι

diagra ms a nd ci rc u it b oa rd ill u strations .

L 635

SC HEM BOA R D LOCATIO N LOCATIO N 51

C H ASSIS

Α

ν

2 3

C H ASSIS MO UN TE D P A R TS CI R C U IT NUMBER

MA NUA L B I ND ER

CIRC U IT NUMBER V635

SCHEM BOA R D LOCATION LOCATIO N 6J

C H ASSIS

4

3 . L ocate the Component on t he Schematic Diagram α.

Locate and pull out tabbed page whose number a nd title correspond with t he Schematic Diagram Number just determined i n t hetable . Schematic diagram nomenclature and n umbers are printed on the front side of the tabs (facing the front of the m anual) .

b.

ε.

Und er t he SCHEM LOCATION column, read t he grid coordinates for t he d esired component .

d.

Using the Circuit Number a nd grid coordinates, locatethe component on the schematic d iagram .

Scan the Component Location Table adjacent to the schematic d iagram and find t he Circuit N umber of the d esired component .

PULL O UT PAGE TABS F OR SCHEMATIC DIAGRAMS

π π z π c

P ARTIAL Α 6 C RT CIRCUIT BOARD

CR T CI RC U IT ιο

SCHE MATIC DIAGRAM NAME AND NUMBER To id entify any component in α schematic d iagram a nd to locate that component on its respective circuit board .

3516-81

5105

CH 1 AND CH 2 VERTICAL PREAMP CH 1 O R Χ

C H 1 HIGH -Ζ ATTENUATOR AND INPUT COUPLING

C H 20R Y

CH 2 HIGH-Ζ ATTENUATOR AND INPUT

ι

I

COUPL NG

CH 1

CH 1

BUFFER AWL

L OW-Ζ

Q122, Q125 0133, Q134 Q139, U 120

ATTENUATOR R 139

CH 2 BUFFER AWL Q222, Q225

CH 2

L OW-Ζ

ATTENUATOR R239

Q233, 0234

0239, U22θ

CH 1 Χ 1/Χ1 θ AWL U 146

CH 1-

CH 2 Χ 1 / 0 AWL U245

CH 2-

CH 1+

CH 2+

ι

C H 1 ΡRΕΛΜΡ 0157, Q1 β7 U 17 ΘD , Ε

CH 2 ΡR ΕΛΜΡ

Q257) Q258 0257, 0268 U2700 ,E

CH 1 TR I G+ CH 1 TR I GCH 2 TR I G+

I

CH 2 TR G-

INTERNAL T RIGGER PICKOFF Q173, Q273

U 170A , Β C U 197Λ Β D ,Ε U270Α ώ PC

Ι

S201

I NVERT

S205

ΛC-GNO-DC

S2β4

CH 2 VOLTS/DIV SWITCH

S4 θ 1

I NTERNAL

AC-DC-DC+10 ΕΧΤ INPUT

ΕΧΤ COUPLING

INTERNAL

EXT TRIGGER AWL

Qt 1 1 Λ ,Θ

Q 14

_ ΙΝΤ

S44θ

~ χ ω

INTERNAL TRIGGER AWL

ά t, ~

i

I

DIODE S W ITCH ING

CR t 18 , CR440 CR 444 , CR448

S4 β4

I

TR GG ER

LEVEL _ COMPΛRΛTOR U4 β 0Λ Β C , D ,Ε ,F

SLOPE

SLOPE

LEVEL

Ι

πυΤ Sβ11 T RIGGER MODE

NOR

Ι 1

I

I

SC HM TT

TV TR G

TR I GGER AND LEVEL

AND I NVERT IN AWL

SH I FTER

α ω υ υ ά Η

i _

T RIGGER

Q492, Q493 U48 θΛ B ,D

Q474 Q47 β

m ω >-

AUTO

B ASEL I NE Q605 Uβ4θΛ

AUTO DISABLE

TV F IELD

ΥΑR HOLOOFF R557

U48θC

LEVEL

Rt55

T R I GGER

SIG

X-AXIS

U421 Α Β C D Ε

TR GGER SOUR C E

LINE ΕΧΤ

SOURCE

υ ~

T RIGGER + TRIGGER -

AUTO

BASEL I NE

z υ Ν Χ Ι Χ

S660 DE AY

TIME

.5μs

Χ28 MULTIPLIER R658 ΝΟ αΥ

HORIZONTAL MODE S65θ

F igure 9-4. 2213 block diagram.

αΥ - ο ΙΝτεΝS

CH 1 P OSIT ION CHANNEL SWI TCH AND VERTICAL O UTPU T

C H 1+

COMMONBASE πΜΡΙ Q177 Q178

f1 R 19θ

ERNΛL WER WFF CH IG ι Q273 j_ CH 2 TR I G 1 Λ ιθ ,C W 1 ιθ ,D , Ε 1 Λ ιΒ ,C COMMONBASE Τγ ΛΜΡL Q277 Q278

CH 1-

CHANNEL

DIOD E GATE

C R177, C R 187, CR277 , CR287 ,

CH 2+

CR 178 C R I BB CR278 CR288

CH 1 ΕΝΛΒLΕ CH 2 ΕΝΛΒLΕ

CH 2-

CH 2 TRIG

POS I TION

TIMING SW ITCH R629

XY

ΤΙΜΙΝG SWITCH TCH AND RC S63θ

CAL

HOLDO FF

A UTO

Ι

SWEEP LOGIC 1603 Λ , Β (Ιθ7Α , Θ ,C

VERTICAL M ODE

υ rc

z

HOLDOFF TIMING U64013

Σ Η

ο z ω

υ α s Ν

r

SWEEP LOGIC GATING U62θ

r

0624, Q632 Q644, 0650 0652

I NTERNAL T RI GGER

S W ITC H ING LOG I C

U3θ5Λ , θ ,C ,D U3158 ,C ALT SYNC

C HOP C HOP

CHOP OSC I LL ATOR AND CHOP BLANK ING U31 θΒ ιC ,D U 3178

υ z Η

z z

M I LLER

SWP RE TRACE

SWEEP Q63ΘΑ , Β Q631

Φ a0 τ υ

SWEEP

SWP DUTY AU TO

r

DEL AY TIME

υ

ALT SYNC END-OF -SWEEP COMPARATOR 0640

GATE

CHANNEL SW I TCH I NG L OGI C U 310A 17A U3

ΧΥ

ω

Σ ο Ν υ = Ιτ

ω

CH 1 BOTH CH 2 ADD A LT

S315 S317

R557

S WP

ADD ENABLE Q31 β U197C U 315A

R290

C H 1 TRIG CH 2

DELAY LI NE DR I VER Q331, Q336 Q341, Q345

< ω ο

1

S WP D U TY Z-AXIS U6070 ι C R620 , C R622,

GATE

CR619 CR621 CR663

I

Ζ-D R IVE

AUTO I N T EN S I TY Q811 , Q812 Q813 U825 B ,C U835A ,Β

NTENS LEVEL

Ζ-DR I VE

Rβθ 7

AUTO INTENSITY I

SWEEP G ENER ATOR A ND L OGIC

Z-AXIS I NPUT

BEAM F I ND S39θ

ix

Z-AXIS

AMPL I F I ER

Q841, Q844 0845, Q847 Q85θ

N TEN S LEVEL

AUTO

INTENSITY AND Z-AXIS

L I NE

TR I GGER

Χ-AX I S S I GNAL

IELJ1 Υ

2213 Se rvice

VERTICA L O U TPU T ΛΜΡL Q35θ , Q38θ Q37β , Q377 Q38β , Q387

VERTICAL VERTICAL

CH

PROB E ADJUST

S305 ΙΝΤ

TRI GGER

CH 2

SOURCE

S734 HORI Z

O UTPU T

ΛΜΡL Q747, Q753 Q703, Q705 Q770 i 0775 Q779, Q78θ Q785 ι Q789

ΧΥ ΛΜΡL Q7θ3, Q7 θβ Q7θ8, Q714

ΧΥ AMPL I F IER / HORI Z OUTPU T

R883 AUTO

FOC US

PO WER S UPPL Y, PROBE ΛDJ AND CRT

INTENS Z-AXIS

LEVEL

S I GNAL

CURREN T L IMIT Q933, Q938

+ ηςγ

3827-19

2213 Service

TE ST WAVEFO RM AND VOLTAGE S ETUP S WAVEF O RM

ME AS UREMEN TS

On the left- han d pages p receding the sc hematic d iagrams are test waveform illust rations that are inte nd e d to aid in trou bleshooting th e in st ru ment . To test the i nst ru me nt fo r t hese wavefo rms, ma ke t h e initial co n t rol settings as follows:

Changes to the cont rol setti ngs fo r specific wavefo rms are n oted at the b eginni ng of each set of wavefo rms . I nput signals and hoo kups r equ ired are also in dicated, if needed, fo r eac h set of waveforms.

DC V O LTAG E ME AS UREMENTS

Crt AUTO INTEN SITY AUTO F OC US

Visible d isplay Best focuse d d isplay

Vertical (Bot h C hannels, if app lica ble) CH 2 INVERT V OLTS/DIV

VOLTS/DI V V a ria ble AC-G ND-DC POSITIO N

VERTICA L M OD E

Off ( button out)

Typical voltage meas ur emen ts, locate d on th e sc hematic d iagra m, were obtained with t he inst ru ment operating u nder t he con d itio n s specified in t he Waveform M easurement setup . Co ntrol-setti ng ch anges requ ired for specific voltages are ind icated on each waveform page. M easurements are referenced to chassis grou nd with the exception of t he Pr ereg u lato r an d Inve rte r voltages on d iagram 9. Th ose voltages a re reference d as i ndicated on t he sc hematic d iagram .

10 mV CA L detent

RE CO MMEN D E D TEST E QU I PMENT

GN D

Display Centered CH 1

Test equ ipment listed i n Ta ble 4-1 in the "P e rfo r mance

C hec k Procedur e" sectio n 4 of this ma nual, meets the

requ ired specifications for testing th is instrume nt.

H orizontal POSITIO N Χ10 M AG

M idrange

SEC/DI V SEC/DI V Va r iable

.5 ms CA L detent

H ORIZO NTA L MOD E

Off ( bu tton in ) ΝΟ DLY

T rigge r SLOPE

f

MOD E ΙΝΤ

AUTO VERT M OD E

VAR H OLDO FF

M in (f u lly ccw)

LEVEL

SO UR CE

Midrange

ΙΝΤ

REV D EC 1981

P OWER S UPPLY ISOLATIO N PR OC EDURE E ac h regulated s upply h as n ume rous feed poi nts to external loads thr o ugh o ut the instru me nt. The power d istribution d iag ram is u sed in co nj unction wit h th e sc hematic d iag rams to determine those loads that can be isolated b y removing se rvice ju mpers and those t h at ca nn ot . The power dist ribu tion diagram is d ivided i nto ci rcu it boards . E ac h power su pp ly feed to α circ u it boa rd is in d icated by the sc hematic d iagram n umbe r on whic h the voltage a pp ea rs. The sc hematic d iagram grid location of α se rvice ju mper or co mponent is give n adj acent to the component number on the p ower distribution d iagram . If α power supply comes up afte r lifting one of the main j umpe rs from the p ower supply to isolate that su pp ly, it is ve ry pr obable that α s hort exists in the ci rcu it ry on t h at su p ply li n e. By lifti ng ju mpers fa rth er down the li ne, t h e ci rcu it in whic h α s hort exists may be located. Typical resistance values to ground from the r eg ulated su pp lies outp u t as measured at the supply test points are: -8 .6 V +8 .6 V +5 V +30 V +100 V

114 0 at ΤΡ 500 95 Ω at W 975 330 Ω at W985 905 Ω at W965 12 .5 kΩ at W966

R esistance values significantly lowe r may i n d icates shorted components in the load. Val ues will va ry between i nst rume n ts .

Always set the P OWER switc h to OFF before solder ing or un soldering service j um pers or ot h e r components d an befo re atte mpti ng to measure components r esistance values .

+1001/

W9~4 3J

+10Ον -

+3Ον ,

ι ι W`"~Cb 3J

7 ~7799 Ο 8J _ ι ι ιι ι Ο C SJ -O,-TL 0

ω 9Φ9 E31

\N3Ά

RWF9 W 4L Ο ©ca49~

+1~V 1 ΗΟRΙΖ Ο ρ Τ AMPL

GRID BIAS RSbO ΑΝ ID GFAΜ ΑDJ . R8Ν

+ICOV Ζ PXI ΑΟ

+=λο\d

83

VERT OUT PUT

3 Ο

ι399

7Ν

R79B Β .ι Ο

+~ν

ΑΧ \L

\N96S 3S

C91 λΓι

FROM POW SUPPLYR

W9 J~7 R9J Ο ~Ce5 0 ~9gΚ~

PULL-UP AND AMPL

HORIZ. ν C~μΡUίο

νυr 9 ο

+5V

_

ν

W985 (.3 WSSb bJ

Ι

Ι 3C +θ bν2 ~ +8.bυ2 CΗΙές~-1Ζ CN Ι L Cμ2 ΥΕφΡRΕλ)ΛΡ 20 ν (ΡΑΡΤΙΕ ~ +Β. bν4 Χ AXIS AMPL ~-y +8 .6υ4 ΙΝ7 Τ 4 ΙG _ C431 7Ο BUFFER _ ® SWITCH

ν

~ ω4ο

ο1.ιε -sΗΟτ Α GΑτΕ C01νταοL LGGIG ΟΟΟ

-8.6ν

ννΓο Ζ© W 4©

TRG SELEC-T ~ ΡΑατιη ~~' L1

bJ

\N ΘΑ2 92 -H V Α G .b ΑΤΕΟ RESEΓ

G457`Υ 8Ο ΡΑ57

-Θ. ιcV 3 Α TRIG COMPΑRATOR

®

ω87E6 ωθ77 31 9

W 297 4ι

Ψ ®C4121 2Ο ®R3D 1

©CβΚ7

-θ.ων AuΤΟ Fοωs AMPL

ω299 41ςμ G2991 ~ .Φν2 G Α ΤΤ _ ΟΕ1.ΑΥ ιΙΝΕ Ο W29 DRIVER

AU TO ΙΝΤΕΝSΙΤΥ CIRCU IT

GΝΟΡ OSG VERT CNANwEL SEL Ψ GIC ΑΝΟ RR ~~EL LOCIC 1 ΝΤ ~T

G317 G310 1~ ~

- 8"bν DELAY ί οΝΕ -SHOT

W9τώ/~

Οωθ ο

f

0CT%~ 9J

ω8Α7 RTeb IDΖ 9J Ο W I7O 41-8"b2 CΕΖ VERT ρ Ρ

_

INΤ ΤRIG ΡIGΚΖFF , ρ VERT ΙΧ0ΤΡ JΤ ΑΜΡL Ο 3 -1B. ΙΝΤ "4/4 TRIG BUFFER

-θ~\/ C}41 1 Β 50URGΕ ZD ί _ Ρ4 ρ ΖΑΧΙδ © ΑΜΡL

_β bνι H OR IZ OUTPUT ΑeηΡι -8 .6 ν

" νεπτ ουτ ADD FILT E CRT -Bbνz ιΗ ι νΕRΤ ΡΡΙΕΡΜΡ _ Α "

NUMBE RA L I

C1 RCU_ R ΝΙΝ

SHOWN ΟΝ~1

CΟΑΛ )ΟΝΕΜ ΟΝ ΤΗΕ ΑΡΛ

ψ 1ςΤ3 βι 8 ψ 1Cgί9O Rσ-Ι 9

S

M'tωΕΕΡ ULL F R R

EL

ΙΝ7Ε G ΑτΟRδ

41

O

33Εμz-ι -z ι REV D EC ι gθι

P WER O

DIST

R BU I

TIO

FpFiιΖ ρμΡ ΑξΕΙ

8L

NUMBER AL AND LETT ER AT COMPONENT CI R CUIT NUMBER IN DICAT ES G R ID COORDI N AT E WHERE CO MONENT IS SHOWN ON ΤΗΕ APPLICA BLE DIAGRAM. COMPONENT VALUE S ARE HOWN NLY ON ΤΗΕ A PPLICABLE DIAGRAM.

-8.6 ν ν VERT ΑΤΤΣΝ REF ZEUER ΒWΕΕΡ '1ΟυΤΑ.Ε R ΕFO

N

ΡΙΟΙΟ ι ί , 3 Ι

ιW1011 -1 -i ~-2 ~-4

GND CH I(,) C4 Ις-ι GND

3 Rz οιο

(ω2οι 1 -Ι ~-i ~-2 " -4

GND CH 2(+) CH 2l-) GN D

' Ι } }Ι Ρ7000 +3oV ~ Θ.bV ι

Ι ω7ΟΟΙ

ι _q

~-

~R739 i SO R720 ~ 630Β-6 i ./-V LB

ί ~-i --5

Η PREAMP ουΤ

-764 q~ιαν W763 υ825Α- ιιυ825Β-Ι 3

R7b0

CλΖλ7ΡθΟΟ 6

ί Ι

5205

ι

56308-3ι 4 ν 5630B-s R725

ΧΥ

χΥ -

ηΙ Ιη

~-C R 7034J

W702

R726 ΗΟ RιΖΟΝΤΑ L Po51710U

λΟ

βFΑΜ FIN D

Ι

53 Ι 7- β,53ΙΤ~~~11 3 53 ι 7-G ΟS264ρ 5305-β,S3Ο`υ-ς 1ΝVE R 7 Ι

- Β_7 - Β W630

ι

R8 5 Re 9 ,ι

vAR +&6V HOIDOFF W ΓΙ55Τ ΙΟ

ι

Ο

8"v RG 45

R 6-

t

TREGGER IR4441>

`_1

!

W508

_

U 507A-Ι

8453

U5078-7 Ο R 6ΙΙ ι R525, R517

JIODI GH I ΙΝΡΙΠ J200i GH 2 ΙΝΡυτ

m

Ψ ι

J1000 ΡRο~ε ' ADJU~

R 496F" ο C W 3

.CR536

ΑΙ Ι

2213

R 637

Ο

J4001 ΕΧΤ ΙΝΡ UΤ

F RΟ ΝΤ PAN EL BOAR.

Ν ύ ύ Ι τ Ζ

ΑΙΟ ΜΑ1 Ν ΘΟΑRD Wb001

-5 -9

sezτ-zo FED Oat

REV

.Α.ξ .ΟΤΆ1 ΟΝ

: ςλl

Fλ Ι

ΙΙι ι

ΓR86Β

Q35.

ς_ι

R 883~

4387 Q377

RIBS

R178

ωα 7ΟΟ

Q360

-8700

R99? y

Τ94Ο-5 i -24 Ο '94

N .C NC.-~

ι

- R760

ANOD E +8 KV

{λ3λzl '1'

-Ti

R876 C076

C806 R00b R887

R073 C873 R574

C871 R071 R870 1

6\y

F901 J9001

GR Y

ΗΙβΗ

VO LTAG E M ODULE

' Ρ 9 ΟΟΟ

(Ε - Ζ

ι 59 ΟΙ -213

Ο αιυ

-S901-4,5

P902S

Ζ ΑΧΙ5 ωΡυ 7

ρ

R 496'" Ο Ο9 TΙ Ι

- R801

RG37

Γ -Ι V

V

11

760 1 71-7, 3

J8001

ύ ύ

3ez7-zo

REV FED 1987-

3

Λ Λ C_ 1Ι

ύ ύύ 7 ΖΖ ι

Ο,

3

σ z

CI RCUIT 90A RD ΙΝΤΣ RCΟΝΝΣ CΤΙΟΝ5

Λ Ο

ΖΙ Ζ

m

Λ Ο

Ζ Υ!

2213 Service

Α

'

Β

~

C

~

D

Ε

~ ! R 627 ='_ω'-`

Ι !742 (-

ι' m ~

F

~

0629

' β733

VR 629

W 633

βG86

R 634

2

3

4 3827-31

5

©Static Se n sitive Devices See Maintenance Section COMP O NENT

NUMBER EXA MPLE

Component Numb er

Fig ure 9-5.

Α23 Α2 A12-Attenuator/Sweep

boa rd .

Assem bly Numb er

R 1234

hematic ~~~~ScCircuit Subassem bly Number Number (if used)

Chassis-mounted components have no Assembly Numb er prefix-see end of Re placeable Electrical Parts List.

Α 12-ΑΤΤΕΝ UΑΤΟ R/SWEEP

CI R C UIT NUMBER

C104 C105 C107 C110 C111 C112 C119 C121 C123 C125 C132 C133 ς 134 C136 C137 C139 C140 C141 C142 C144 C204 C205 C207 C210 C211 C212 C219 C221 C225 C232 C233 C234 C236 C237 C239 C241 C242 C244 C625 C626

SC HEM NUMBER

CI R C UIT NUMBER

SC HEM NUMBER

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 8 8

C628 C630 C636 C677 C679 C720 C732 C734 C736 C738 C741 C R 119 C R 219 C R 626 C R 630 Ρ 1010-1 Ρ 1010-2 Ρ 1010-3 Ρ 1010-4 Ρ2000-10 Ρ2000-1 Ρ 2000-2 Ρ 2000-3 Ρ 2000-4 Ρ 2000-5 Ρ 2000-6 Ρ 2000-7 Ρ 2000-8 Ρ 2000-9 Ρ 2010-1 Ρ 2010-2 Ρ 2010-3 Ρ 2010-4 Ρ 6000-10 Ρ 6000-1 Ρ 6000-2 Ρ6000-3 Ρ6000-4 Ρ6000-5 Ρ6000-6

8 5 8 8 8 7 7 7 7 8 8 1 1 5 5 1 1 1 1 5 1 1 1 1 1 1 8 8 7 1 1 1 1 7 5 7 7 5 5 5

CI R C U IT NUMBER

Ρ 6000-7 Ρ 6000-8 Ρ 6000-9 Ρ 7000-1 Ρ 7000-2 Ρ7000-3 Ρ7000-4 Ρ7000-5 Ρ7000-6 Ρ7000-7 Q122 Q125 Q133 Q134 Q139 Q222 Q225 Q233 0234 Q239 Q629 Q630 Q631 Q720 Q730 Q731 Q736 R 103 R 105 R 106 R 107 R 108 R 110 R 111 R 112 R 114 R 115 R 116 R 117 R 119

SC HEM NUMBER

5 7 7 8 8 8 8 7 7 8 1 1 1 1 1 1 1 1 1 1 8 5 5 7 7 7 7 1 1 1 1 1 1 1 1 1 1 1 1 1

CI R CU IT NUMBE R

R 120 R 121 R 122 R 123 R 124 R 125 R 126 R 127 R 128 R 130 R 131 R 132 R 133 R 134 R 135 R 136 R 137 R 138 R 139 R 140 R 141 R 142 R 143 R 144 R 145 R 146 R 147 R 148 R 149 R 203 R 205 R 206 R 207 R208 R210 R211 R 212 R 214 R 215 R 216

B OA RD

SC HEM NUMBER

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

CI R C U IT NUMBER

R217 R219 R220 R221 R222 R225 R226 R227 R231 R 232 R 233 R 234 R 235 R 236 R 237 R 238 R 239 R 240 R 241 R 242 R 243 R 244 R 245 R 246 R 247 R 248 R 249 R 625 R 626 R 627 R 628 R629 R630 R631 R633 R636 R677 R679 R684 R 686

SC HEM NUMBER

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 8 8 8 8 8 5 5 7 8 8 8 7 8

CIR C U IT NUMBER

R691 R720 R721 R722 R723 R724 R725 R728 R729 R730 R731 R732 R733 R 734 R 736 R 737 R 738 R 739 R 741 R T144 RT244 S105 S205 S630 S734 U 120 U 145 U 220 U 245 VR 122 VR 130 V8222 VR 629 W116 W734

SC HEM NUMBER

8 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 8 7 8 1 1 1 1 8 7 1 1 1 1 1 1 1 8 1 7

β114 Rl12 Rl15

RIOT R106 ω17 ύ

-

`

-

R2 σ 4 * R212 R215

No R207 R20b

$lose

3827-32

Figure 9-6.

Circuit view of Αl2-Atten uator/Sweep

b oa rd .

©Static Sensitive Devices See Maintenance Section COMPONENT NUMBER EXAMPLE Component Number

Α 23 Α 2 R 1234

ι

γ Schematic Assembly ~T_Τ Ί.~ Circuit Number Subassembly Number Num ber (if use d)

hassis-mounted components have no Assem bly prefix-see end of Replacea ble E lectrical P arts C

N umber List.

C H 1 & CH 2 ATTENUATO RS ASSEMBLY Al 1 BOARD CIRCUIT SCHEM NUMBER Ι LOCATION 1 LOCATION C101 C102 C202

3C 2C 68

38 3Β 3C

J 2000-1

3C

3Α

Partial

CIRCUIT SCHEM NUMBER Ι LOCATION

J 2000-2 J 2000-3 J 2000-4 J 2000-5 J 2000-6

2C 2C 7C 7C 6C

BOARD LOCATION 38 38 3C 3C 3C

CIRCUIT SCHEM BOARD NUMBER Ι LOCATION Ι LOCATION R100 R102 R200 R202

28 2C 6Β 6C

3Α 3Β 3C 3C

CIRCUIT NUMBER S101 S201

SCHEM BOARD LOCATION Ι LOCATION 2Β 7Β

38 3C

Α 1 1 also shown on diagrams 2, 3, 4, 5, 6, 7, 8 and 9 .

ASSEMBLY Al 2 CIRCUIT NUMBER C104 C105 C107 C110 C111 C112 C119 C121 C123 C125 C132 C133 C134 C136 C137 C139 C140 C141 C142 C144 C204 C205 C207 C210 C211 C212 C219 C221 C225 C232 C233 C234 C236 C237 C239 C241 C242 C244 CR119 CR219

SCHEM BOARD LOCATION Ι LOCATION

SCHEM LOCATION

BOARD LOCATION

CIRCUIT NUMBER

2E 2E 3E 3E 3E 3E 2G 2G 8D 3Η 5G 21 41 9D 8D 3-1 2Ν 2Κ 2Ν 4L 7E 7E 7E 8Ε 7E 8Ε 7G 6G 8Η 6G 71 81 9D 8D 81 7Κ 7Ν SL

3Β 38 3Β 3Α 3Α 3Α 28 28 1Β 2Α 1Α 2Α 1Α 1C 1Β 3Α 1Β 2Β 28 28 3C 3D 3D 3C 3C 3C 2C 2C 2C 1C 2C 1C 1C 1D 3C 2C 2D 2D

Ρ 1010-1 Ρ 1010-2 Ρ 1010-3 Ρ 1010-4 Ρ2000-1 Ρ2000-2 Ρ20 Ο0-3 Ρ2000-4 Ρ20 Ο0-5 Ρ 2000-6 Ρ 2010-1 Ρ 2010-2 Ρ 2010-3 Ρ 2010-4

2Ν 2Ν 4Ν 4Ν 3C 2C 2C 7C 7C 6C 6Ν 7Ν 9Ν 9Ν

18 18 1Β 1Β 4Α 4Α 4Β 4C 4C 4C 7C 1C 1C 1C

0122 0125 Q133 Q134 Q139 Ο 222 0225 Ο 233 Q234 0239

2Η 4Η 2Η 4Η 31 7Η 8Η 7Η 8Η 81

2Β 1Α 2Α 2Α 2Α 2C 2C 2C 2C 2C

3Η 8G

2Α 2C

R103 R105 R106 R107 R108 R110 Rill R112 R114 R115 R116 R117 R119 R120 R121 R122

2E 2E 2E 3F 2F 3E 3E 3E 3F 3F 2G 2G 2G 3G 3G 2Η

38 38 38 36 38 4Α 3Α 3Α 3Α 3Α 38 28 28 2Β 2Β 2Α

CIRCUIT SCHEM BOARD NUMBER Ι LOCATION Ι LOCATION

BOARD CIRCUIT SCHEM NUMBER Ι LOCATION Ι LOCATION

R 123

R 225

R226 R227 R231 R232 8233 R234 R235 R236 R237 R 238 R239 R240 R241 R242 R243 R244 R245 R246 R247 R248 R249

8Η 9Η 8Η 6Η 6G 71 8Η 81 9C 9C 9Κ 71 7Κ 7Κ 7Κ 9Κ 8Ν 8Ν 9Κ 9L 9L 8Ν

2C 1C 1C 1C 1C 1C 1C 2C 1C 1C 1D 2C 2C 2C 2D 2C 2D 1D 2C 1C 1C 2D

RT144 RT244

3Ν ΒΝ

2Β 2D

S105A S105B S205A S205B

1E 7Κ 5E 5Κ

38 38 3C 3C

U 120 U 145 υ 220 U 245

2G 21 7G 7L

28 2Β 2D 2D

VR122 VR130 VR222

21 6Η 61

2Α 1Α 2C

W 116

2G

38

R124 R125 R126 R127 R128 R130 R131 R132 R133 R 134 R135 R136 R137 R138 R139 R140 R141 R142 R143 R144 R145 R146 R147 R148 R149 R203 R205 Ρ 206 R207 R208 R210 R211 R212 R214 R215 R216 R217 R219 R220 R221 R222

8C 61 3Η 4Η 4Η 6-1 5Η 5Η 5G 21 4Η 31 9C 8C 5Κ 2J 3Κ 3Κ 2Κ 4Κ 3Ν 3Ν 4Κ 4L 41 3Ν 6E 7E 7E 7F 7F 7E 8Ε 8Ε SF 7F 7G 7G 7G 8G 6G 6Η

18 2Β 2Α 1Β 1Α 2D 1Α 1Α 1Α 1Α 1Α 2Α 1C 1C 1Β 2Α 2Α 2Β 2Β 2Α 28 18 28 1Β 18 28 4C 3D 3D 3C 3C 4C 2C 3C 3C 3C 3C 2C 2C 2C 2C 2C

Partial Α 12 also shown on diagrams 5, 7 and 8.

CHASSIS CIRCUIT NUMBER

J 1001 J 2001

MOUNTED

PARTS

SCHEM

BOARD

2Α 7Α

CHASSIS

LOCATION Ι LOCATION CHASSIS

CIRCUIT NUMBER R 101

R201

Ι

SCHEM Ι BOARD LOCATION LOCATION 2Α 7Α

CHASSIS

CHASSIS

CIRCUIT Ι SCHEM NUMBER LOCATION I LOCATION

CIRCUIT Ι SCHEM Ι BOARD LOCATION LOCATION NUMBER

77 2 5 10

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