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The Twelfth International Symposium on High-Performance Computer Architecture, 2006. 11-15 Feb. 2006 Filter Results Search within results:

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Efficient instruction schedulers for SMT processors

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J. J. Sharkey ; D. V. Ponomarev Publication Year: 2006, Page(s):288 - 298 Cited by: Papers (9)

B. Lee (1) Y. Zhang (1)

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Abstract | PDF (420 KB) |

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J. Yang (1) J. Li (1)

Speculative synchronization and thread management for fine granularity threads

J. E. Smith (1) W. Jiang (1)

A. Gontmakher ; A. Mendelson ; A. Schuster ; G. Shklover Publication Year: 2006, Page(s):278 - 287 Cited by: Papers (2)

J. E. Moreira (1) P. Stenstrom (1) R. Yavatkar (1) M. J. Thazhuthaveetil (1) M. Valero (1) A. Aggarwal (1)

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Abstract | PDF (603 KB) |

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The common case transactional behavior of multithreaded programs

R. Gonzalez (1) M. D. Hill (1)

J. W. Chung ; H. Chafi ; C. C. Minh ; A. McDonald ; B. Carlstrom ; C. Kozyrakis ; K. Olukotun Publication Year: 2006, Page(s):266 - 277 Cited by: Papers (18) | Patents (10)

A. Garg (1) G. Gu (1) A. Schuster (1) M. Huang (1) Youngjae Kim (1)

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Abstract | PDF (271 KB) |

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D. A. Wood (1) P. Emma (1)

LogTM: log-based transactional memory

S. Hu (1)

K. E. Moore ; J. Bobba ; M. J. Moravan ; M. D. Hill ; D. A. Wood Publication Year: 2006, Page(s):254 - 265 Cited by: Papers (174) | Patents (40)

B. Zhang (1) W. Shi (1) M. Gupta (1)

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Abstract | PDF (300 KB) |

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AFFILIATION

Software-hardware cooperative memory disambiguation

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Dept. of Comput. Sci., Illinois Univ., Urbana, IL, USA (2) Dept. of Comput. Sci., Wisconsin Univ., Madison, WI, USA (2) IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA (1) Dept. of Electr. Eng., Princeton Univ., NJ, USA (1) Stanford Univ., CA, USA (1) Comput. Syst. Lab., Stanford Univ., CA, USA (1) Dept. of Comput. Sci., Virginia Univ., Charlottesville, VA, USA (1) Technion-Israel Inst. of Technol., Haifa, Israel (1) Georgia Inst. of Technol., Atlanta, GA, USA (1) Dept. of Comput. Sci., Princeton Univ., NJ, USA (1) Chalmers Univ. of Technol., Goteborg, Sweden (1) Dept. of Comput. Sci., Pennsylvania State Univ., University Park, PA, USA (1) Dept. of Comput. Sci., State Univ. of New York, Binghamton, NY, USA (1) Dept. of Comput. Sci. & Autom., Indian Inst. of Sci., Bangalore, India (1) Illinois Univ., Champaign, IL, USA (1)

R. Huang ; A. Garg ; M. Huang Publication Year: 2006, Page(s):244 - 253 Cited by: Papers (4) |

Abstract | PDF (472 KB) |

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CORD: cost-effective (and nearly overhead-free) orderrecording and data race detection M. Prvulovic Publication Year: 2006, Page(s):232 - 243 Cited by: Papers (30) | Patents (1) |

Abstract | PDF (408 KB) |

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Dept. d'Arquitectura de Computadors, Univ. Politecnica de Catalunya, Barcelona, Spain (1) Adv. Comput. Archit. Lab., Michigan Univ., Ann Arbor, MI, USA (1) Comput. Syst. Lab., Cornell Univ., Ithaca, NY, USA (1) Dept. of Electr. & Comput. Eng., Rochester Univ., NY, USA (1) Dept. of Electr. & Comput. Eng., Binghamton Univ., NY, USA (1) VSSAD, Intel Corp., USA (1) ECE Dept., Binghamton Univ., NY, USA (1) Sch. of Electr. & Comput. Eng., Georgia Tech., GA, USA (1)

CONFERENCE LOCATION

Austin, TX (3)

W. Shi ; J. B. Fryman ; G. Gu ; H. -H. S. Lee ; Y. Zhang ; J. Yang Publication Year: 2006, Page(s):222 - 231 Cited by: Papers (3)

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Abstract | PDF (323 KB) |

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2016 IEEE International Symposium on High Performance Computer Architecture (HPCA) 2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA) 2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA) 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA) more...

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Reducing resource redundancy for concurrent error detection techniques in high performance microprocessors Sumeet Kumar ; Aneesh Aggarwal Publication Year: 2006, Page(s):212 - 221 Cited by: Papers (8) | Patents (1) |

Abstract | PDF (881 KB) |

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ReViveI/O: efficient handling of I/O in highly-available rollbackrecovery servers J. Nakano ; P. Montesinos ; K. Gharachorloo ; J. Torrellas Publication Year: 2006, Page(s):200 - 211 Cited by: Papers (15) | Patents (1) |

Abstract | PDF (284 KB) |

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Industrial Perspectives: The Next Roadblocks in SOC Evolution: On-Chip Storage Capacity and Off-Chip Bandwidth P. Emma Publication Year: 2006, Page(s): 201 | PDF (61 KB) |

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Industrial Perspectives: System IO Network Evolution Closing Requirement Gaps R. Recio Publication Year: 2006, Page(s): 201 HTML

Industrial Perspectives: Platform Design Challenges with Many cores

2017 IEEE International Symposium on High Performance Computer Architecture (HPCA)

High-Performance Computer Architecture (HPCA), 2006 12th International Symposium on Print Purchase at Partner

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Previous Titles

The proceedings of this conference will be available for purchase through Curran Associates.

InfoShield: a security architecture for protecting information usage in memory

Coll. of Comput., Georgia Inst. of Technol., Atlanta, GA, USA (1) ECE Dept., North Carolina State Univ., Raleigh, NC, USA (1)

Proceedings Available

R. Yavatkar Publication Year: 2006, Page(s): 201 Cited by: Papers (1) | PDF (61 KB) |

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High performance file I/O for the Blue Gene/L supercomputer H. Yu ; R. K. Sahoo ; C. Howson ; G. Almasi ; J. G. Castanos ; M. Gupta ; J. E. Moreira ; J. J. Parker ; T. E. Engelsiepen ; R. B. Ross ; R. Thakur ; R. Latham ; W. D. Gropp Publication Year: 2006, Page(s):187 - 196 Cited by: Papers (22) |

Abstract | PDF (726 KB) |

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Understanding the performance-temperature interactions in disk I/O of server workloads Youngjae Kim ; Sudhanva Gurumurthi ; Anand Sivasubramaniam Publication Year: 2006, Page(s):176 - 186 Cited by: Papers (20) | Patents (1) |

Abstract | PDF (576 KB) |

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Completely verifying memory consistency of test program executions C. Manovit ; S. Hangal Publication Year: 2006, Page(s):166 - 175 Cited by: Papers (12) |

Abstract | PDF (704 KB) |

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Retention-aware placement in DRAM (RAPID): software methods for quasi-non-volatile DRAM R. K. Venkatesan ; S. Herr ; E. Rotenberg Publication Year: 2006, Page(s):155 - 165 Cited by: Papers (63) | Patents (9) |

Abstract | PDF (732 KB) |

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Increasing the cache efficiency by eliminating noise P. Pujara ; A. Aggarwal Publication Year: 2006, Page(s):145 - 154 Cited by: Papers (9) |

Abstract | PDF (848 KB) |

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DMA-aware memory energy management Vivek Pandey ; W. Jiang ; Y. Zhou ; R. Bianchini Publication Year: 2006, Page(s):133 - 144 Cited by: Papers (20) | Patents (1) |

Abstract | PDF (559 KB) |

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Phase characterization for power: evaluating control-flowbased and event-counter-based techniques C. Isci ; M. Martonosi Publication Year: 2006, Page(s):121 - 132 Cited by: Papers (33) |

Abstract | PDF (509 KB) |

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Probabilistic counter updates for predictor hysteresis and stratification N. Riley ; C. Zilles Publication Year: 2006, Page(s):110 - 120 Cited by: Papers (5) | Patents (1) |

Abstract | PDF (714 KB) |

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Chip-multiprocessing and beyond P. Stenstrom Publication Year: 2006 Cited by: Papers (2) |

Abstract | PDF (59 KB)

Construction and use of linear regression models for processor performance analysis P. J. Joseph ; Kapil Vaswani ; M. J. Thazhuthaveetil Publication Year: 2006, Page(s):99 - 108 Cited by: Papers (59) |

Abstract | PDF (404 KB) |

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Last level cache (LLC) performance of data mining workloads on a CMP - a case study of parallel bioinformatics workloads A. Jaleel ; M. Mattina ; B. Jacob Publication Year: 2006, Page(s):88 - 98 Cited by: Papers (35) | Patents (4) |

Abstract | PDF (483 KB) |

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Dynamic power-performance adaptation of parallel computation on chip multiprocessors J. Li ; J. F. Martinez Publication Year: 2006, Page(s):77 - 87 Cited by: Papers (51) | Patents (6) |

Abstract | PDF (549 KB) |

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Store vectors for scalable memory dependence prediction and scheduling Samantika Subramaniam ; G. H. Loh Publication Year: 2006, Page(s):65 - 76 Cited by: Papers (5) |

Abstract | PDF (354 KB) |



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The Twelfth International Symposium on High - IEEE Xplore

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