VHDL Multiplier Example [PDF]

Q0: in std_logic;. --LSB of multiplier. Start: in std_logic;. --start algorithm. Load: out std_logic;. --Load M,Q; Clear

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Idea Transcript


VHDL Modeling for Synthesis Hierarchical Design Textbook Section 4.8: Add and Shift Multiplier

“Add and shift” binary multiplication

Shift & add Shift & add

Shift & add

System Example: 8x8 multiplier Multiplicand Multiplier

LoadM

multiplicand (M)

adder (ADR)

LoadA ShiftA ClearA

Start Clock

Q0

controller (C)

Done accumulator (A)

Product

multiplier (Q)

LoadQ ShiftQ

Controller outputs in red

Roth example: Block diagram with control signals

“Add and shift” multiply algorithm (Moore model) INIT A

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